bdrv_is_allocated

Hi, I’m trying to understand this function, but seems no note in the header file, could anyone help explain this function? It will be great if there is an example. Thanks in advance! thanks

How to understand vvfat

Hello, Recently I’m learning QEMU storage. I think the two structures are very important, BlockBackend and BlockDriver. Usually BlockBackend resides in the block device structure like disk, flash etc and the block device is storage device seen by guest OS and driver. BlockDriver will handle the

Any reason we need memoryregionsection

Usually when we add memory region in the platform init process, the corresponding address range in address space will not overlap with others, I’m not sure in which case we should use MemoryRegionSection? Thanks

Re: Fill tlb for data and io address

> 在 2021年2月16日，下午7:48，Peter Maydell 写道： > > On Tue, 16 Feb 2021 at 11:28, 沈梦姣 wrote: >> Look at the store/load helper, it will use the tlb entry to do the address >> translation(from guest virtual address to host virtual address) but where >> the tlb is fil

Fill tlb for data and io address

Look at the store/load helper, it will use the tlb entry to do the address translation(from guest virtual address to host virtual address) but where the tlb is filled for the data ram and io address, I know where the code ram is filled(tb_find->tb_lookup__cpu_state...) Thanks a lot

Re: How to copy data between guest memory and host

By the way, I’m using TCG mode. Thanks > 在 2020年11月18日，下午3:44，沈梦姣 写道： > > Hi, > I’m adding device for one platform(e.g. mps2), and also writing driver for > that device on guest os. There is a buffer allocated in qemu where some data > will be cooked, and driver

How does the TB chaining works?

I just see the current TB’s code pointer given to prologue which works as function call. But how to jump to the next TB to execution instead exit the execution and entry the prologue again?

Re: How the cpu_R in DisasContext is associated with register of CPUArchState

:40，Peter Maydell 写道： > > On Fri, 3 Jul 2020 at 15:15, 沈梦姣 wrote: >> >> Because in translate stage when write cpu register by guest code, it >> operates totally on cpu_R of DisasContext, how to reflect it to register of >> CPUArchState? > > You don'

How the cpu_R in DisasContext is associated with register of CPUArchState

Because in translate stage when write cpu register by guest code, it operates totally on cpu_R of DisasContext, how to reflect it to register of CPUArchState? thanks a lot!