[PATCH 1/2] target/sparc: Loosen decode of STBAR for v8

Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 13 and bits 12-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). Fi

[PATCH 0/2] target/sparc: Loosen decode of STBAR/RDY for v7/v8

Hi Mark, Here's an alternative to your recent STBAR patch. It goes further and adjusts RDY as well for really old machines. r~ Richard Henderson (2): target/sparc: Loosen decode of STBAR for v8 target/sparc: Loosen decode of RDY for v7 target/sparc/translate.c | 36

Re: [PULL 01/30] lcitool: use newer Rust for Debian and Ubuntu

Big-endian MIPS is already deprecated in preparation for Trixie. Until it's removed we can keep that target, or all cross-build testing as you suggested, on Bookworm. Paolo On Thu, Sep 4, 2025 at 9:39 PM Marc-André Lureau wrote: > > Hi > > On Wed, Sep 3, 2025 at 5:59 PM Paolo Bonzini wrote: > >

[PATCH v4 1/4] linux-user: Create vdso_sigreturn_region_{start,end}

These variables will be populated from the vdso, and used for detecting whether we are executing the sigreturn. Signed-off-by: Richard Henderson --- linux-user/loader.h| 2 ++ linux-user/signal-common.h | 2 ++ linux-user/elfload.c | 5 + linux-user/gen-vdso.c

[PATCH v6 07/25] target/avr: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places the hook for AVR targets. That architecture appears to only

[PATCH] bql: Fix bql_locked status with condvar APIs

QEMU has a per-thread "bql_locked" variable stored in TLS section, showing whether the current thread is holding the BQL lock. It's a pretty handy variable. Function-wise, QEMU have codes trying to conditionally take bql, relying on the var reflecting the locking status (e.g. BQL_LOCK_GUARD), or

[PATCH v6 17/25] target/rx: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for Renesas Xtreme targets. Reviewed-by: Richard Hen

Re: [PATCH] target/sparc: allow partial decode of v8 STBAR instructions

On 04/09/2025 17:44, Richard Henderson wrote: On 9/4/25 18:10, Mark Cave-Ayland wrote: Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 14 and bits 13-0 of the "Read Stat

[PATCH v2] target/sparc: allow partial decode of v8 STBAR instructions

Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 14 and bits 13-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). In

[PATCH v6 19/25] target/sh4: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for SuperH targets. Reviewed-by: Richard Henderson

[PATCH v6 25/25] tests: add test with interrupted memory accesses on rv64

This test aims at catching API misbehaviour w.r.t. the interaction between interrupts and memory accesses, such as the bug fixed in 27f347e6a1d269c533633c812321cabb249eada8 Because the condition for triggering misbehaviour may not be deterministic and the cross-section between memory accesses

[PATCH v6 21/25] target/tricore: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places an exception hook for TriCore targets. Interrupts are not i

[PATCH v6 24/25] tests: add test for double-traps on rv64

We do have a number of test-case for various architectures exercising their interrupt/exception logic. However, for the recently introduced trap API we also want to exercise the logic for double traps on at least one architecture. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Julian Ganz -

[PATCH v6 16/25] target/riscv: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for RISC-V targets. Reviewed-by: Daniel Henrique Bar

[PATCH v6 04/25] contrib/plugins: add plugin showcasing new dicontinuity related API

We recently introduced new plugin API for registration of discontinuity related callbacks. This change introduces a minimal plugin showcasing the new API. It simply counts the occurances of interrupts, exceptions and host calls per CPU and reports the counts when exitting. Reviewed-by: Pierrick Bo

[PATCH v6 18/25] target/s390x: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for IBM System/390 targets. We treat "program interru

[PATCH v6 22/25] target/xtensa: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for xtensa targets. Reviewed-by: Max Filippov Signe

[PATCH v6 13/25] target/mips: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for MIPS targets. We consider the exceptions NMI and

[PATCH v6 06/25] target/arm: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for ARM (and Aarch64) targets. We decided to treat th

[PATCH v6 10/25] target/loongarch: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for loongarch targets. This architecture has one spec

[PATCH v6 05/25] target/alpha: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for Alpha targets. Reviewed-by: Richard Henderson S

[PATCH v6 20/25] target/sparc: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for SPARC (32bit and 64bit) targets. We treat any int

[PATCH v6 23/25] tests: add plugin asserting correctness of discon event's to_pc

We recently introduced plugin API for the registration of callbacks for discontinuity events, specifically for interrupts, exceptions and host call events. The callback receives various bits of information, including the VCPU index and PCs. This change introduces a test plugin asserting the correc

[PATCH v6 03/25] plugins: add hooks for new discontinuity related callbacks

The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. In addition, we recently introduced API for registering callbacks for discontinuity events, specifically for interrupts, exceptions and host calls. This change introduces the

[PATCH v6 09/25] target/i386: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places the hook for x86 targets. Signed-off-by: Julian Ganz ---

Re: [PATCH v2 2/4] target/ppc: Add IBM PPE42 special instructions

On 8/27/25 01:47, Glenn Miles wrote: Adds the following instructions exclusively for IBM PPE42 processors: LSKU LCXU STSKU STCXU LVD LVDU LVDX STVD STVDU STVDX SLVD SRVD CMPWBC CMPLWBC CMPWIBC BNBWI BNBW CLRBWIBC CLRWBC DCBQ RLDICL

[PATCH v6 14/25] target/openrisc: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for OpenRISC targets. We treat anything other than re

[PATCH v6 12/25] target/microblaze: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places the hook for MicroBlaze targets. This architecture has one

[PATCH v6 15/25] target/ppc: call plugin trap callbacks

We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for Power PC targets. Signed-off-by: Julian Ganz --

[PATCH v6 02/25] plugins: add API for registering discontinuity callbacks

The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. In addition to those events, we recently defined discontinuity events, which include traps. This change introduces a function to register callbacks for these events. We define

[PATCH v6 01/25] plugins: add types for callbacks related to certain discontinuities

The plugin API allows registration of callbacks for a variety of VCPU related events, such as VCPU reset, idle and resume. However, traps of any kind, i.e. interrupts or exceptions, were previously not covered. These kinds of events are arguably quite significant and usually go hand in hand with a

Re: [PATCH v2 2/4] target/ppc: Add IBM PPE42 special instructions

On Thu, 2025-09-04 at 18:00 +0530, Chinmay Rath wrote: > On 8/27/25 01:47, Glenn Miles wrote: > > Adds the following instructions exclusively for > > IBM PPE42 processors: > > > >LSKU > >LCXU > >STSKU > >STCXU > >LVD > >LVDU > >LVDX > >STVD > >STVDU > >STVDX

Re: [PULL 01/30] lcitool: use newer Rust for Debian and Ubuntu

Hi On Wed, Sep 3, 2025 at 5:59 PM Paolo Bonzini wrote: > > On 9/3/25 15:54, Marc-André Lureau wrote: > > Hi Paolo > > > > On Tue, May 6, 2025 at 7:30 PM Paolo Bonzini wrote: > >> > >> On Debian, the rustc-web package provides a newer Rust compiler (1.78) > >> for all architectures except mips64e

Re: [PATCH v3 10/12] target/loongarch: Invalid tlb entry in invalidate_tlb()

On 2025/9/3 下午9:00, Richard Henderson wrote: On 9/3/25 10:48, Bibo Mao wrote: Invalid tlb entry in function invalidate_tlb(), and its usage is simple and easy to use. Signed-off-by: Bibo Mao ---   target/loongarch/tcg/tlb_helper.c | 2 +-   1 file changed, 1 insertion(+), 1 deletion(-) diff

Re: [PATCH 2/3] target/risvc: Fix vector whole ldst vstart check

Alex, Richard, On 9/4/25 2:16 AM, Nicholas Piggin wrote: On Wed, Sep 03, 2025 at 05:13:36PM -0300, Daniel Henrique Barboza wrote: Hi Nick, ^ typo in the patch subject: s/risvc/riscv Well I'm off to a fine start :/ On 9/3/25 12:01 AM, Nicholas Piggin wrote: The whole vector ldst instructi

Re: [PATCH] hw/riscv/riscv-iommu: Fix MSI table size limit

On 9/4/25 10:27 AM, Andrew Jones wrote: The MSI table is not limited to 4k. The only constraint the table has is that its base address must be aligned to its size, ensuring no offsets of the table size will overrun when added to the base address (see "8.5. MSI page tables" of the AIA spec). F

[PATCH v7 1/2] target/riscv: Use tcg nodes for strided vector ld/st generation

This commit improves the performance of QEMU when emulating strided vector loads and stores by substituting the call for the helper function with the generation of equivalent TCG operations. PS: An implementation is permitted to cause an illegal instruction if vstart is not 0 and it is set to a v

[PATCH v2 024/281] tests/functional: Move m68k tests into architecture specific folder

From: Thomas Huth The tests/functional folder has become quite crowded, thus move the m68k tests into a target-specific subfolder. Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth Message-ID: <20250819112403.432587-13-th...@redhat.com> --- MAINTAIN

[PATCH v4 0/3] vfio-user client functional test

Add a basic functional test for the vfio-user client, along with a couple of test framework extensions to support it. v4: generalize the test so it's less sensitive to build/environment John Levon (2): tests/functional: return output from cmd.py helpers tests/functional: add vm param to cmd.p

[PATCH v2 006/281] Update version for the v10.1.0 release

From: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index dadcbd47d3c..4149c39eec6 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -10.0.94 +10.1.0 -- 2.47.2

Re: [RFC PATCH v3 3/3] target/riscv: Expose Zvqdotq extension as a cpu property

On 9/3/25 11:03 AM, Max Chou wrote: Signed-off-by: Max Chou --- Reviewed-by: Daniel Henrique Barboza target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 95edd02e68..ed486113ba 100644 --- a/target/riscv/cpu.c +++ b/target

[PATCH v2 004/281] python: mkvenv: fix messages printed by mkvenv

From: Paolo Bonzini The new Matcher class does not have a __str__ implementation, and therefore it prints the debugging representation of the internal object: $ ../configure --enable-rust && make qemu-system-arm --enable-download python determined to be '/usr/bin/python3' python version: P

[PATCH v2 059/281] linux-user: Move get_elf_hwcap to sh4/elfload.c

From: Richard Henderson Change the return type to abi_ulong, and pass in the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/loader.h | 3 ++- linux-user/sh4/target_elf.h | 2 ++ linux-user/elfload.c| 29 + linux-us

Re: [PATCH v6 1/2] target/riscv: Generate strided vector loads/stores with tcg nodes.

On 2025/9/4 12:37, Nicholas Piggin wrote: > On Wed, Sep 03, 2025 at 09:52:01PM +0800, Chao Liu wrote: >> From: Chao Liu >> >> This commit improves the performance of QEMU when emulating strided vector >> loads and stores by substituting the call for the helper function with the >> generation of

[PATCH v2 076/281] linux-user/aarch64: Create init_main_thread

From: Richard Henderson Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 14 ++ linux-user/elfload.c | 10 +- 2

Re: [PATCH v3 2/4] hw/acpi: Introduce the QEMU Battery

On Thu, 28 Aug 2025 01:00:48 +0300 Leonid Bloch wrote: > The battery device communicates battery state to the guest via ACPI. > It supports two modes of operation: > > 1. QMP control mode (default): Battery state is controlled programmatically >via QMP commands, making the device determinist

[PATCH v6 10/11] target/loongarch:Implement csrrd CSR_MSGIR register

implement the read-clear feature for CSR_MSGIR register. Signed-off-by: Song Gao --- target/loongarch/csr.c| 5 + target/loongarch/tcg/csr_helper.c | 21 +++ target/loongarch/tcg/helper.h | 1 + .../tcg/insn_trans/trans_pr

Re: [PATCH RFC 0/9] migration: Threadify loadvm process

On Thu, Aug 28, 2025 at 4:59 AM Peter Xu wrote: > > [this is an early RFC, not for merge, but to collect initial feedbacks] > > Background > == > > Nowadays, live migration heavily depends on threads. For example, most of > the major features that will be used nowadays in live migration (m

[PATCH 5/5] hw/gpio/npcm8xx: Implement npcm sgpio device input pin logic

Signed-off-by: Coco Li Reviewed-by: Hao Wu --- hw/gpio/npcm8xx_sgpio.c | 134 --- include/hw/gpio/npcm8xx_sgpio.h | 4 +- tests/qtest/npcm8xx_sgpio-test.c | 180 ++- 3 files changed, 274 insertions(+), 44 deletions(-) diff --git a/hw/g

Re: [PATCH v6 1/2] target/riscv: Generate strided vector loads/stores with tcg nodes.

On Wed, Sep 03, 2025 at 09:52:01PM +0800, Chao Liu wrote: > From: Chao Liu > +static void gen_ldst_stride_main_loop(DisasContext *s, TCGv dest, uint32_t > rs1, > + uint32_t rs2, uint32_t vm, uint32_t nf, > + gen_tl_ldst *l

[PATCH 2/5] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property

From: Felix Wu - Added qtests to test gpio-set property for ASPEED. - Added function to get uint in qdict. Signed-off-by: Felix Wu --- include/qobject/qdict.h| 1 + qobject/qdict.c| 13 tests/qtest/aspeed_gpio-test.c | 105 ++--- 3

Re: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3 accel device

Hi Shameer, On 7/16/25 11:27 AM, Shameerali Kolothum Thodi wrote: > >> -Original Message- >> From: Duan, Zhenzhong >> Sent: Wednesday, July 16, 2025 4:39 AM >> To: Nicolin Chen >> Cc: Shameerali Kolothum Thodi >> ; qemu-...@nongnu.org; >> qemu-devel@nongnu.org; eric.au...@redhat.com; >>

Re: [RFC PATCH 0/4] migration: Introduce postcopy-setup capability and state

Hello Dave, On 2025-09-03 12:00, Dr. David Alan Gilbert wrote: > * Juraj Marcin (jmar...@redhat.com) wrote: > > Hi Dave, > > > > On 2025-09-01 17:57, Dr. David Alan Gilbert wrote: > > > * Peter Xu (pet...@redhat.com) wrote: > > > > On Thu, Aug 14, 2025 at 05:42:23PM +0200, Juraj Marcin wrote: > >

[PATCH v2 001/281] target/i386: Add support for save/load of exception error code

From: Xin Wang For now, qemu save/load CPU exception info(such as exception_nr and has_error_code), while the exception error_code is ignored. This will cause the dest hypervisor reinject a vCPU exception with error_code(0), potentially causing a guest kernel panic. For instance, if src VM stopp

[PATCH v2 032/281] tests/functional: Move sh4/sh4eb tests into target-specific folders

From: Thomas Huth The tests/functional folder has become quite crowded, thus move the sh4 tests into a target-specific subfolder. Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth Message-ID: <20250819112403.432587-21-th...@redhat.com> --- MAINTAINE

Re: [PATCH v3 3/3] hw/loongarch/virt: Register reset interface with CPU object

On Wed, 3 Sep 2025 10:35:56 +0800 Bibo Mao wrote: > With cpu hotplug is implemented on LoongArch virt machine, reset > interface with hot-added CPU should be registered. Otherwise there > will be problem if system reboots after cpu is hot-added. > > Now register reset interface with CPU object

Re: [PATCH v2 001/281] target/i386: Add support for save/load of exception error code

On Thu, 4 Sep 2025 09:06:35 +0100 Alex Bennée wrote: > From: Xin Wang > > For now, qemu save/load CPU exception info(such as exception_nr and > has_error_code), while the exception error_code is ignored. This will > cause the dest hypervisor reinject a vCPU exception with error_code(0), > pote

Re: [PATCH] target/sparc: allow partial decode of v8 STBAR instructions

On 9/4/25 18:10, Mark Cave-Ayland wrote: Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 14 and bits 13-0 of the "Read State Register Instructions" are notionally zero, th

[PATCH v2 1/4] hw/arm: use g_autofree for filename in arm_load_dtb

The function has quite a number of exit cases so lets try and clean things up with g_autofree. As the fdt hasn't be allocated yet we can return directly from the fail point. Reviewed-by: Richard Henderson Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée --- hw/arm/boot.c | 8 +++

[PATCH] ui/spice: fix crash when disabling GL scanout on

From: Marc-André Lureau When spice_qxl_gl_scanout2() isn't available, the fallback code incorrectly handles NULL arguments to disable the scanout, leading to: Program terminated with signal SIGSEGV, Segmentation fault. #0 spice_server_gl_scanout (qxl=0x55a25ce57ae8, fd=0x0, width=0, height=0,

[PATCH v2 055/281] linux-user: Move get_elf_hwcap to sparc/elfload.c

From: Richard Henderson Change the return type to abi_ulong, and pass in the cpu. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/loader.h | 3 ++- linux-user/sparc/target_elf.h | 2 ++ linux-user/elfload.c | 30 +- l

[PATCH] linux-user: Add missing includes

scall.c +++ b/linux-user/syscall.c @@ -101,6 +101,7 @@ #include #include #include +#include #include #include #if defined(CONFIG_FIEMAP) --- base-commit: baa79455fa92984ff0f4b9ae94bed66823177a27 change-id: 20250904-includes-19d9afaed67a Best regards, -- Peter Foley

[PATCH v2 071/281] linux-user: Move target_cpu_copy_regs decl to qemu.h

From: Richard Henderson The function is not used by bsd-user, so placement within include/user/cpu_loop.h is not ideal. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/user/cpu_loop.h | 4 linux-user/qemu.h | 3 +++ 2 files changed, 3 insertions(+), 4 deleti

[PATCH v2 034/281] tests/functional: Move x86_64 tests into target-specific folder

From: Thomas Huth The tests/functional folder has become quite crowded, thus move the x86_64 tests into a target-specific subfolder. Reviewed-by: Pierrick Bouvier Signed-off-by: Thomas Huth Message-ID: <20250819112403.432587-23-th...@redhat.com> --- MAINTAINERS

[PATCH v2 069/281] linux-user: Remove ELF_PLATFORM

From: Richard Henderson All real definitions of ELF_PLATFORM are now identical, and the stub definitions are NULL. Use HAVE_ELF_PLATFORM and provide a stub as a fallback definition of get_elf_platform. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/elfload.c | 18

RE: [PATCH v5 11/21] intel_iommu: Handle PASID entry removal and update

>-Original Message- >From: Liu, Yi L >Subject: Re: [PATCH v5 11/21] intel_iommu: Handle PASID entry removal and >update > >On 2025/9/1 11:31, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Liu, Yi L >>> Subject: Re: [PATCH v5 11/21] intel_iommu: Handle PASID entry

[PATCH v2 007/281] Open 10.2 development tree

From: Stefan Hajnoczi Signed-off-by: Stefan Hajnoczi --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 4149c39eec6..9856be5dd98 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -10.1.0 +10.1.50 -- 2.47.2

[PATCH] Use meson's detected python installation

dcc73909c6133f5460..6bf72a69060414ba1b7c1857515eeceb5a2c7b7c 100644 --- a/plugins/meson.build +++ b/plugins/meson.build @@ -6,7 +6,7 @@ qemu_plugin_symbols = configure_file( input: files('../include/qemu/qemu-plugin.h'), output: 'qemu-plugin.symbols', capture: true, - command: [files('../scripts/qemu-plugin-symbols.py'), '@INPUT@']) + command: [python, files('../scripts/qemu-plugin-symbols.py'), '@INPUT@']) # Modules need more symbols than just those in plugins/qemu-plugins.symbols if not enable_modules --- base-commit: baa79455fa92984ff0f4b9ae94bed66823177a27 change-id: 20250904-python-78ccebd0fded Best regards, -- Peter Foley

Re: Issues with pdcm in qemu 10.1-rc on migration and save/restore

Hello, In addition to my previous mail describing the issue on different Ubuntu releases, I went further by testing directly qemu upstream at HEAD (baa79455fa92984ff0f4b9ae94bed66823177a27) As the start version for the migration, I take quite recent release v10.0.x to make the version gap smalle

Re: [RFC PATCH v2 8/9] hw/misc: add test device for memory access

On Mon, Sep 01, 2025 at 06:03:41PM +0100, Peter Maydell wrote: > Could we have a comment in this header file that documents > what interface the test device presents to tests, please? > Both this patch and the test-case patch are hard to > review, because I don't know what the test device is > tryi

[PATCH v2 3/5] tests/guest-debug: Add quiet option to run-tests.py

Add a --quiet option to run-tests.py so it can run without printing any messages to the stdout. Signed-off-by: Gustavo Romero --- tests/guest-debug/run-test.py | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-tes

Re: [RFC PATCH v3 05/15] hw/arm/smmuv3-accel: Introduce smmuv3 accel device

On 7/14/25 7:23 PM, Nicolin Chen wrote: > On Mon, Jul 14, 2025 at 04:59:31PM +0100, Shameer Kolothum wrote: >> Also setup specific PCIIOMMUOps for accel SMMUv3 as accel >> SMMUv3 will have different handling for those ops callbacks >> in subsequent patches. >> >> The "accel" property is not yet

[PATCH v2 4/5] tests/functional: Support tests that require a runner

Add support for running tests that require a specific runner. The test is specified via a tuple (name, runner, protocol), where name is the test name as found in the tests/functional directory without the 'test_' prefix and the .py extension, runner is an array containing the runner and any argume

Re: [PATCH v2 0/8] virtio-net: live-TAP local migration

On 04.09.25 17:42, Lei Yang wrote: Tested the current series of patches, mixed with patches from series [1] and [2], and the virtio-net regression tests passed. I also tested local VM migration under multiple NIC queues enabled and disabled, it also passed. [1] https://patchwork.ozlabs.org/proj

[PATCH v6 01/11] target/loongarch: move some machine define to virt.h

move some machine define to virt.h Signed-off-by: Song Gao Reviewed-by: Bibo Mao --- include/hw/loongarch/virt.h | 19 +++ target/loongarch/cpu.h | 21 - 2 files changed, 19 insertions(+), 21 deletions(-) diff --git a/include/hw/loongarch/virt.h b/inclu

[PATCH v7 0/2] Generate strided vector loads/stores with tcg nodes

Hi all, Thanks Nick for the review. In patch v7: 1. Standardize the subject line of patch 1 and remove the trailing period. 2. Split into sub-functions to improve the patch's code readability and facilitate review. 3. Use more faster TCG ops, use tcg_gen_andi_tl() instead of tcg_gen_rem_tl()

Re: [RFC PATCH v3 1/3] target/riscv: Add Zvqdotq cfg property

On 9/3/25 11:03 AM, Max Chou wrote: The Zvqdotq extension is the vector dot-product extension of RISC-V. Signed-off-by: Max Chou --- target/riscv/cpu.c| 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c| 5 + 3 files changed, 7 insertio

[PATCH v6 00/11] hw/loongarch: add the advanced extended interrupt controllers (AVECINTC) support

Hi, Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECIN

Re: [PATCH v4 4/5] spdm: define SPDM transport enum types

On Thu, 4 Sep 2025 13:10:58 +1000 Wilfred Mallawa wrote: > From: Wilfred Mallawa > > SPDM maybe used over different transports, such as PCIe Data Object > Exchange (DoE) or Storage amongst others. This patch Odd line wrap. I'd also drop the 'amongst others' as 'such as' already suggests ther

[PATCH v4 4/4] linux-user: Add syscall dispatch support

From: Arusekk This commit adds support for the `prctl(PR_SET_SYSCALL_USER_DISPATCH)` function in the Linux userspace emulator. It is implemented as a fully host-independent function, by forcing a SIGSYS early during syscall handling, if the PC is outside the allowed range. Since disabled SUD is

[PATCH v4 2/4] linux-user: Populate sigreturn_region_{start, end} in all vdso.S

Mark the regions which contain sigreturn syscalls within each vdso. Rebuild the shared objects. Signed-off-by: Richard Henderson --- linux-user/aarch64/vdso-be.so | Bin 3224 -> 3320 bytes linux-user/aarch64/vdso-le.so | Bin 3224 -> 3320 bytes linux-user/aarch64/vdso.S | 2 ++ linux-u

[PATCH v4 3/4] linux-user: Populate vdso_sigreturn_region_{start, end} from sigtramp page

When a target does not support a vdso, we generate a sigtramp page. The only thing on this page is a (set of) signal return syscalls. We do not need to narrowly restrict the vdso_sigreturn_region; simply record the entire page for all such targets. Signed-off-by: Richard Henderson --- linux-user

[PATCH] target/sparc: allow partial decode of v8 STBAR instructions

Solaris 8 appears to have a bug whereby it executes v9 MEMBAR instructions when booting a freshly installed image. According to the SPARC v8 architecture manual, whilst bits 14 and bits 13-0 of the "Read State Register Instructions" are notionally zero, they are marked as unused (i.e. ignored). In

[PATCH v6 03/11] hw/loongarch: add misc register supoort avecintc

Add feature register and misc register for avecintc feature checking and setting Signed-off-by: Song Gao --- hw/loongarch/virt.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 1a2aa92c25..124f96af03 100644 --- a/hw/loongarch/virt.

[PATCH v6 11/11] hw/loongarch: Implement AVEC plug/unplug interfaces

when cpu added, connect avec irq to cpu INT_AVEC irq pin. Signed-off-by: Song Gao --- hw/intc/loongarch_avec.c | 71 hw/loongarch/virt.c | 11 +++ 2 files changed, 82 insertions(+) diff --git a/hw/intc/loongarch_avec.c b/hw/intc/loongarch_avec.c

Re: [PATCH v2] e1000e: Prevent crash from legacy interrupt firing after MSI-X enable

On 07.08.2025 14:08, Laurent Vivier wrote: A race condition between guest driver actions and QEMU timers can lead to an assertion failure when the guest switches the e1000e from legacy interrupt mode to MSI-X. If a legacy interrupt delay timer (TIDV or RDTR) is active, but the guest enables MSI-X

[PATCH v2 2/5] tests/guest-debug: Format comments

Capitalize and add periods to comments. Signed-off-by: Gustavo Romero --- tests/guest-debug/run-test.py | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index d21a5dda77..e051e8947c 100755 --- a/tests

[PATCH v2 5/5] tests/functional: Adapt reverse_debugging to run w/o Avocado

This commit removes Avocado as a dependency for running the reverse_debugging test. The main benefit, beyond eliminating an extra dependency, is that there is no longer any need to handle GDB packets manually. This removes the need for ad-hoc functions dealing with endianness and arch-specific reg

[PATCH v2 1/5] tests/guest-debug: Make QEMU optional in run-test.py

This commit makes QEMU optional in run-test.py, allowing it to be used as a GDB runner, i.e., to call GDB and pass a test script to it without launching QEMU. In this configuration, it is the test script’s duty to configure and run the VMs that GDB connects to. sys.argv passed via -ex now includes

[PATCH v2 0/5] tests/functional: Adapt reverse_debugging to run w/o Avocado

The goal of this series is to remove Avocado as a dependency for running the reverse_debugging functional test. This test, the last one I’m aware of that relies on Avocado, requires it because of the need for GDB to test reverse stepping, continue, etc. In this series, we leveraged the run-test.p

Re: [PATCH v2 0/8] virtio-net: live-TAP local migration

Tested the current series of patches, mixed with patches from series [1] and [2], and the virtio-net regression tests passed. I also tested local VM migration under multiple NIC queues enabled and disabled, it also passed. [1] https://patchwork.ozlabs.org/project/qemu-devel/cover/20250903094411.1

Re: [PATCH v3 00/19] TAP initialization refactoring

Tested the current series of patches, mixed with patches from series [1] and [2], and the virtio-net regression tests passed. I also tested local VM migration under multiple NIC queues enabled and disabled, it also passed. [1] https://patchwork.ozlabs.org/project/qemu-devel/cover/20250903094411.1

Re: [PATCH 00/10] io: deal with blocking/non-blocking fds

Tested the current series of patches, mixed with patches from series [1] and [2], and the virtio-net regression tests passed. I also tested local VM migration under multiple NIC queues enabled and disabled, it also passed. [1] https://patchwork.ozlabs.org/project/qemu-devel/cover/20250903124934.1

[PATCH] 9pfs: Include glib.h

6823177a27 change-id: 20250904-9p-11c0405ae7c5 Best regards, -- Peter Foley

Re: [PATCH v3 3/3] hw/loongarch/virt: Register reset interface with CPU object

On Thu, 4 Sep 2025 19:55:49 +0800 Bibo Mao wrote: > On 2025/9/4 下午4:13, Igor Mammedov wrote: > > On Wed, 3 Sep 2025 10:35:56 +0800 > > Bibo Mao wrote: > > > >> With cpu hotplug is implemented on LoongArch virt machine, reset > >> interface with hot-added CPU should be registered. Otherwise t

Re: [PATCH v7 1/2] target/riscv: Use tcg nodes for strided vector ld/st generation

On 9/4/25 11:13, Chao Liu wrote: +/* + * Check whether the i bit of the mask is 0 or 1. + * + * static inline int vext_elem_mask(void *v0, int index) + * { + * int idx = index / 64; + * int pos = index % 64; + * return (((uint64_t *)v0)[idx] >> pos) & 1; + * } + * + * And + * + * if (

[PATCH v3 2/2] hw/cxl: Add Physical Port Control (Opcode 5102h)

-added assert-deassert PERST implementation for physical ports (both USP and DSP's). -assert PERST involves bg operation for holding 100ms. -reset PPB implementation for physical ports. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c| 138 ++ includ

[PATCH] hw/riscv/riscv-iommu: Fix MSI table size limit

The MSI table is not limited to 4k. The only constraint the table has is that its base address must be aligned to its size, ensuring no offsets of the table size will overrun when added to the base address (see "8.5. MSI page tables" of the AIA spec). Fixes: 0c54acb8243d ("hw/riscv: add RISC-V IOM

[PATCH v3 1/2] hw/cxl: Refactored Identify Switch Device & Get Physical Port State

-Storing physical ports info during enumeration. -Refactored changes using physical ports info for Identify Switch Device (Opcode 5100h) & Get Physical Port State (Opcode 5101h) physical switch FM-API command set. Signed-off-by: Arpit Kumar --- hw/cxl/cxl-mailbox-utils.c| 230 +

[PATCH v3 0/2] FM-API Physical Switch Command Set Support

This patch series refactor existing support for Identify Switch Device and Get Physical Port State by utilizing physical ports (USP & DSP) information stored during enumeration. Additionally, it introduces new support for Physical Port Control of FM-API based physical switch command set as per CX

  1   2   >