Re: [PATCH 00/10] Designware PCIe host fixes

On 8/20/25 14:19, Bernhard Beschow wrote: This series fixes the Designware PCIe host to work with cards other than virio-net-pci, e.g. e1000. It was tested on the imx8mp-evk machine. The series is structured as follows: The first part refactors the device model to create memory regions for inbou

[PATCH v2 03/10] target/loongarch: Add present and write bit with pte entry

With hardware PTW feature enabled, Present) bit and Write bit is checked by hardware, rather Valid bit and Dirty bit. Bit P means that the page is valid and present, and bit W means that the page is writable. The original V bit is treated as access bit, hardware sets this bit if there is read or w

[PATCH v2 00/10] Add hardware page table walk support

Hardware page table walk (PTW for short) is one feature supported in Loongson 3C6000 system. With hardware PTW supported, if there is an TLB miss, hardware will take PTW and fill it in TLB if matched, report TLB exception if not matched. With hardware PTW supported, bit Present and Write in pte en

[PATCH v2 10/10] target/loongarch: Add bit A/D checking in TLB entry with PTW supported

With read/write access, add bit A/D checking if hardware PTW is supported. If no matched, hardware page table walk is called. And then bit A/D is updated in PTE entry and TLB entry is updated also. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 15 +++ 1 file changed

[PATCH v2 09/10] target/loongarch: Update matched ptw bit A/D with PTW supported

With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 26 ++ target/loongarch/cpu_helper.c | 92 +-- 2 files changed

[PATCH v2 08/10] target/loongarch: Add basic hardware PTW support

With software PTW, there is TLB refill exception if there is TLB miss. However with hardware PTW supported, hardware will search page table with TLB miss. Also if Present bit is not set, hardware PTW will take, it is used in odd/even TLB entry. For example in the first time odd TLB entry is valid

[PATCH v2 06/10] target/loongarch: Add MMUContext parameter in fill_tlb_entry()

Function fill_tlb_entry() can be used with hardware PTW in future, here add input parameter MMUContext in fill_tlb_entry(). Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/loongarch/tc

[PATCH v2 01/10] target/loongarch: Use auto method with PTW feature

PTW is short for page table walker, it is hardware page table walker function. With PTW supported, hardware MMU will parse page table table and update TLB entries automatically. This patch adds type OnOffAuto for PTW feature setting. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 22 +

[PATCH v2 02/10] target/loongarch: Add CSR_PWCH write helper function

Bit HPTW_EN in register CSR_PWCH controls enabling hardware page table walker feature when PTW feature is enabled. Otherwise it is reserved bit. Here add register CSR_PWCH write helper function. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h| 2 ++ target/loonga

[PATCH v2 07/10] target/loongarch: Add debug parameter with loongarch_page_table_walker()

Add debug parameter with function loongarch_page_table_walker(), in debug mode it is only to get physical address. And It used in future HW PTW usage, bit dirty and access will be updated in HW PTW mode. Also function loongarch_page_table_walker() is renamed as loongarch_ptw() for short. Signed-o

[PATCH v2 05/10] target/loongarch: Add common function get_tlb_random_index()

With software PTW system, tlb index is calculated randomly when new TLB entry is added. For hardware PTW, it is the same logic to add new TLB entry. Here common function get_tlb_random_index() is added to get random tlb index when adding new TLB entry. Signed-off-by: Bibo Mao --- target/loongar

[PATCH v2 04/10] target/loongarch: Add function sptw_prepare_tlb before adding tlb entry

With software page table walker, tlb entry comes from CSR registers. however with hardware page table walker, tlb entry comes from page table entry information directly, TLB CSR registers are not necessary. Here add function sptw_prepare_context(), get tlb entry information from TLB CSR registers.

Re: [RFC PATCH 0/3] block/export: Add FUSE-over-io_uring for Storage Exports

On 8/17/25 9:45 AM, Stefan Hajnoczi wrote: > On Thu, Aug 14, 2025 at 11:46:16PM -0400, Zhi Song wrote: >> Due to kernel limitations, when the FUSE-over-io_uring option is >> enabled, >> you must create and assign nr_cpu IOThreads. For example: > > While it would be nice for the kernel to support a

[PATCH 07/10] hw/pci-host/designware: Don't map PCI memory space into PCI inbound window

The real device has a default mapping which disappears as soon as an inbound iATU is configured. Furthermore, inbound and outbound mappings are entirely defined by iATUs. Remove the hardcoded mapping of PCI memory space to match real hardware. Note that the device model attempts to implement the d

[PATCH 04/10] hw/pci-host/designware: Distinguish stronger between viewport memory types

This is a preparation for implementing I/O space support. At the same time, unimplemented memory types and guest errors are logged. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/hw/pci

[PATCH 03/10] hw/pci-host/designware: Determine PCIDevice of configuration region once

Now that viewport memory regions are created on demand, the PCIDevice of the configuration memory can be determined once upon creation of the memory region rather than dynamically resolving it upon each access. This is both more efficient at runtime and resolves an attribute. Furthermore, if an inv

[PATCH 06/10] hw/pci-host/designware: Fix I/O range

Fix the size of the I/O space to be 64KiB, as defined by the PCI specification. This fixes illegal memory access by guests in the imx8mp-evk machine such that the FSL_IMX8MP_PCIE1_MEM unimplemented region can be omitted there. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 2 +-

[PATCH 10/10] hw/arm/fsl-imx8mp: Do not map PCI window as unimplemented

Now that populating the PCI window via iATUs is functional, it's no longer necessary to cover the PCI window with an unimplemented memory region. Previously, this workaround was required because the device model failed to map all configured memory regions, which caused Linux to emit backtraces duri

[PATCH 02/10] hw/pci-host/designware: Create viewport memory regions on demand

Currently, all viewport memory regions are created upfront in the realize phase. This has several drawbacks: First, two MemoryRegion members are needed per viewport while maximum only one is ever used at a time. Second, for inbound viewports, the `cfg` member is never used nor initialized. Third, a

[PATCH 00/10] Designware PCIe host fixes

This series fixes the Designware PCIe host to work with cards other than virio-net-pci, e.g. e1000. It was tested on the imx8mp-evk machine. The series is structured as follows: The first part refactors the device model to create memory regions for inbound/outbound PCI mappings on demand rather th

[PATCH 05/10] hw/pci-host/designware: Implement I/O space

Mapping I/O space works via viewports in this device but isn't implemented in the model. Fix that. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 5

[PATCH 01/10] hw/pci-host/designware: Eliminate some helper variables

In the next step, code gets moved around where the helper variables aren't used any longer. Eliminate them now to make the code movement clearer. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 36 +++- 1 file changed, 15 insertions(+), 21 deletions

[PATCH 08/10] hw/pci-host/designware: Fix default inbound viewport mapping

Linux clears all inbound viewport mappings which results in the default mapping set up during realize() to be cleared. Fix that by introducing a fallback memory region which gets enabled if no inbound viewports are configured, as the real HW would do. Signed-off-by: Bernhard Beschow --- include/

[PATCH 09/10] hw/pci-host/designware: Implement device reset

Fixes the memory mapping to be cleared during reset, like real hardware would do. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 33 ++--- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware

Re: [RFC PATCH] hw/virtio: rename vhost-user-device and make user creatable

On Wed, Aug 20, 2025 at 08:56:32PM +0100, Alex Bennée wrote: > We didn't make the device user creatable in the first place because we > were worried users might get confused. Rename the device to make its > nature as a test device even more explicit. While we are at it add a > Kconfig variable so i

Re: [RFC PATCH] hw/virtio: rename vhost-user-device and make user creatable

On Wed, Aug 20, 2025 at 10:57 PM Alex Bennée wrote: > > We didn't make the device user creatable in the first place because we > were worried users might get confused. Rename the device to make its > nature as a test device even more explicit. While we are at it add a > Kconfig variable so it can

[PATCH RFC] bql: Fix bql_locked status with condvar APIs

QEMU has a per-thread "bql_locked" variable stored in TLS section, showing whether the current thread is holding the BQL lock. It's a pretty handy variable. Function-wise, QEMU have codes trying to conditionally take bql, relying on the var reflecting the locking status (e.g. BQL_LOCK_GUARD), or

[PATCH 1/2] scripts/minikconf.py: fix invalid attribute access

Fix parse method to use `defconfig` global variable instead of the non-existent KconfigParser class attribute Fixes: f349474920d80838ecea3d421531fdb0660b8740 ("minikconfig: implement allnoconfig and defconfig modes") Signed-off-by: Manos Pitsidianakis --- scripts/minikconf.py | 2 +- 1 file cha

Re: [PATCH 0/2] Two minor minikconf.py fixes

Queued, thanks. Paolo

[PATCH 2/2] scripts/minikconf.py: s/Error/KconfigParserError

Error is not defined in this script, raise KconfigParserError instead. Fixes: 82f5181777ebe04b550fd94a1d04c49dd3f012dc ("kconfig: introduce kconfig files") Signed-off-by: Manos Pitsidianakis --- scripts/minikconf.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/

[PATCH 0/2] Two minor minikconf.py fixes

scripts/minikconf.py: s/Error/KconfigParserError scripts/minikconf.py | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) --- base-commit: 88f72048d2f5835a1b9eaba690c7861393aef283 change-id: 20250820-scripts-minikconf-fixes-e62a20429f54 -- γαῖα πυρί μιχθήτω

Re: [PATCH v7 6/8] tests/qtest: Add GET_SHMEM validation test

On Tue, Aug 19, 2025 at 02:16:47PM +0200, Albert Esteve wrote: > On Tue, Aug 19, 2025 at 12:42 PM Stefan Hajnoczi wrote: > > > > On Mon, Aug 18, 2025 at 12:03:51PM +0200, Albert Esteve wrote: > > > Improve vhost-user-test to properly validate > > > VHOST_USER_GET_SHMEM_CONFIG message handling by >

Re: [PATCH v11 01/27] migration: push Error **errp into vmstate_subsection_load()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 05:06:11PM -0300, Fabiano Rosas wrote: > Fabiano Rosas writes: > > > Arun Menon writes: > > > >> This is an incremental step in converting vmstate loading > >> code to report error via Error objects instead of directly > >> printing it

[RFC PATCH] hw/virtio: rename vhost-user-device and make user creatable

We didn't make the device user creatable in the first place because we were worried users might get confused. Rename the device to make its nature as a test device even more explicit. While we are at it add a Kconfig variable so it can be skipped for those that want to thin out their build configur

[PATCH] ii6300esb: fix incorrect mask for interrupt type

According to Intel 6300ESB Controller Hub Datasheet 14.4.15, the interrupt type mask should be 0x03 (0b11) instead of 0x11. In the original implementation, when we want to disable all interrupt by setting the value to 0x03, we will get 0x01 which will be incorrect when we reading the value again. H

[PATCH] i6300esb: fix incorrect mask for interrupt type

According to Intel 6300ESB Controller Hub Datasheet 14.4.15, the interrupt type mask should be 0x03 (0b11) instead of 0x11. In the original implementation, when we want to disable all interrupt by setting the value to 0x03, we will get 0x01 which will be incorrect when we reading the value again. H

[ANNOUNCE] QEMU 10.1.0-rc4 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the fifth release candidate for the QEMU 10.1 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu.org/qemu-10.1.0-rc4.tar.xz http://download.qem

Re: [PATCH 1/3] tests/functional: return output from exec_command_and_wait_for_pattern()

On Mon, Aug 18, 2025 at 12:05:44PM +0100, John Levon wrote: > Tests might want to look at the whole output from a command execution, > as well as just logging it. Add support for this. > > Signed-off-by: John Levon > --- > tests/functional/qemu_test/cmd.py | 38 +++ >

[PATCH] i6300esb: fix incorrect mask for interrupt type

According to Intel 6300ESB Controller Hub Datasheet 14.4.15, the interrupt type mask should be 0x03 (0b11) instead of 0x11. In the original implementation, when we want to disable all interrupt by setting the value to 0x03, we will get 0x01 which will be incorrect when we reading the value again. H

Re: [PULL 2/5] net: move backend cleanup to NIC cleanup

On Wed, 2025-08-20 at 08:22 -0400, Jonah Palmer wrote: > > > > > > From: Eugenio Pérez > > > > > > > > > > > > Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net > > > > > > structures if peer nic is present") effectively delayed the backend > > > > > > cleanup, allowing the fronte

Re: [PATCH v11 02/27] migration: push Error **errp into vmstate_load_state()

On Wed, Aug 20, 2025 at 12:24:49PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > Hi Fabiano, > > > > Thanks for the review. > > > > On Fri, Aug 15, 2025 at 12:41:50PM -0300, Fabiano Rosas wrote: > >> Arun Menon writes: > >> > >> > This is an incremental step in converting vmstate loadi

Re: [PATCH v11 10/27] migration: push Error **errp into qemu_loadvm_section_start_full()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 04:29:49PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensur

Re: [PATCH v11 23/27] migration: Capture error in postcopy_ram_listen_thread()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 04:57:38PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > postcopy_r

Re: [PATCH v11 07/27] migration: push Error **errp into qemu_loadvm_state()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 03:55:19PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensu

Re: [PATCH v11 08/27] migration: push Error **errp into qemu_load_device_state()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 03:58:50PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensu

Re: [PATCH v11 11/27] migration: push Error **errp into qemu_loadvm_section_part_end()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 04:35:36PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensu

Re: [PATCH v11 19/27] migration: push Error **errp into loadvm_handle_recv_bitmap()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 04:51:04PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensu

Re: [PATCH v11 04/27] migration: push Error **errp into vmstate_load()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 01:41:40PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensu

Re: [PATCH v11 09/27] migration: push Error **errp into qemu_loadvm_state_main()

Hi Fabiano, Thanks for the review. On Fri, Aug 15, 2025 at 04:23:42PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensur

Re: [RFC 06/11] hw/arm/smmuv3: Plumb security state through core functions

On 2025/8/19 05:28, Mostafa Saleh wrote: On Wed, Aug 06, 2025 at 11:11:29PM +0800, Tao Tang wrote: To support parallel processing of secure and non-secure streams, the SMMUv3 model needs to differentiate between the two contexts throughout its core logic. This commit is the foundational step t

Re: [PATCH 3/3] tests/functional: add a vfio-user smoke test

On Mon, Aug 18, 2025 at 12:05:46PM +0100, John Levon wrote: > From: Mark Cave-Ayland > > Add a basic test of the vfio-user PCI client implementation. > > Co-authored-by: John Levon > Signed-off-by: Mark Cave-Ayland > Signed-off-by: John Levon > --- > MAINTAINERS

Re: [PATCH 2/3] tests/functional: add vm param to console routines

On Mon, Aug 18, 2025 at 12:05:45PM +0100, John Levon wrote: > Extend the "vm" parameter of wait_for_console_pattern() to all the other > utility functions; this allows them to be used on a VM other than > test.vm. > > Signed-off-by: John Levon > --- > tests/functional/qemu_test/cmd.py | 18 +

Re: [RFC 03/11] hw/arm/smmuv3: Implement S_INIT for secure initialization

On 2025/8/19 05:26, Mostafa Saleh wrote: On Wed, Aug 06, 2025 at 11:11:26PM +0800, Tao Tang wrote: This patch implements the S_INIT register, a secure-only register with no non-secure counterpart. It provides a simple mechanism for secure software to perform a global invalidation of all SMMU c

Re: [PATCH v2 03/24] migration: Normalize tls arguments

Peter Xu writes: > On Fri, Jul 04, 2025 at 10:12:33AM -0300, Fabiano Rosas wrote: > > [...] > >> >>> +static void tls_opt_to_str(StrOrNull **tls_opt) >> >>> +{ >> >>> +StrOrNull *opt = *tls_opt; >> >>> + >> >>> +if (!opt) { >> >>> +return; >> >> >> >> ... it can also be null. >> >

Re: [PATCH v7 6/8] tests/qtest: Add GET_SHMEM validation test

On Tue, Aug 19, 2025 at 02:16:47PM +0200, Albert Esteve wrote: > On Tue, Aug 19, 2025 at 12:42 PM Stefan Hajnoczi wrote: > > > > On Mon, Aug 18, 2025 at 12:03:51PM +0200, Albert Esteve wrote: > > > Improve vhost-user-test to properly validate > > > VHOST_USER_GET_SHMEM_CONFIG message handling by >

Re: [PATCH v11 02/27] migration: push Error **errp into vmstate_load_state()

Arun Menon writes: > Hi Fabiano, > > Thanks for the review. > > On Fri, Aug 15, 2025 at 12:41:50PM -0300, Fabiano Rosas wrote: >> Arun Menon writes: >> >> > This is an incremental step in converting vmstate loading >> > code to report error via Error objects instead of directly >> > printing it

Re: [RFC 02/11] hw/arm/smmuv3: Implement read/write logic for secure registers

On 2025/8/19 05:24, Mostafa Saleh wrote: On Wed, Aug 06, 2025 at 11:11:25PM +0800, Tao Tang wrote: This patch builds upon the previous introduction of secure register definitions by providing the functional implementation for their access. The availability of the secure programming interface

Re: [PATCH 4/4] target/ppc: Fix env->quiesced migration

On 20/08/2025 17.07, Fabiano Rosas wrote: Thomas Huth writes: On 20/08/2025 00.39, Fabiano Rosas wrote: The commit referenced (from QEMU 10.0) has changed the way the pseries machine marks a cpu as quiesced. Previously, the cpu->halted value from QEMU common cpu code was (incorrectly) used. W

Re: [RFC PATCH 3/4] tests/functional: Add a OS level migration test for pseries

Thomas Huth writes: > On 20/08/2025 00.39, Fabiano Rosas wrote: >> There's currently no OS level test for ppc64le. Add one such test by >> reusing the boot level tests that are already present. >> >> The test boots the source machine, waits for it to reach a mid-boot >> message, migrates and che

Re: [PATCH 4/4] target/ppc: Fix env->quiesced migration

Thomas Huth writes: > On 20/08/2025 00.39, Fabiano Rosas wrote: >> The commit referenced (from QEMU 10.0) has changed the way the pseries >> machine marks a cpu as quiesced. Previously, the cpu->halted value >> from QEMU common cpu code was (incorrectly) used. With the fix, the >> env->quiesced v

Re: [PATCH v2 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation

Hi Luc, On 20/8/25 10:25, Luc Michel wrote: Refactor the CPU cluster creation using the VersalMap structure. There is no functional change. The clusters properties are now described in the VersalMap structure. For now only the APU is converted. The RPU will be taken care of by next commits. Sig

Re: [PATCH v4 6/8] add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide

On 8/14/25 12:05 PM, Igor Mammedov wrote: the helpers form load-acquire/store-release pair and use them to replace open-coded checkers/setters consistently across the code, which ensures that appropriate barriers are in place in case checks happen outside of BQL. Signed-off-by: Igor Mammedov --

Re: [PATCH 26/33] io/channel-socket: introduce qio_channel_socket_keep_nonblock()

On Wed, Aug 20, 2025 at 10:37:41AM -0400, Peter Xu wrote: > On Wed, Aug 20, 2025 at 02:43:54PM +0100, Daniel P. Berrangé wrote: > > On Wed, Aug 20, 2025 at 09:27:09AM -0400, Peter Xu wrote: > > > On Wed, Aug 13, 2025 at 07:48:47PM +0300, Vladimir Sementsov-Ogievskiy > > > wrote: > > > > Add a poss

Re: [PATCH 26/33] io/channel-socket: introduce qio_channel_socket_keep_nonblock()

On Wed, Aug 20, 2025 at 02:43:54PM +0100, Daniel P. Berrangé wrote: > On Wed, Aug 20, 2025 at 09:27:09AM -0400, Peter Xu wrote: > > On Wed, Aug 13, 2025 at 07:48:47PM +0300, Vladimir Sementsov-Ogievskiy > > wrote: > > > Add a possibility to keep socket non-block status when passing > > > through q

[PATCH 1/5] docker: Remove 32-bit MIPS toolchain from debian-all-test image

In commit d3322023bfe ("configure: unify again the case arms in probe_target_compiler") we lost coverage of 32-bit MIPS with the debian-all-test image. No need to keep installing the toolchain. Signed-off-by: Philippe Mathieu-Daudé --- tests/docker/dockerfiles/debian-all-test-cross.docker | 4 --

[PATCH 0/5] tcg/mips: Remove support for 32-bit hosts

32-bit hosts are deprecated since v10.0. 2 releases later (as of v10.2) we can remove such code. Start with MIPS TCG backend. Remove related buildsys and testing. Based-on: <20250820134937.45077-1-phi...@linaro.org> Philippe Mathieu-Daudé (5): docker: Remove 32-bit MIPS toolchain from debian-al

[PATCH 3/5] docker: Stop building 32-bit MIPS images

32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Besides, the Debian distribution we are using to cross-build dropped support for MIPS as of Debian 13 [*]: From trixie, the architectures mipsel and mips64el are no longer supported by Debian.

[PATCH 5/5] tcg/mips: Remove support for 32-bit hosts

32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"), released as v10.0. The next release being v10.2, we can remove the TCG backend for 32-bit MIPS hosts. Signed-off-by: Philippe Mathieu-Daudé --- tcg/mips/tcg-target-has.h | 2 - tcg/mips/tc

[PATCH 2/5] gitlab: Stop cross-testing for 32-bit MIPS hosts

32-bit host support is deprecated since commit 6d701c9bac1 ("meson: Deprecate 32-bit host support"). Next commits will remove support for 32-bit MIPS hosts. Stop cross-building QEMU on our CI. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.d/container-cross.yml | 6 -- .gitlab-ci.d/cr

[PATCH 4/5] tcg/mips: Check O32/N32/64 ABI definitions actually exist

Similarly noted in libunwind: https://reviews.llvm.org/D38110#895887, when _ABIO32 / _ABIN32 / _ABI64 are not defined (like on OpenBSD) we get: [666/1234] Compiling C object libsystem.a.p/tcg_tcg-common.c.o In file included from ../tcg/tcg-common.c:26: In file included from include/tcg/tcg.h

Re: [PATCH 26/33] io/channel-socket: introduce qio_channel_socket_keep_nonblock()

On Wed, Aug 20, 2025 at 09:27:09AM -0400, Peter Xu wrote: > On Wed, Aug 13, 2025 at 07:48:47PM +0300, Vladimir Sementsov-Ogievskiy wrote: > > Add a possibility to keep socket non-block status when passing > > through qio channel. We need this to support migration of open > > fds through migration c

Re: [PATCH] MAINTAINERS: add a few more files to "Top Level Makefile and configure"

On Wed, 20 Aug 2025 at 10:46, Paolo Bonzini wrote: > > On Tue, Aug 19, 2025 at 6:08 PM Peter Maydell > wrote: > > > > On Tue, 19 Aug 2025 at 16:43, Paolo Bonzini wrote: > > > > > > A few files in scripts, and the list of packages in pythondeps.toml, are > > > strictly related to the toplevel bu

[RFC PATCH] tcg: Restrict qemu_ld2 and qemu_st2 opcodes to 32-bit hosts

qemu_ld2 and qemu_st2 opcodes are band-aid for 32-bit hosts and can't be reached on 64-bit ones. See in commit 3bedb9d3e28 ("tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}") and 86fe5c2597c ("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}") their constraint is C_NotImplemented. Signed-off-by: Philippe Mat

Re: [PATCH v11 05/27] migration: push Error **errp into loadvm_process_command()

On Fri, Aug 15, 2025 at 03:35:40PM -0300, Fabiano Rosas wrote: > Arun Menon writes: > > > This is an incremental step in converting vmstate loading > > code to report error via Error objects instead of directly > > printing it to console/monitor. > > It is ensured that loadvm_process_command() mu

Re: [PATCH] MAINTAINERS: list qemu-secur...@nongnu.org as security contact

Daniel P. Berrangé writes: > The qemu-secur...@nongnu.org list is considered the authoritative > contact for reporting QEMU security issues. Remove the Red Hat > security team address in favour of QEMU's list, to ensure that > upstream gets first contact. There is a representative of the > Red Ha

Re: [PATCH 26/33] io/channel-socket: introduce qio_channel_socket_keep_nonblock()

On Wed, Aug 13, 2025 at 07:48:47PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Add a possibility to keep socket non-block status when passing > through qio channel. We need this to support migration of open > fds through migration channel. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- >

Re: [PULL 0/2] Python patches

On Wed, Aug 20, 2025 at 01:01:06AM -0400, John Snow wrote: > On Wed, Aug 20, 2025 at 12:58 AM John Snow wrote: > > > > The following changes since commit 5836af0783213b9355a6bbf85d9e6bc4c9c9363f: > > > > Merge tag 'uefi-20250812-pull-request' of https://gitlab.com/kraxel/qemu > > into staging (

Re: [PATCH 27/33] migration/socket: keep fds non-block

On Wed, Aug 13, 2025 at 07:48:48PM +0300, Vladimir Sementsov-Ogievskiy wrote: > For migration channel keep fds non-blocking property as is. > It's needed for future local migration of fds. It is pretty risky. This changes the attribute for all the iochannels that migration incoming side uses, inc

Re: [PATCH 26/33] io/channel-socket: introduce qio_channel_socket_keep_nonblock()

On Wed, Aug 13, 2025 at 07:48:47PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Add a possibility to keep socket non-block status when passing > through qio channel. We need this to support migration of open > fds through migration channel. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- >

Re: [PATCH] MAINTAINERS: list qemu-secur...@nongnu.org as security contact

On Wed, Aug 20, 2025 at 2:44 PM Daniel P. Berrangé wrote: > > The qemu-secur...@nongnu.org list is considered the authoritative > contact for reporting QEMU security issues. Remove the Red Hat > security team address in favour of QEMU's list, to ensure that > upstream gets first contact. There is

Re: [PATCH v2 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation

On 14:21 Wed 20 Aug , Philippe Mathieu-Daudé wrote: [snip] > > > -arm_load_kernel(&s->soc.fpd.apu.cpu[0], machine, &s->binfo); > > > +arm_load_kernel(ARM_CPU(qemu_get_cpu(0)), machine, &s->binfo); > > > > We'd like to restrict qemu_get_cpu() to generic accelerator code, where > > what

[PATCH] fix: Fix build error with CONFIG_POWERNV disabled

Currently when CONFIG_POWERNV is not enabled, the build fails, such as with --without-default-devices: $ ./configure --without-default-devices $ make [281/283] Linking target qemu-system-ppc64 FAILED: qemu-system-ppc64 cc -m64 @qemu-system-ppc64.rsp /usr/bin/ld: libqemu-pp

[PATCH] MAINTAINERS: list qemu-secur...@nongnu.org as security contact

The qemu-secur...@nongnu.org list is considered the authoritative contact for reporting QEMU security issues. Remove the Red Hat security team address in favour of QEMU's list, to ensure that upstream gets first contact. There is a representative of the Red Hat security team as a member of qemu-sec

Re: [PATCH v2 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt

On 20/8/25 10:25, Luc Michel wrote: To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel Revi

Re: [PATCH 3/3] hw/ppc: Add stub for pnv_chip_find_core()

+Michael On 11/08/25 14:10, Philippe Mathieu-Daudé wrote: On 22/7/25 20:04, Aditya Gupta wrote: Hi Cédric and Philippe, On 26/05/25 17:21, Philippe Mathieu-Daudé wrote: On 26/5/25 13:48, Cédric Le Goater wrote: On 5/26/25 13:23, Philippe Mathieu-Daudé wrote: Since commit 9808ce6d5cb, build

Re: [PATCH v2 34/47] hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices

On 20/8/25 10:25, Luc Michel wrote: Use the bsa.h header for ARM timer and maintainance IRQ indices instead of redefining our owns. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 6 -- hw/arm/xlnx-versal.c | 28 +

Re: [PATCH v6 02/13] hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU

> On 8 Aug 2025, at 09.01, Mohamed Mediouni wrote: > > Creating a vCPU locks out APIs such as hv_gic_create(). > > As a result, switch to using the hv_vcpu_config_get_feature_reg interface. > > Hardcode MIDR because Apple deliberately doesn't expose a divergent MIDR > across systems. > > Si

Re: [PATCH v2 46/47] hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine

On 20/8/25 10:25, Luc Michel wrote: Add the Versal Gen 2 Virtual development machine embedding a versal2 SoC. This machine follows the same principle than the xlnx-versal-virt machine. It creates its own DTB and feeds it to the software payload. This way only implemented devices are exposed to th

Re: [PATCH v2 41/47] hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt

On 20/8/25 10:25, Luc Michel wrote: To align with current branding and ensure coherency with the upcoming versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt. Keep an alias of the old name to the new one for command-line backward compatibility. Signed-off-by: Luc Michel Revi

Re: [PULL 2/5] net: move backend cleanup to NIC cleanup

On 8/20/25 3:14 AM, Eugenio Perez Martin wrote: On Wed, Aug 20, 2025 at 8:47 AM David Woodhouse wrote: On Wed, 2025-08-20 at 10:34 +0800, Jason Wang wrote: On Wed, Aug 20, 2025 at 12:13 AM David Woodhouse wrote: On Mon, 2025-03-10 at 20:22 +0800, Jason Wang wrote: From: Eugenio Pérez

Re: [PATCH v2 20/47] hw/arm/xlnx-versal: refactor CPU cluster creation

On 20/8/25 14:16, Philippe Mathieu-Daudé wrote: Hi Luc, On 20/8/25 10:25, Luc Michel wrote: Refactor the CPU cluster creation using the VersalMap structure. There is no functional change. The clusters properties are now described in the VersalMap structure. For now only the APU is converted. Th

Re: [PATCH v2 21/47] hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping

Hi Luc, On 20/8/25 10:25, Luc Michel wrote: Add a way to configure the MP affinity value of the CPUs given their core and cluster IDs. For the Versal APU CPUs, the MP affinity value is directly given by the core ID. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- hw/arm/xlnx-v

Re: [PATCH v2 1/2] tracetool: add CHECK_TRACE_EVENT_GET_STATE

On Thu, Aug 07, 2025 at 12:35:39PM +0200, Paolo Bonzini wrote: > On 8/6/25 21:13, Daniel P. Berrangé wrote: > > It is best to have new functionality added in a separate commit > > from the removal of obsolete code. > > My mistake - when Tanish and I "un-rebased" these patches from on top of > your

Re: [PATCH 0/7] target/arm/hvf cleanups

> On 18 Aug 2025, at 06.13, Richard Henderson > wrote: > > While working on other things cpregs related, I noticed that > target/arm/hvf failed to produce a sorted cpreg_indexes[]. > > I wondered if that explained the migration-test failure that > we have, but no such luck. (I have no idea h

Re: [PATCH 08/12] util: convert error-report & log to message API for timestamp

On Wed, Aug 20, 2025 at 08:02:14AM +1000, Richard Henderson wrote: > On 8/20/25 06:27, Daniel P. Berrangé wrote: > > void qemu_log(const char *fmt, ...) > > { > > FILE *f; > > -g_autofree const char *timestr = NULL; > > - > > /* > > - * Prepare the timestamp*outside* the log

[PATCH v2 01/47] hw/arm/xlnx-versal: split the xlnx-versal type

Split the xlnx-versal device into two classes, a base, abstract class and the existing concrete one. Introduce a VersalVersion type that will be used across several device models when versal2 implementation is added. This is in preparation for versal2 implementation. Signed-off-by: Luc Michel Re

Re: [PATCH 07/12] util: introduce common helper for error-report & log code

On Wed, Aug 20, 2025 at 07:57:47AM +1000, Richard Henderson wrote: > On 8/20/25 06:27, Daniel P. Berrangé wrote: > > +char *qmessage_context(int flags) > > +{ > > +g_autofree char *timestr = NULL; > > + > > +if ((flags & QMESSAGE_CONTEXT_SKIP_MONITOR) && > > +monitor_cur()) { > > +

Re: [PATCH 06/12] util: add API to fetch the current thread name

On Wed, Aug 20, 2025 at 07:50:05AM +1000, Richard Henderson wrote: > On 8/20/25 06:27, Daniel P. Berrangé wrote: > > +strncpy(namebuf, "unnamed", sizeof(namebuf) - 1); > > +namebuf[sizeof(namebuf) - 1] = '\0'; > > g_strlcpy? Sure, I always forget about that. With regards, Daniel

Re: [PATCH 05/12] util: add API to fetch the current thread id

On Tue, Aug 19, 2025 at 11:35:26PM +, Dr. David Alan Gilbert wrote: > * Daniel P. Berrangé (berra...@redhat.com) wrote: > > For logging it is useful to include the current thread id. On > > POSIX there is no standard API for this, so try the Linux gettid() > > syscall preferentially, otherwise

Re: [PATCH] hw/arm: add static NVDIMMs in device tree

Hi David, On 2025/8/20 17:29, David Hildenbrand wrote: On 20.08.25 06:10, Gao Xiang wrote: (try to Cc David and Paolo for some discussion...) Hi David and Paolo, Hi! If possible, could you share some thoughts about this, because currently each `memory-backend-file` has their own page cach

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