Re: [PATCH v3 0/3] pc-bios: Update vbootrom images

Philippe, On 7/30/25 06:58, Cédric Le Goater wrote: Hello ! Michael provided changes to fix the build of the vbootrom image of the AST2700 SoC machine in [1]. However, a workaound in roms/Makefile was still necessary to build ast27x0_bootrom.bin correctly. This was later fixed in [2]. This ser

[PATCH v2] target/xtensa: Replace malloc() with g_strdup_printf()

malloc() return value is used without a check. Found by Linux Verification Center (linuxtesting.org) with SVACE. v2: Also replaced strdup() with g_strdup() Signed-off-by: Dmitry Frolov --- target/xtensa/translate.c | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a

Re: [PATCH v4 15/19] target/loongarch: Use correct address when flush tlb

On 7/29/25 17:10, Bibo Mao wrote: With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit. However on LoongArch TLB emulation system, virtual address is 48 bit. It is necessary to signed-extend 48 bit address to 64 bit when flush tlb, also fix address calculation issue with odd page. Sig

Re: [PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address()

On 7/29/25 17:08, Bibo Mao wrote: With function get_physical_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 3 +-- target/loongarch/cpu_helper.c | 32 ---

Re: [PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address()

On 7/29/25 17:01, Bibo Mao wrote: With function loongarch_map_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 32 ++-- 1 file changed, 14 insertions(+), 18 deletion

Re: [PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb

On 7/29/25 17:01, Bibo Mao wrote: With function loongarch_get_addr_from_tlb(), parameter MMUContext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c| 7 +-- target/loongarch/tcg/tcg_loongarch.h | 4 ++-- target/

Re: [PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry()

On 7/29/25 17:01, Bibo Mao wrote: With function loongarch_map_tlb_entry(), parameter MMUConext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 33 +++ 1 file changed, 16 insertions(+), 17 del

Re: [PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte()

On 7/29/25 17:01, Bibo Mao wrote: Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge if found. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h

Re: [PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition

On 7/29/25 17:01, Bibo Mao wrote: There is mixed usage between enum variable TLBRET_xxx and int type, here add enum type TLBRet definition and replace int type variable with enum type TLBRet in some functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 27 ++

Re: [PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()

On 7/29/25 17:01, Bibo Mao wrote: Replace target_ulong type with vaddr in function get_physical_address() and the same with its calling functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 2 +- target/loongarch/cpu_helper.c | 9 - target/loongarch/tcg/tlb

Re: [PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()

On 7/29/25 17:01, Bibo Mao wrote: Enum type MMUAccessType is used in function loongarch_map_tlb_entry() rather than int type, and keep consistent with its caller function. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Rev

RE: [PATCH v3 3/3] pc-bios: Update vbootrom image to commit 183c9ff8056b

> From: Cédric Le Goater > Sent: Wednesday, July 30, 2025 12:58 PM > To: qemu-devel@nongnu.org > Cc: Philippe Mathieu-Daudé ; Michael Tokarev > ; Peter Maydell ; Hao Wu > ; Jamin Lin ; Cédric Le > Goater > Subject: [PATCH v3 3/3] pc-bios: Update vbootrom image to commit > 183c9ff8056b > > Full c

RE: [PATCH v3 2/3] roms/Makefile: build ast27x0_bootrom

> From: Cédric Le Goater > Sent: Wednesday, July 30, 2025 12:58 PM > To: qemu-devel@nongnu.org > Cc: Philippe Mathieu-Daudé ; Michael Tokarev > ; Peter Maydell ; Hao Wu > ; Jamin Lin ; Cédric Le > Goater > Subject: [PATCH v3 2/3] roms/Makefile: build ast27x0_bootrom > > From: Michael Tokarev >

RE: [PATCH v3 1/3] roms/vbootrom: update to 7b1eb5f7fe6a

> From: Cédric Le Goater > Sent: Wednesday, July 30, 2025 12:58 PM > To: qemu-devel@nongnu.org > Cc: Philippe Mathieu-Daudé ; Michael Tokarev > ; Peter Maydell ; Hao Wu > ; Jamin Lin ; Cédric Le > Goater > Subject: [PATCH v3 1/3] roms/vbootrom: update to 7b1eb5f7fe6a > > From: Michael Tokarev >

Re: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support

Jamin, On 7/30/25 03:47, Jamin Lin wrote: Hi Cédric, Michael From: Cédric Le Goater Sent: Tuesday, July 29, 2025 5:12 PM To: Jamin Lin ; Michael Tokarev ; Peter Maydell ; Steven Lee ; Troy Lee ; Andrew Jeffery ; Joel Stanley ; open list:ASPEED BMCs ; open list:All patches CC here Cc: Troy Le

[PATCH v3 0/3] pc-bios: Update vbootrom images

Hello ! Michael provided changes to fix the build of the vbootrom image of the AST2700 SoC machine in [1]. However, a workaound in roms/Makefile was still necessary to build ast27x0_bootrom.bin correctly. This was later fixed in [2]. This series is an update of [1] including a vbootrom image matc

[PATCH v3 3/3] pc-bios: Update vbootrom image to commit 183c9ff8056b

Full changelog since last update (1287b6e42e83) : Hao Wu (2): Automatically search for UBOOT location for NPCM8xx images. Dynamically detects NPCM8XX UBOOT destination and size. Jamin Lin (5): Add initial support for AST27x0 ast27x0: Show build date and git version a

[PATCH v3 1/3] roms/vbootrom: update to 7b1eb5f7fe6a

From: Michael Tokarev Changes: 7b1eb5f ast27x0: Fix Makefile to unconditionally set CC to support correct cross-compilation 601d410 ast27x0: Fix missing SCU module reset for SSP and TSP initialization 80768e4 ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory from DTB f8ab63

[PATCH v3 2/3] roms/Makefile: build ast27x0_bootrom

From: Michael Tokarev Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3052 Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Link: https://lore.kernel.org/qemu-devel/607a943a587248fbe0ff0897de80aee98a093caa.1753654515.git@tls.msk.

[PATCH v4 18/19] target/loongarch: Reduce TLB flush with helper_tlbwr

With function helper_tlbwr(), specified LoongArch TLB entry will be updated. There are two PTE pages in one TLB entry, it is not necessary to flush QEMU TLB when one PTE page keeps unchanged and ther other PTE page is newly added. Here check whether PTE page is the same or not, TLB flush can be sk

[PATCH v4 19/19] target/loongarch: Update TLB index selection method

With function helper_tlbfill(), since there is no suitable TLB entry, new TLB will be added and invalidate one old TLB entry. The old TLB entry index is selected randomly, instead it can be optimized as following: 1. invalid TLB entry can be selected at first. 2. TLB entry with other ASID can b

[PATCH v4 17/19] target/loongarch: Add parameter tlb pointer with fill_tlb_entry

With function fill_tlb_entry(), it will update LoongArch emulated TLB information. Here parameter tlb pointer is added so that TLB entry will be updated based on relative TLB CSR registers. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/tcg/tlb_helper.c | 7 +++

[PATCH v4 16/19] target/loongarch: Use mmu idx bitmap method when flush tlb

With API tlb_flush_range_by_mmuidx(), bitmap of mmu idx should be used rather than itself. And mmu idx comes from page table entry information rather current running mode. Also field KM in TLB misc records bitmap mask of TLB entry which is access in kernel mode. If set, MMU_KERNEL_IDX should be ad

[PATCH v4 15/19] target/loongarch: Use correct address when flush tlb

With tlb_flush_range_by_mmuidx(), the virtual address is 64 bit. However on LoongArch TLB emulation system, virtual address is 48 bit. It is necessary to signed-extend 48 bit address to 64 bit when flush tlb, also fix address calculation issue with odd page. Signed-off-by: Bibo Mao --- target/lo

[PATCH v4 14/19] target/loongarch: Track user space address accessed in kernel mode

The concept of mmu idx between QEMU TLB and LoongArch TLB emulation is different: mmu idx in QEMU TLB comes from currently working mode of vCPU mmu idx from LoongArch TLB is page priviledge level With copy_from_user() executed in system, vCPU is in kernel mode however PLV of PTE is user mode.

[PATCH v4 13/19] target/loongarch: Use MMUContext in get_physical_address()

With function get_physical_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 3 +-- target/loongarch/cpu_helper.c | 32 --- target/loongarch/tcg/tlb_helper.c |

[PATCH v4 07/19] target/loongarch: Use MMUAccessType in loongarch_map_tlb_entry()

Enum type MMUAccessType is used in function loongarch_map_tlb_entry() rather than int type, and keep consistent with its caller function. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/tcg/tlb_hel

[PATCH v4 10/19] target/loongarch: Use MMUConext in loongarch_map_tlb_entry()

With function loongarch_map_tlb_entry(), parameter MMUConext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 33 +++ 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/target/loonga

[PATCH v4 08/19] target/loongarch: Add common function loongarch_check_pte()

Common function loongarch_check_pte() is to check tlb entry, return the physical address and access priviledge if found. Also it can be used with page table entry, which is used in page table walker. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 10 + target/loongarch/cpu_h

[PATCH v4 12/19] target/loongarch: Use MMUContext in loongarch_map_address()

With function loongarch_map_address(), parameter MMUContext is added and remove parameter address, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 32 ++-- 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/target/loongarch/c

[PATCH v4 02/19] target/loongarch: Define function loongarch_cpu_post_init as static

Function loongarch_cpu_post_init() is implemented and used in the same file target/loongarch/cpu.c, it can be defined as static function. This patch moves implementation about function loongarch_cpu_post_init() before it is referenced. And it is only code movement, no function change. Signed-off-

[PATCH v4 04/19] target/loongarch: Add header file cpu-mmu.h

New header file cpu-mmu.h is added and move mmu relative function declaration to this file. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu-mmu.h| 30 ++ target/loongarch/cpu.c| 1 + target/loongarch/cpu_helper.c

[PATCH v4 00/19] target/loongarch: Enhancement about tcg mmu

There are some enhancement about LoongArch mmu tcg emulation, add new header file cpu-mmu.h and function loongarch_check_pte(). Function loongarch_check_pte() can work on both TLB entry and pte entry. This patchset mainly is code cleanup and enhancement, its main purpose is to work for hardware pa

[PATCH v4 01/19] target/loongarch: Move some function definition to kvm directory

Move function definition specified with kvm to the corresponding directory. Also remove header file "cpu.h" including outside of macro QEMU_KVM_LOONGARCH_H. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h

[PATCH v4 05/19] target/loongarch: Add enum type TLBRet definition

There is mixed usage between enum variable TLBRET_xxx and int type, here add enum type TLBRet definition and replace int type variable with enum type TLBRet in some functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 27 ++- target/loongarch/cpu_

[PATCH v4 11/19] target/loongarch: Use MMUContext in loongarch_get_addr_from_tlb

With function loongarch_get_addr_from_tlb(), parameter MMUContext is added and remove parameter physical, prot and address. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c| 7 +-- target/loongarch/tcg/tcg_loongarch.h | 4 ++-- target/loongarch/tcg/tlb_helper.c| 18 +++

[PATCH v4 09/19] target/loongarch: Use loongarch_check_pte in loongarch_page_table_walker

Function loongarch_check_pte() can get physical address and access priviledge, it works on both TLB entry and pte entry. It can be used in function loongarch_page_table_walker() also. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu_helper.c | 42 +

[PATCH v4 06/19] target/loongarch: Use vaddr in get_physical_address()

Replace target_ulong type with vaddr in function get_physical_address() and the same with its calling functions. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h| 2 +- target/loongarch/cpu_helper.c | 9 - target/loongarch/tcg/tlb_helper.c | 11 ++- 3 files ch

[PATCH v4 03/19] target/loongarch: Set page size in TLB entry with STLB

With VTLB different TLB entry may have different page size, and page size is set in PS field of TLB entry. However with STLB, all the TLB entries have the same page size, page size comes from register CSR_STLBPS, PS field of TLB entry is not used. Here PS field of TLB entry is used with all TLB en

RE: [PATCH v1 19/21] pc-bios: Update AST27x0 vBootrom with SSP/TSP SCU initialization support

Hi Cédric, Michael > From: Cédric Le Goater > Sent: Tuesday, July 29, 2025 5:12 PM > To: Jamin Lin ; Michael Tokarev > ; Peter Maydell ; Steven Lee > ; Troy Lee ; Andrew > Jeffery ; Joel Stanley ; open > list:ASPEED BMCs ; open list:All patches CC here > > Cc: Troy Lee ; Hao Wu ; > Havard Skinne

[PATCH v1] roms/vbootrom: update to 7b1eb5f

Changes: 7b1eb5f ast27x0: Fix Makefile to unconditionally set CC to support correct cross-compilation 601d410 ast27x0: Fix missing SCU module reset for SSP and TSP initialization 80768e4 ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory from DTB f8ab635 ast27x0: Show build dat

Re: [PULL 00/11] riscv-to-apply queue

On Wed, Jul 30, 2025 at 11:01 AM wrote: > > From: Alistair Francis > > The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e: > > Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400) > > are available in the Git repository at: > > https://github.com/ali

[PULL 03/11] hw/riscv/virt-acpi-build.c: Update FADT and MADT versions

From: Sunil V L RISC-V support is added only in ACPI 6.6. According to the ACPI 6.6 specification, the minor version of the Fixed ACPI Description Table (FADT) should be 6, and the Multiple APIC Description Table (MADT) should use revision 7. So, update the RISC-V FADT and MADT to reflect correct

[PULL 01/11] target/riscv: Fix pmp range wraparound on zero

From: Vac Chen pmp_is_in_range() prefers to match addresses within the interval [start, end]. To archieve this, pmpaddrX is decremented during the end address update. In TOR mode, a rule is ignored if its start address is greater than or equal to its end address. However, if pmpaddrX is set to

[PULL 10/11] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts

From: Jay Chang RISC-V Privileged Spec states: "In harts with S-mode, the medeleg and mideleg registers must exist, and setting a bit in medeleg or mideleg will delegate the corresponding trap , when occurring in S-mode or U-mode, to the S-mode trap handler. In harts without S-mode, the medeleg a

[PULL 11/11] target/riscv: Restrict midelegh access to S-mode harts

From: Jay Chang RISC-V AIA Spec states: "For a machine-level environment, extension Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels. For a supervisor-level environment, extension Ssaia is essentiall

[PULL 09/11] target/riscv: Fix exception type when VU accesses supervisor CSRs

From: Xu Lu When supervisor CSRs are accessed from VU-mode, a virtual instruction exception should be raised instead of an illegal instruction. Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking) Signed-off-by: Xu Lu Reviewed-by: Anup Patel Reviewed-by: Nutty Liu Message

[PULL 07/11] target/riscv: do not call GETPC() in check_ret_from_m_mode()

From: Daniel Henrique Barboza GETPC() should always be called from the top level helper, e.g. the first helper that is called by the translation code. We stopped doing that in commit 3157a553ec, and then we introduced problems when unwinding the exceptions being thrown by helper_mret(), as report

[PULL 05/11] intc/riscv_aplic: Fix target register read when source is inactive

From: Yang Jialong The RISC-V Advanced interrupt Architecture: 4.5.16. Interrupt targets: If interrupt source i is inactive in this domain, register target[i] is read-only zero. Signed-off-by: Yang Jialong Reviewed-by: Daniel Henrique Barboza Message-ID: <20250728055114.252024-1-z_baj...@yeah.

Re: [PATCH] target/xtensa: Replace malloc() with g_strdup_printf()

On Tue, Jul 29, 2025 at 4:12 AM Dmitry Frolov wrote: > > malloc() return value is used without a check. > > Found by Linux Verification Center (linuxtesting.org) with SVACE. > > Signed-off-by: Dmitry Frolov > --- > target/xtensa/translate.c | 9 ++--- > 1 file changed, 2 insertions(+), 7 del

[PULL 02/11] bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes

From: Sunil V L Signed-off-by: Sunil V L Acked-by: Michael S. Tsirkin Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Message-ID: <20250724110350.452828-2-suni...@ventanamicro.com> Signed-off-by: Alistair Francis --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file cha

[PULL 04/11] tests/data/acpi/riscv64: Update expected FADT and MADT

From: Sunil V L Update the expected tables for the version change. /* * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 004h] Signature : "FACP"[Fixed ACPI Description Table (FADT)] [004

[PULL 06/11] linux-user/strace.list: add riscv_hwprobe entry

From: Daniel Henrique Barboza We're missing a strace entry for riscv_hwprobe, and using -strace will report it as "Unknown syscall 258". After this patch we'll have: $ ./build/qemu-riscv64 -strace test_mutex_riscv 110182 riscv_hwprobe(0x7f207efdc700,1,0,0,0,0) = 0 110182 brk(NULL) = 0x0

[PULL 08/11] riscv: Revert "Generate strided vector loads/stores with tcg nodes."

From: Daniel Henrique Barboza This reverts commit 28c12c1f2f50d7f7f1ebfc587c4777ecd50aac5b. As reported in [1] this commit is breaking Linux vector code, and although a simpler reproducer was provided, the fix itself isn't trivial due to the amount and the nature of the changes. And we really do

[PULL 00/11] riscv-to-apply queue

From: Alistair Francis The following changes since commit 9b80226ece693197af8a981b424391b68b5bc38e: Update version for the v10.1.0-rc1 release (2025-07-29 13:00:41 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20250730-2 for

Re: [PULL 02/20] target/arm: Correct encoding of Debug Communications Channel registers

Fabiano Rosas writes: > Fabiano Rosas writes: > >> Peter Maydell writes: >> >>> On Wed, 23 Jul 2025 at 23:20, Fabiano Rosas wrote: Peter Maydell writes: > We don't implement the Debug Communications Channel (DCC), but > we do attempt to provide dummy versions of its s

[PATCH 85/89] linux-user/sparc: Move target_pt_regs to signal.c

This structure is part of the sparc signal frame. Signed-off-by: Richard Henderson --- linux-user/sparc/target_syscall.h | 19 --- linux-user/sparc/signal.c | 20 2 files changed, 20 insertions(+), 19 deletions(-) diff --git a/linux-user/sparc/target

[PATCH 69/89] linux-user: Move elf parameters to microblaze/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/microblaze/target_elf.h | 5 + linux-user/elfload.c | 10 -- 2 files changed, 5 insertions(+), 10 deletions(-) diff --git a/linux-user/microblaze/target_elf.h b/linux-user/microblaze/target_elf.h index bfe2997fd2..738a10

[PATCH 61/89] linux-user: Move get_elf_cpu_model to target/elfload.c

Rename from cpu_get_model to emphasize that this is an elf-specific function. Declare the function once in loader.h. This frees up target_elf.h for other uses. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_elf.h | 5 +--- linux-user/alpha/target_elf.h | 5 +--- lin

[PATCH 38/89] linux-user/xtensa: Create init_main_thread

Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 18 +- linux-user/xtensa/cpu_loop.c | 22 -- 2 files changed, 17 insertions(+), 23 del

[PATCH 54/89] linux-user: Unify the include of target_coredump.c.inc

Now that all target_coredump.c.inc files have been created, USE_ELF_CORE_DUMP signals that it is available. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 16 +--- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c i

[PATCH 03/89] linux-user: Move hwcap functions to {arm, aarch64}/elfload.c

For get_elf_hwcap and get_elf_hwcap2, change the return type to abi_ulong, and pass in the cpu. We must do these targets at the same time because of the ifdef dependency between TARGET_AARCH64 and TARGET_ARM. Signed-off-by: Richard Henderson --- linux-user/arm/target_proc.h | 4 +- linux-user

[PATCH 60/89] linux-user: Remove ELF_EXEC_PAGESIZE

Use TARGET_PAGE_SIZE instead. If the target page size may vary, using a different fixed size is wrong. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 21 ++--- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c

[PATCH 86/89] linux-user/microblaze: Move target_pt_regs to signal.c

This structure is part of the microblaze signal frame. Signed-off-by: Richard Henderson --- linux-user/microblaze/target_syscall.h | 44 -- linux-user/microblaze/signal.c | 44 ++ 2 files changed, 44 insertions(+), 44 deletions(-) diff --g

[PATCH 66/89] linux-user: Move elf parameters to ppc/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/ppc/target_elf.h | 45 ++ linux-user/elfload.c| 55 - 2 files changed, 45 insertions(+), 55 deletions(-) diff --git a/linux-user/ppc/target_elf.h b/linux-user/ppc/target_elf.h

[PATCH 40/89] linux-user: Remove do_init_main_thread

All targets have been converted, so we can call init_main_thread directly. Remove do_init_main_thread and HAVE_INIT_MAIN_THREAD. Signed-off-by: Richard Henderson --- linux-user/loader.h | 1 - linux-user/qemu.h| 2 -- linux-user/elfload.c | 46

[PATCH 62/89] linux-user: Move ppc uabi/asm/elf.h workaround to osdep.h

Move the workaround out of linux-user/elfload.c, so that we don't have to replicate it in many places. Place it immediately after the include of , which draws in the relevant symbols. Signed-off-by: Richard Henderson --- include/qemu/osdep.h | 8 linux-user/elfload.c | 7 --- 2 fil

[PATCH 49/89] target/openrisc: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 17 + linux-user/openrisc/target_coredump.c.inc | 15 +++ 2 files changed, 16 insertions(+), 16 deletions(-) create mode 100644 linux-user/openrisc/target_coredump.c.inc diff --git a/lin

[PATCH 88/89] linux-user/s390x: Move target_psw_t to signal.c

Remove struct target_pt_regs as unused. Move target_psw_t to signal.c, as it is used there. Signed-off-by: Richard Henderson --- linux-user/s390x/target_syscall.h | 22 -- linux-user/s390x/signal.c | 5 + 2 files changed, 5 insertions(+), 22 deletions(-) diff --

[PATCH 87/89] linux-user/openrisc: Move target_pt_regs to signal.c

This structure is part of the openrisc signal frame. Signed-off-by: Richard Henderson --- linux-user/openrisc/target_syscall.h | 11 --- linux-user/openrisc/signal.c | 12 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/linux-user/openrisc/target_sys

[PATCH 82/89] linux-user: Remove MAP_DENYWRITE from elfload.c

The last use of this fallback was removed in bf858897b769. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 5 - 1 file changed, 5 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 6eb4e31bdb..14d4502b3c 100644 --- a/linux-user/elfload.c +++ b/linux-user

[PATCH 89/89] linux-user: Remove struct target_pt_regs from target_syscall.h

This structure is unused, and would only ever be used for the ptrace syscall, which we will never implement for linux-user. Signed-off-by: Richard Henderson --- linux-user/aarch64/target_syscall.h | 7 - linux-user/alpha/target_syscall.h | 40 - linux-user/

[PATCH 67/89] linux-user: Move elf parameters to loongarch64/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/loongarch64/target_elf.h | 7 +++ linux-user/elfload.c| 14 -- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/linux-user/loongarch64/target_elf.h b/linux-user/loongarch64/target_elf.h index 39a08d35

[PATCH 81/89] linux-user: Remove ELIBBAD from elfload.c

The last use of this fallback was removed in 8e62a71738bc. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 5 - 1 file changed, 5 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 5185c84e58..6eb4e31bdb 100644 --- a/linux-user/elfload.c +++ b/linux-user

[PATCH 80/89] linux-user: Rename elf_check_arch

Rename to elf_check_machine to match ELF_MACHINE. Remove the unnecessary definition for loongarch64. Signed-off-by: Richard Henderson --- linux-user/i386/target_elf.h| 2 +- linux-user/loongarch64/target_elf.h | 1 - linux-user/microblaze/target_elf.h | 2 +- linux-user/sparc/target_elf

[PATCH 51/89] linux-user/m68k: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 29 +- linux-user/m68k/target_coredump.c.inc | 30 +++ 2 files changed, 31 insertions(+), 28 deletions(-) create mode 100644 linux-user/m68k/target_coredump.c.inc diff --

[PATCH 50/89] target/sh4: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 34 +--- linux-user/sh4/target_coredump.c.inc | 32 ++ 2 files changed, 33 insertions(+), 33 deletions(-) create mode 100644 linux-user/sh4/target_coredump.c.inc diff --gi

[PATCH 74/89] linux-user: Move elf parameters to s390x/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/s390x/target_elf.h | 6 ++ linux-user/elfload.c | 12 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/linux-user/s390x/target_elf.h b/linux-user/s390x/target_elf.h index e51b053339..aa12ecf36b 100644 --- a/

[PATCH 15/89] linux-user: Move get_elf_platform to arm/elfload.c

Move the aarch32 get_elf_platform to arm/elfload.c; pass in CPUState. Create a simple version in aarch64/elfload.c, which we must do at the same time because of the ifdef dependency between TARGET_AARCH64 and TARGET_ARM. Since all versions of get_elf_platform now have the same signature, remove th

[PATCH 19/89] linux-user: Move get_elf_base_platform to mips/elfload.c

Pass in CPUState. Since this was the only instance of ELF_BASE_PLATFORM, go ahead provide a weak fallback for all other targets. Signed-off-by: Richard Henderson --- linux-user/loader.h | 1 + linux-user/elfload.c | 42 ++- linux-user/mips/elfload

[PATCH 70/89] linux-user: Move elf parameters to openrisc/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/openrisc/target_elf.h | 4 linux-user/elfload.c | 10 -- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/linux-user/openrisc/target_elf.h b/linux-user/openrisc/target_elf.h index b34f2ff672..0a2b3ef762 10064

[PATCH 57/89] linux-user: Move init_guest_commpage to hppa/elfload.c

Signed-off-by: Richard Henderson --- linux-user/hppa/target_elf.h | 4 linux-user/loader.h | 2 -- linux-user/elfload.c | 32 linux-user/hppa/elfload.c| 31 +++ 4 files changed, 35 insertions(+), 34 deletions

[PATCH 84/89] linux-user: Remove a.out declarations from elfload.c

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 19 --- 1 file changed, 19 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 54ea9221d9..e8d5b56cfb 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -196,25 +196,6 @@ bool arch_pa

[PATCH 28/89] linux-user/loongarch64: Create init_main_thread

Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Note that init_thread had set crmd in target_pt_regs, but target_cpu_copy_regs did not copy to env. This turns out to be ok because loongarch_cpu_reset_hold initializes CRMD properly. Signed

[PATCH 58/89] linux-user: Remove INIT_GUEST_COMMPAGE

Provide a weak stub version of init_guest_commpage instead of using the preprocessor. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 8ebde57fa5..01c39bf456

[PATCH 30/89] linux-user/microblaze: Create init_main_thread

Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 8 +-- linux-user/microblaze/cpu_loop.c | 39 2 files changed, 6 insertions(+),

[PATCH 77/89] linux-user: Move elf parameters to xtensa/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/xtensa/target_elf.h | 4 linux-user/elfload.c | 9 - 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/linux-user/xtensa/target_elf.h b/linux-user/xtensa/target_elf.h index 2c55c22e14..cacfb6e81a 100644 --- a/linu

[PATCH 78/89] linux-user: Move elf parameters to hexagon/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/hexagon/target_elf.h | 3 +++ linux-user/elfload.c| 7 --- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/linux-user/hexagon/target_elf.h b/linux-user/hexagon/target_elf.h index eccf207f6b..a9f6d77fc6 100644 --- a/lin

[PATCH 41/89] linux-user/x86_64: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c| 41 +--- linux-user/x86_64/target_coredump.c.inc | 42 + 2 files changed, 43 insertions(+), 40 deletions(-) create mode 100644 linux-user/x86_64/target_coredump.c.inc diff

[PATCH 47/89] linux-user/mips: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c| 46 + linux-user/mips/target_coredump.c.inc | 46 + linux-user/mips64/target_coredump.c.inc | 1 + 3 files changed, 48 insertions(+), 45 deletions(-) create mode 1006

[PATCH 75/89] linux-user: Move elf parameters to riscv/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/riscv/target_elf.h | 10 ++ linux-user/elfload.c | 14 -- 2 files changed, 10 insertions(+), 14 deletions(-) diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h index bfe86105d0..61446dd945 100644

[PATCH 71/89] linux-user: Move elf parameters to sh4/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/sh4/target_elf.h | 4 linux-user/elfload.c| 9 - 2 files changed, 4 insertions(+), 9 deletions(-) diff --git a/linux-user/sh4/target_elf.h b/linux-user/sh4/target_elf.h index d17011bd75..68b58beaa4 100644 --- a/linux-user/sh4/t

[PATCH 55/89] linux-user: Move init_guest_commpage to x86_64/elfload.c

Signed-off-by: Richard Henderson --- linux-user/loader.h | 3 +++ linux-user/elfload.c| 20 linux-user/x86_64/elfload.c | 20 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/linux-user/loader.h b/linux-user/loader.h index

[PATCH 73/89] linux-user: Move elf parameters to alpha/target_elf.h

Signed-off-by: Richard Henderson --- linux-user/alpha/target_elf.h | 3 +++ linux-user/elfload.c | 7 --- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/linux-user/alpha/target_elf.h b/linux-user/alpha/target_elf.h index 52b68680ad..f9d6372c9f 100644 --- a/linux-user/

[PATCH 02/89] linux-user: Move get_elf_hwcap to {i386, x86_64}/elfload.c

Change the return type to abi_ulong, and pass in the cpu. Duplicate the one line function between i386 and x86_64, as most other additions to elfload.c won't be common. Signed-off-by: Richard Henderson --- linux-user/loader.h | 3 +++ linux-user/elfload.c| 9 + linux-us

[PATCH 42/89] linux-user/i386: Split out target_coredump.c.inc

Signed-off-by: Richard Henderson --- linux-user/elfload.c | 31 +- linux-user/i386/target_coredump.c.inc | 32 +++ 2 files changed, 33 insertions(+), 30 deletions(-) create mode 100644 linux-user/i386/target_coredump.c.inc diff --

[PATCH 37/89] linux-user/hppa: Create init_main_thread

Merge init_thread and target_cpu_copy_regs. There's no point going through a target_pt_regs intermediate. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 13 + linux-user/hppa/cpu_loop.c | 18 +++--- 2 files changed, 12 insertions(+), 19 deletions(-) di

[PATCH 59/89] linux-user: Move get_vdso_image_info to arm/elfload.c

Rename from vdso_image_info to avoid a symbol clash. Provide fallback versions for other targets. Signed-off-by: Richard Henderson --- linux-user/loader.h | 12 linux-user/arm/elfload.c | 20 linux-user/elfload.c | 41 ++-

[PATCH 18/89] linux-user: Remove ELF_PLATFORM

All real definitions of ELF_PLATFORM are now identical, and the stub definitions are NULL. Provide a weak stub as a fallback definition. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 21 ++--- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/linux-use

[PATCH 83/89] linux-user: Move arch_parse_elf_property to aarch64/elfload.c

Signed-off-by: Richard Henderson --- linux-user/aarch64/target_elf.h | 1 + linux-user/loader.h | 5 + linux-user/aarch64/elfload.c| 18 + linux-user/elfload.c| 35 ++--- 4 files changed, 30 insertions(+), 29 deletions(

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