Re: [PATCH 03/15] hw/intc/loongarch_extioi: Add irqchip-in-kernel save/restore function

在2025年5月19日周一 上午3:56，Bibo Mao写道： [...] >> >> Hi Bibo, >> >> I believe hijacking loongarch_extioi.c is not the proper way to do it. >> The sensible solution is to create a TYPE_LOONGARCH_EXTIOI_KVM, which >> inherits TYPE_LOONGARCH_EXTIOI_COMMON, and let machine create >> TYPE_LOONGARCH_EXTIOI_

Re: [PATCH v2 08/12] qapi: Make CpuModelExpansionInfo::deprecated-props optional and generic

Pierrick Bouvier writes: > From: Philippe Mathieu-Daudé > > We'd like to have some unified QAPI schema. Having a structure field > conditional to a target being built in is not very practical. > > While @deprecated-props is only used by s390x target, it is generic > enough and could be used by o

Re: [PATCH] vfio/igd: Respect x-igd-opregion=off in IGD quirk handling

Hello, On 5/19/25 02:01, edmund.raile wrote: Restore SR-IOV Intel iGPU VF passthrough capability: Check x-igd-opregion=off parameter in vfio_pci_igd_config_quirk and vfio_pci_kvmgt_config_quirk to ensure x-igd-opregion=off is respected despite subsequent attempt of automatic IGD opregion detecti

Re: [PATCH v2 02/12] qapi: expand docs for SEV commands

Pierrick Bouvier writes: > From: Daniel P. Berrangé > > This gives some more context about the behaviour of the commands in > unsupported guest configuration or platform scenarios. > > Reviewed-by: Richard Henderson > Signed-off-by: Daniel P. Berrangé > Signed-off-by: Pierrick Bouvier > --- >

[PATCH] hw/s390x/s390-virtio-ccw: Remove the deprecated 4.1 machine type

From: Thomas Huth With the upcoming release of QEMU 10.1, the s390-ccw-virtio-4.1 machine will be older than 6 years, so according to our machine support policy, it can be removed now. The V4_1 CPU feature group gets merged into the minimum CPU feature group now. Signed-off-by: Thomas Huth ---

[PULL 00/56] riscv-to-apply queue

From: Alistair Francis The following changes since commit 757a34115e7491744a63dfc3d291fd1de5297ee2: Merge tag 'pull-nvme-20250515' of https://gitlab.com/birkelund/qemu into staging (2025-05-15 13:42:27 -0400) are available in the Git repository at: https://github.com/alistair23/qemu.git t

[PULL 27/56] target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions

From: Max Chou Handle the overlap of source registers with different EEWs. The vd of vector widening mul-add instructions is one of the input operands. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-9-max.c...@s

Re: [PATCH V3 4/4] acpi/virt: suppress UART device & SPCR when guest has no serial hardware

On Thu, May 15, 2025 at 08:44:39PM +0800, Li Chen wrote: > From: Li Chen > > The virt machines always instantiate a PL011/16550 at UART0 and > describe it in ACPI (DSDT device node plus optional SPCR table). When > the command line contains “-serial none” there is no backend attached to > that U

[PULL 22/56] target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to check mismatched input EEWs encoding constraint

From: Max Chou According to the v spec, a vector register cannot be used to provide source operands with more than one EEW for a single instruction. The vs1 EEW of vrgatherei16.vv is 16. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <

[PULL 50/56] hw/riscv/virt.c: use s->memmap in virt_machine_done()

From: Daniel Henrique Barboza Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-4-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 15 +++ 1 file changed, 7 insertions(+), 8 deletions(-) diff --

[PULL 05/56] target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode

From: Loïc Lefort With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg writes would match the wrong cases of Smepmp truth table. The existing code allows writes for the following cases: - L=1, X=0: cases 8, 10, 12, 14 - L=0, RWX!=WX: cases 0-2, 4-6 This leaves cases 3,

[PULL 48/56] hw/riscv/virt.c: enforce s->memmap use in machine_init()

From: Daniel Henrique Barboza Throughout the code we're accessing the board memmap, most of the time, by accessing it statically via 'virt_memmap'. This static map is also assigned in the machine state in s->memmap. We're also passing it as a variable to some fdt functions, which is unorthodox s

[PULL 23/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

From: Max Chou Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-5-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- t

[PULL 32/56] target/riscv: Pass ra to riscv_csr_write_fn

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-2-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 3 +-

[PULL 16/56] Expand the probe_pages helper function to handle probe flags.

From: Paolo Savini This commit expands the probe_pages helper function in target/riscv/vector_helper.c to handle also the cases in which we need access to the flags raised while probing the memory and the host address. This is done in order to provide a unified interface to probe_access and probe

[PULL 55/56] hw/riscv/virt.c: use s->memmap in finalize_fdt() functions

From: Daniel Henrique Barboza Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and create_fdt_rtc() to use s->memmap in their logic. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-9-dbarb...@ventanamicro.com> Signed-off-by

[PULL 54/56] hw/riscv/virt.c: use s->memmap in create_fdt_virtio()

From: Daniel Henrique Barboza create_fdt_virtio() can use s->memmap instead of having an extra argument for it. While we're at it rewrite it a little bit to avoid the clunky line in 'name' and code repetition: - declare 'virtio_base' out of the loop since it never changes; - declare a 'size' va

[PULL 20/56] target/riscv: rvv: Source vector registers cannot overlap mask register

From: Anton Blanchard Add the relevant ISA paragraphs explaining why source (and destination) registers cannot overlap the mask register. Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-2-ma

[PULL 40/56] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()

From: Daniel Henrique Barboza 'reglist' is being g-malloc'ed but never freed. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Message-ID: <20250429124421.223883-3-dbarb...@ventanamicro.com> Signed-off-by: Alistair Franc

[PULL 37/56] target/riscv: Move insn_len to internals.h

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-7-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/internals.h | 5

[PULL 42/56] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro

From: Daniel Henrique Barboza We need the reg_id_ulong() helper to be a macro to be able to create a static array of KVMCPUConfig that will hold CSR information. Despite the amount of changes all of them are tedious/trivial: - replace instances of "kvm_riscv_reg_id_ulong" with "KVM_RISCV_REG_

[PULL 31/56] MAINTAINERS: Add common-user/host/riscv to RISC-V section

From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250422024752.2060289-1-alistair.fran...@wdc.com> Signed-off-by: Alistair Francis --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 57dddc

[PULL 35/56] target/riscv: Pass ra to riscv_csrrw

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-5-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8

[PULL 41/56] target/riscv/kvm: turn u32/u64 reg functions into macros

From: Daniel Henrique Barboza This change is motivated by a future change w.r.t CSRs management. We want to handle them the same way as KVM extensions, i.e. a static array with KVMCPUConfig objs that will be read/write during init and so on. But to do that properly we must be able to declare a st

[PULL 24/56] target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

From: Max Chou Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-6-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- t

[PULL 38/56] target/riscv: Fix write_misa vs aligned next_pc

From: Richard Henderson Do not examine a random host return address, but properly compute the next pc for the guest cpu. Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-b

[PULL 09/56] hw/misc: Add MPFS system reset support

From: Sebastian Huber Signed-off-by: Sebastian Huber Acked-by: Alistair Francis Message-ID: <20250319061342.26435-2-sebastian.hu...@embedded-brains.de> Signed-off-by: Alistair Francis --- hw/misc/mchp_pfsoc_sysreg.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/hw/misc/mchp_pfsoc

[PULL 51/56] hw/riscv/virt.c: add 'base' arg in create_fw_cfg()

From: Daniel Henrique Barboza The function can receive the value via s->memmap[VIRT_FW_CFG].base from the caller, avoiding the use of virt_memmap. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-5-dbar

[PULL 47/56] target/riscv/kvm: add scounteren CSR

From: Daniel Henrique Barboza Add support for the scounteren KVM CSR. Note that env->scounteren is a 32 bit and all KVM CSRs are target_ulong, so scounteren will be capped to 32 bits read/writes. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Review

[PULL 46/56] target/riscv/kvm: read/write KVM regs via env size

From: Daniel Henrique Barboza We're going to add support for scounteren in the next patch. KVM defines as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit field. This will cause the current code to read/write a 64 bit CSR in a 32 bit field when running in a 64 bit CPU. To preve

[PULL 49/56] hw/riscv/virt.c: remove trivial virt_memmap references

From: Daniel Henrique Barboza We should use s->memmap instead of virt_memmap to be able to use an updated memmap when we start versioning the board. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-3-dbarb...@ventanamicro.com> Signed-off-b

[PULL 43/56] target/riscv/kvm: add kvm_csr_cfgs[]

From: Daniel Henrique Barboza At this moment we're not checking if the host has support for any specific CSR before doing get/put regs. This will cause problems if the host KVM doesn't support it (see [1] as an example). We'll use the same approach done with the CPU extensions: read all known KV

[PULL 53/56] hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path

From: Daniel Henrique Barboza create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(), create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_aclint() and create_fdt_socket_memory()) can use s->memmap from their RISCVVirtState pointer instead of having an extra memmap arg

[PULL 15/56] target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.

From: Paolo Savini This patch replaces the use of a helper function with direct tcg ops generation in order to emulate whole register loads and stores. This is done in order to improve the performance of QEMU. We still use the helper function when vstart is not 0 at the beginning of the emulation

[PULL 44/56] target/riscv/kvm: do not read unavailable CSRs

From: Daniel Henrique Barboza [1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. This happens because the kernel does not know 'senvcfg', making it unable to boot because QEMU is reading/wriiting it without any checks. After converting the CSRs to do "automated" get/put reg

[PULL 45/56] target/riscv/kvm: add senvcfg CSR

From: Daniel Henrique Barboza We're missing the senvcfg CSRs which is already present in the KVM UAPI. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones Acked-by: Alistair Francis Message-ID: <20250429124421.223883-8-dbarb...@ventanamicro.com> Signed-

[PULL 17/56] hw/riscv: Fix type conflict of GLib function pointers

From: Paolo Bonzini qtest_set_command_cb passed to g_once should match GThreadFunc, which it does not. But using g_once is actually unnecessary, because the function is called by riscv_harts_realize() under the Big QEMU Lock. Reported-by: Kohei Tokunaga Signed-off-by: Paolo Bonzini Reviewed-b

[PULL 30/56] target/riscv: Fix vslidedown with rvv_ta_all_1s

From: Anton Blanchard vslidedown always zeroes elements past vl, where it should use the tail policy. Signed-off-by: Anton Blanchard Reviewed-by: Alistair Francis Message-ID: <20250414213006.3509058-1-ant...@tenstorrent.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- targ

[PULL 56/56] hw/riscv/virt.c: remove 'long' casts in fmt strings

From: Daniel Henrique Barboza We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt strings for uint64_t and hwaddr types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-10-dbarb...

Re: [PATCH V3 1/4] acpi: Add machine option to disable SPCR table

On Thu, May 15, 2025 at 08:41:03PM +0800, Li Chen wrote: > From: Li Chen > > The ACPI SPCR (Serial Port Console Redirection) table allows firmware > to specify a preferred serial console device to the operating system. > On ARM64 systems, Linux by default respects this table: even if the > kernel

[PULL 08/56] Generate strided vector loads/stores with tcg nodes.

From: Paolo Savini This commit improves the performance of QEMU when emulating strided vector loads and stores by substituting the call for the helper function with the generation of equivalent TCG operations. Signed-off-by: Paolo Savini Reviewed-by: Daniel Henrique Barboza Message-ID: <202503

[PULL 34/56] target/riscv: Pass ra to riscv_csrrw_do128

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-4-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 9 +

[PULL 21/56] target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

From: Anton Blanchard Signed-off-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Reviewed-by: Max Chou Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-3-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- target/riscv/insn_trans/trans_rvv

[PULL 36/56] target/riscv: Pass ra to riscv_csrrw_i128

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-6-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4

[PULL 11/56] hw/riscv: Make FDT optional for MPFS

From: Sebastian Huber Real-time kernels such as RTEMS or Zephyr may use a static device tree built into the kernel image. Do not require to use the -dtb option if -kernel is used for the microchip-icicle-kit machine. Issue a warning if no device tree is provided by the user since the machine do

[PULL 03/56] target/riscv: pmp: don't allow RLB to bypass rule privileges

From: Loïc Lefort When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs but should not affect interpretation of actual PMP rules. This is not the case with the current implementation where pmp_hart_has_privs calls pmp_is_locked which implements mseccfg.RLB bypass. This

[PULL 06/56] target/riscv: pmp: exit csr writes early if value was not changed

From: Loïc Lefort Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250313193011.720075-5-l...@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 22 +++--- 1 file changed,

[PULL 33/56] target/riscv: Pass ra to riscv_csrrw_do64

From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250425152311.804338-3-richard.hender...@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/csr.c | 15

[PULL 29/56] target/riscv: Fix the rvv reserved encoding of unmasked instructions

From: Max Chou According to the v spec, the encodings of vcomoress.vm and vector mask-register logical instructions with vm=0 are reserved. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-11-max.c...@sifive.com> Signed-off-by: Alistair Francis

[PULL 25/56] target/riscv: rvv: Apply vext_check_input_eew to vector slide instructions(OPIVI/OPIVX)

From: Max Chou Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-7-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- t

[PULL 39/56] target/riscv/kvm: minor fixes/tweaks

From: Daniel Henrique Barboza Remove an unused 'KVMScratchCPU' pointer argument in kvm_riscv_check_sbi_dbcn_support(). Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will make a future patch diff easier to read, when changes in kvm_riscv_reset_regs_csr() and kvm_riscv_get_re

[PULL 52/56] hw/riscv/virt.c: use s->memmap in create_fdt() path

From: Daniel Henrique Barboza create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the memmap via their RISCVVirtState pointers. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20250429125811.224803-6-dbarb...@ventanamicro.com> Signed-off-by: Al

[PULL 01/56] hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure

From: Sunil V L When the IOMMU is implemented as a PCI device, its BDF is created locally in virt.c. However, the same BDF is also required in virt-acpi-build.c to support ACPI. Therefore, make this information part of the global RISCVVirtState structure so that it can be accessed outside of virt

[PULL 04/56] target/riscv: pmp: move Smepmp operation conversion into a function

From: Loïc Lefort Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250313193011.720075-3-l...@rivosinc.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- target/riscv/pmp.c | 22

[PULL 13/56] hw/riscv: Configurable MPFS CLINT timebase freq

From: Sebastian Huber This property enables the setting of the CLINT timebase frequency through the command line, for example: -machine microchip-icicle-kit,clint-timebase-frequency=1000 Signed-off-by: Sebastian Huber Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Me

[PULL 28/56] target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

From: Max Chou Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-10-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org ---

[PULL 26/56] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

From: Max Chou Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard Reviewed-by: Daniel Henrique Barboza Signed-off-by: Max Chou Message-ID: <20250408103938.3623486-8-max.c...@sifive.com> Signed-off-by: Alistair Francis Cc: qemu-sta...@nongnu.org --- t

[PULL 19/56] common-user/host/riscv: use tail pseudoinstruction for calling tail

From: Icenowy Zheng The j pseudoinstruction maps to a JAL instruction, which can only handle a jump to somewhere with a signed 20-bit destination. In case of static linking and LTO'ing this easily leads to "relocation truncated to fit" error. Switch to use tail pseudoinstruction, which is the st

[PULL 18/56] target/riscv: fix endless translation loop on big endian systems

From: Ziqiao Kong On big endian systems, pte and updated_pte hold big endian host data while pte_pa points to little endian target data. This means the branch at cpu_helper.c:1669 will be always satisfied and restart translation, causing an endless translation loop. The correctness of this patch

[PULL 14/56] hw/riscv: microchip_pfsoc: Rework documentation

From: Sebastian Huber Mention that running the HSS no longer works. Document the changed boot options. Reorder documentation blocks. Update URLs. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis Message-ID: <20250319061342.26435-7-sebastian.hu...@embedded-brains.de> Signed-off-b

[PULL 12/56] hw/riscv: Allow direct start of kernel for MPFS

From: Sebastian Huber Further customize the -bios and -kernel options behaviour for the microchip-icicle-kit machine. If "-bios none -kernel filename" is specified, then do not load a firmware and instead only load and start the kernel image. For test runs, use an approach similar to riscv_find

[PULL 10/56] hw/riscv: More flexible FDT placement for MPFS

From: Sebastian Huber If the kernel entry is in the high DRAM area, place the FDT into this area. Signed-off-by: Sebastian Huber Reviewed-by: Alistair Francis Message-ID: <20250319061342.26435-3-sebastian.hu...@embedded-brains.de> Signed-off-by: Alistair Francis --- hw/riscv/microchip_pfsoc.

[PULL 02/56] hw/riscv/virt-acpi-build: Add support for RIMT

From: Sunil V L RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to communicate IOMMU information to the OS. Add support for creating this table when the IOMMU is present. The specification is frozen and available at [1]. [1] - https://github.com/riscv-non-isa/riscv-acpi-rimt/rele

[PULL 07/56] target/riscv: pmp: remove redundant check in pmp_is_locked

From: Loïc Lefort Remove useless check in pmp_is_locked, the function will return 0 in either case. Signed-off-by: Loïc Lefort Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20250313193011.720075-6-l...@rivosinc.com> Signed-off-by: Ali

Re: [PATCH V3 3/4] tests/qtest/bios-tables-test: Add test for disabling SPCR on RISC-V

On Thu, May 15, 2025 at 08:43:07PM +0800, Li Chen wrote: > From: Li Chen > > Add ACPI SPCR table test case for RISC-V when SPCR was off. > > Signed-off-by: Li Chen > --- > tests/qtest/bios-tables-test.c | 22 ++ > 1 file changed, 22 insertions(+) > > diff --git a/tests/qt

Re: [PATCH v3 1/2] hw/i386/amd_iommu: Fix device setup failure when PT is on.

On 5/16/2025 8:13 PM, Philippe Mathieu-Daudé wrote: On 16/5/25 12:05, Sairaj Kodilkar wrote: Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode") introduces the support for "pt" flag by enabling nodma memory when "pt=off". This allowed VFIO devices to successfully register not

Re: [PATCH v2] target/riscv/kvm: add satp mode for host cpu

On Mon, Apr 28, 2025 at 6:57 PM Meng Zhuo wrote: > > This patch adds host satp mode while kvm/host cpu satp mode is not > set. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 > Signed-off-by: Meng Zhuo Can you please rebase this on https://github.com/alistair23/qemu/tree/riscv-t

RE: [PATCH V3 39/42] vfio/iommufd: reconstruct hwpt

>-Original Message- >From: Steve Sistare >Subject: [PATCH V3 39/42] vfio/iommufd: reconstruct hwpt > >Save the hwpt_id in vmstate. In realize, skip its allocation from >iommufd_cdev_attach -> iommufd_cdev_attach_container -> >iommufd_cdev_autodomains_get. > >Rebuild userland structures

Re: [PATCH v2 0/4] Several sstc extension fixes

On Wed, Apr 9, 2025 at 12:53 PM Jim Shu wrote: > > This patch series contains several sstc fixes: > > (1) Writing to ACLINT mtime should also update the period of S/VS-mode > timer, just like M-mode timer. > (2) VSTIP bit of $mip CSR should check both M-mode and H-mode STCE. > (3) Writing to S

Re: [PATCH 4/6] tests/acpi: Add empty ACPI data files for LoongArch64

On 2025/4/1 下午9:48, Igor Mammedov wrote: On Fri, 28 Feb 2025 17:27:27 +0800 Bibo Mao wrote: Add empty acpi table for LoongArch64 virt machine, it is only empty file and there is no data in these files. this patch after 3/6 doesn't make sense, either drop. Empty acpi table can be dropped.

Re: [PATCH 03/15] hw/intc/loongarch_extioi: Add irqchip-in-kernel save/restore function

On 2025/5/9 下午8:36, Jiaxun Yang wrote: 在2025年5月9日周五 上午11:07，Bibo Mao写道： Add save and store funtction if irqchip-in-kernel property is enabled, it is to get/set ExtIOI irqchip state from KVM kernel. Signed-off-by: Bibo Mao --- hw/intc/loongarch_extioi.c | 17 + hw/intc/loon

Re: [PATCH 14/15] target/loongarch: Report error with split kernel_irqchip option

On 2025/5/9 下午8:14, Jiaxun Yang wrote: 在2025年5月9日周五 上午11:12，Bibo Mao写道： Option kernel_irqchip=split is not supported on LoongArch virt machine, report error and exit if detect split kernel_irqchip option. Signed-off-by: Bibo Mao --- target/loongarch/kvm/kvm.c | 7 ++- 1 file change

Re: [PATCH 0/6] Add bios-tables-test for LoongArch64 system

On 2025/4/1 下午9:50, Igor Mammedov wrote: On Fri, 28 Feb 2025 17:27:23 +0800 Bibo Mao wrote: This patchset add bios-tables-test for LoongArch64 virt machine system. It works with UEFI bios, with uefi-test-tools LoongArch64 support is added to build bios-tables-test.loongarch64.iso. Also wit

Re: [PATCH 3/6] tests/qtest/bios-tables-test: Add basic testing for LoongArch64

On 2025/4/1 下午9:41, Igor Mammedov wrote: On Fri, 28 Feb 2025 17:27:26 +0800 Bibo Mao wrote: Add basic ACPI table test case for LoongArch64. Signed-off-by: Bibo Mao --- tests/qtest/bios-tables-test.c | 62 ++ 1 file changed, 62 insertions(+) diff --git a

Re: [PATCH v2 4/4] target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed

On Wed, Apr 9, 2025 at 12:52 PM Jim Shu wrote: > > Updating STCE will enable/disable SSTC in S-mode or/and VS-mode, so we > also need to update S/VS-mode Timer and S/VSTIP bits in $mip CSR. > > Signed-off-by: Jim Shu Acked-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 44

RE: [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 A1

Hi Cédric > Subject: Re: [PULL 45/46] tests/functional/aspeed: Add test case for AST2700 > A1 > > On 5/16/25 04:59, Jamin Lin wrote: > > Hi Cédric > > > >> > >> On a BE host, if I run an ast2700a0-evb machine : > >> > >> $ qemu-system-aarch64 -machine ast2700a0-evb ... > >> ... > >>

Re: [PATCH v2] target/riscv/kvm: add satp mode for host cpu

On Mon, Apr 28, 2025 at 6:57 PM Meng Zhuo wrote: > > This patch adds host satp mode while kvm/host cpu satp mode is not > set. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2931 > Signed-off-by: Meng Zhuo Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c

RE: [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller

Hi Philippe, > Subject: Re: [PULL 34/46] hw/intc/aspeed: Add Support for AST2700 INTCIO > Controller > > On 9/3/25 14:51, Cédric Le Goater wrote: > > From: Jamin Lin > > > > Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. > > Added new register definitions for INTCIO, including

Re: [PATCH 0/6] Add bios-tables-test for LoongArch64 system

On 2025/5/11 下午9:17, Michael S. Tsirkin wrote: On Fri, Feb 28, 2025 at 05:27:23PM +0800, Bibo Mao wrote: This patchset add bios-tables-test for LoongArch64 virt machine system. It works with UEFI bios, with uefi-test-tools LoongArch64 support is added to build bios-tables-test.loongarch64.iso

Re: [PATCH v2 2/4] hw/intc: riscv_aclint: Fix mtime write for sstc extension

On Wed, Apr 9, 2025 at 12:52 PM Jim Shu wrote: > > When changing the mtime value, the period of [s|vs]timecmp timers > should also be updated, similar to the period of mtimecmp timer. > > The period of the stimecmp timer is the time until the next S-mode > timer IRQ. The value is calculated as "st

Re: [PATCH v2] migration: Fix migration failure when aia is configured as 'aplic-imsic'

On Tue, May 13, 2025 at 2:33 AM wrote: > > From: Xuemei Liu > > Address an error in migration when aia is configured as 'aplic-imsic' in > riscv kvm vm by adding riscv_aplic_state_needed() and > riscv_imsic_state_needed() to determine whether the corresponding sates are > needed. > > Previously,

Re: [PATCH 0/2] hw/riscv/virt.c: change default CPU to 'max'

On Tue, May 6, 2025 at 8:47 AM Daniel Henrique Barboza wrote: > > Hi Alistair, > > > I think we should push this upstream and see what happens. We'll have a > full release cycle to undo the change in case we find unintended side > effects. I'm fairly optimistic that this change will be a no-op for

Re: [PATCH 2/2] target/riscv: Add standard B extension implied rule

On Wed, May 14, 2025 at 2:12 PM wrote: > > From: Frank Chang > > Add the missing implied rule for standard B extension. > Standard B extension implies Zba, Zbb, Zbs extensions. > > RISC-V B spec: https://github.com/riscv/riscv-b > > Signed-off-by: Frank Chang > Reviewed-by: Jerry Zhang Jian > R

Re: [PATCH 09/12] target/riscv: Fill in TCGCPUOps.pointer_wrap

On Mon, May 5, 2025 at 6:59 AM Richard Henderson wrote: > > Check 32 vs 64-bit and pointer masking state. > > Cc: qemu-ri...@nongnu.org > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > target/riscv/tcg/tcg-cpu.c | 26 ++ > 1 file changed,

[PATCH] vfio/igd: Respect x-igd-opregion=off in IGD quirk handling

> > Restore SR-IOV Intel iGPU VF passthrough capability: > > Check x-igd-opregion=off parameter in vfio_pci_igd_config_quirk and > > vfio_pci_kvmgt_config_quirk to ensure x-igd-opregion=off is > > respected despite subsequent attempt of automatic > > IGD opregion detection. > > > > Fixes: 7be29f2f1

Re: [PATCH] vfio/igd: Respect x-igd-opregion=off in IGD quirk handling

On Sun, 18 May 2025 22:09:33 + "edmund.raile" wrote: > Restore SR-IOV Intel iGPU VF passthrough capability: > Check x-igd-opregion=off parameter in vfio_pci_igd_config_quirk and > vfio_pci_kvmgt_config_quirk to ensure x-igd-opregion=off is > respected despite subsequent attempt of automatic >

[PATCH] vfio/igd: Respect x-igd-opregion=off in IGD quirk handling

Restore SR-IOV Intel iGPU VF passthrough capability: Check x-igd-opregion=off parameter in vfio_pci_igd_config_quirk and vfio_pci_kvmgt_config_quirk to ensure x-igd-opregion=off is respected despite subsequent attempt of automatic IGD opregion detection. Fixes: 7be29f2f1a3f ("Merge tag 'pull-vfio-

[PATCH] roms: re-remove execute bit from hppa-firmware*

This was fixed in c9d77526bddba0803a1fa982fb59ec98057150f9 for 9.2.0 but regressed in db34be329162cf6b06192703065e6c1010dbe3c5 in 10.0.0 When the bit is present, rpmbuild complains about missing ELF build-id Signed-off-by: Cole Robinson --- pc-bios/hppa-firmware.img | Bin pc-bios/hppa-firmwa

Re: [PATCH 02/27] vfio/container: pass MemoryRegion to DMA operations

On Fri, May 16, 2025 at 05:11:27PM +0200, Cédric Le Goater wrote: > > @@ -121,7 +121,7 @@ struct VFIOIOMMUClass { > > void (*listener_commit)(VFIOContainerBase *bcontainer); > > We forgot to document the listener_commit() and listener_begin() handlers. Apologies, I will send a separate pat

Re: [PATCH v2] virtio-gpu: support context init multiple timeline

On 5/18/25 18:26, Yiwei Zhang wrote: > Venus and later native contexts have their own fence context along with > multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in > the flags must be dispatched to be created on the target context. Fence > signaling also has to be handled on th

[PATCH v2] virtio-gpu: support context init multiple timeline

Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to be handled on the specific timeline within that target contex

Re: [PATCH] virtio-gpu: support context init multiple timeline

On Sat, 17 May 2025, Yiwei Zhang wrote: Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to be handled on the s

[PATCH] virtio-gpu: support context init multiple timeline

Venus and later native contexts have their own fence context along with multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in the flags must be dispatched to be created on the target context. Fence signaling also has to be handled on the specific timeline within that target contex

Re: [PATCH v4] tests/functional: Add PCI hotplug test for aarch64

Hi Phil, On 5/16/25 15:47, Philippe Mathieu-Daudé wrote: On 12/5/25 16:45, Gustavo Romero wrote: Add a functional test, aarch64_hotplug_pci, to exercise PCI hotplug and hot-unplug on arm64. Signed-off-by: Gustavo Romero Reviewed-by: Daniel P. Berrangé ---   MAINTAINERS