Re: [PATCH 5/9] target/riscv: Add mips.ccmov instruction

On 4/25/25 05:01, Djordje Todorovic wrote: +# Fields +%rs3 27:5 +%rs2 20:5 +%rs1 15:5 +%rd7:5 + +# Argument sets + +# Formats +@r4 . .. . . ... . ... %rs3 %rs2 %rs1 %rd + +# *** RV64 MIPS Extension *** +ccmov .11 . . 011 .

Re: [PATCH v2] hw/loongarch/virt: Get physical entry address with elf file

On 4/24/25 19:16, Bibo Mao wrote: With load_elf() api, image load low address and high address is converted to physical address if parameter translate_fn is provided. However executing entry address is still virtual address. Here convert entry address into physical address, since MMU is disabled

[PULL 22/58] target/arm: Handle gdb_core_xml_file in TYPE_ARM_CPU

From: Peter Maydell Instead of having the TYPE_AARCH64_CPU subclass set CPUClass:gdb_core_xml_file to a different value from that that TYPE_ARM_CPU uses, implement the gdb_get_core_xml_file method in the TYPE_ARM_CPU class to return either the AArch64 or AArch32 XML file name. Signed-off-by: Pet

Re: [PATCH v3 8/9] target/riscv: widen scounteren to target_ulong

On Fri, Apr 25, 2025 at 01:02:02PM -0300, Daniel Henrique Barboza wrote: > We want to support scounteren as a KVM CSR. The KVM UAPI defines every > CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. > > The other existing cases where the property size does not match the KVM > r

[PULL 1/4] file-posix: probe discard alignment on Linux block devices

From: Stefan Hajnoczi Populate the pdiscard_alignment block limit so the block layer is able align discard requests correctly. Signed-off-by: Stefan Hajnoczi Message-ID: <20250417150528.76470-2-stefa...@redhat.com> Reviewed-by: Kevin Wolf Signed-off-by: Kevin Wolf --- block/file-posix.c | 67

[PULL 3/4] block: Remove unused callback function *bdrv_aio_pdiscard

From: Sunny Zhu The bytes type in *bdrv_aio_pdiscard should be int64_t rather than int. There are no drivers implementing the *bdrv_aio_pdiscard() callback, it appears to be an unused function. Therefore, we'll simply remove it instead of fixing it. Additionally, coroutine-based callbacks are p

[PULL 2/4] block/io: skip head/tail requests on EINVAL

From: Stefan Hajnoczi When guests send misaligned discard requests, the block layer breaks them up into a misaligned head, an aligned main body, and a misaligned tail. The file-posix block driver on Linux returns -EINVAL on misaligned discard requests. This causes bdrv_co_pdiscard() to fail and

[PULL 0/4] Block layer patches

The following changes since commit 019fbfa4bcd2d3a835c241295e22ab2b5b56129b: Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into staging (2025-04-24 13:44:57 -0400) are available in the Git repository at: https://repo.or.cz/qemu/kevin.git tags/for-upstream for you to fe

[PULL 4/4] qemu-img: improve queue depth validation in img_bench

From: Denis Rastyogin This error was discovered by fuzzing qemu-img. Currently, running `qemu-img bench -d 0` in img_bench is allowed, which is a pointless operation and causes qemu-img to hang. Signed-off-by: Denis Rastyogin Message-ID: <20250327162423.25154-5-ger...@altlinux.org> Reviewed-by

Re: [PATCH] target/i386/hvf: Include missing 'exec/target_page.h' header

On 4/25/25 10:43, Philippe Mathieu-Daudé wrote: Include "exec/target_page.h" to be able to compile HVF on x86_64: ../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier 'TARGET_PAGE_SIZE' uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u);

[PATCH] target/i386/hvf: Include missing 'exec/target_page.h' header

Include "exec/target_page.h" to be able to compile HVF on x86_64: ../target/i386/hvf/hvf.c:139:49: error: use of undeclared identifier 'TARGET_PAGE_SIZE' uint64_t dirty_page_start = gpa & ~(TARGET_PAGE_SIZE - 1u); ^ ../target/i386/

Re: [PATCH 06/21] hw/dma/zynq-devcfg: Simulate dummy PL reset

On Tue, Mar 18, 2025 at 02:07:57PM +0100, Corvin Köhne wrote: > From: YannickV > > Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT > should indicate that the reset is finished successfully. > > In order to add a MMIO-Device as part of the PL in the Zynq, the > reset logic must s

Re: [PATCH 066/147] include/exec: Move TLB_MMIO, TLB_DISCARD_WRITE to slow flags

On Tue, 22 Apr 2025 12:26:55 -0700 Richard Henderson wrote: > Recover two bits from the inline flags. Hi Richard, Early days but something (I'm fairly sure in this patch) is tripping up my favourite TCG corner case of running code out of MMIO memory (interleaved CXL memory). Only seeing it o

[PULL 05/58] target/i386: Register CPUClass:list_cpus

Register x86_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250324185837.46506-3-phi...@linaro.org> --- target/i3

[PATCH alternate 1/2] target/riscv: Update pc before csrw, csrrw

Signed-off-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index b9c7160468..a367fecf7e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc

[PATCH alternate 2/2] target/riscv: Fix write_misa vs aligned next_pc

Do not examine a random host return address, but examine the guest pc via env->pc. Fixes: f18637cd611 ("RISC-V: Add misa runtime write support") Signed-off-by: Richard Henderson --- target/riscv/csr.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c

[PATCH alternate 0/2] target/riscv: Fix write_misa vs aligned next_pc

This is an alternate, but less exact approach. It assumes that there will never be a 16 or 48-bit csr write instruction. This feels dirtier, but it's a fair assumption involves much less faff. r~ Richard Henderson (2): target/riscv: Update pc before csrw, csrrw target/riscv: Fix write_mis

Re: [PATCH 09/21] hw/misc: Add dummy ZYNQ DDR controller

On Tue, Mar 18, 2025 at 02:08:00PM +0100, Corvin Köhne wrote: > From: YannickV > > A dummy DDR controller for ZYNQ has been added. While all registers are > present, > not all are functional. Read and write access is validated, and the user mode > can be set. This provides a basic DDR controller

[PATCH v3 6/9] target/riscv/kvm: do not read unavailable CSRs

[1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6. This happens because the kernel does not know 'senvcfg', making it unable to boot because QEMU is reading/wriiting it without any checks. After converting the CSRs to do "automated" get/put reg procedures in the previous patc

Re: [PATCH 08/21] hw/dma/zynq-devcfg: Fix register memory

On Tue, Mar 18, 2025 at 02:07:59PM +0100, Corvin Köhne wrote: > From: YannickV > > Registers are always 32 bit aligned. R_MAX is not the maximum > register address, it is the maximum register number. The memory > size can be determined by 4 * R_MAX. > > Currently every register with an offset bi

Re: [PATCH 05/21] hw/dma/zynq: Notify devcfg on FPGA reset via SLCR control

On Tue, Mar 18, 2025 at 02:07:56PM +0100, Corvin Köhne wrote: > From: YannickV > > When the FPGA_RST_CTRL register in the SLCR (System Level Control > Register) is written to, the devcfg (Device Configuration) should > indicate the finished reset. > > Problems occure when Loaders trigger a reset

[PULL 25/58] target/arm: Replace target_ulong -> vaddr for CPUWatchpoint

CPUWatchpoint::vaddr/len are of type vaddr. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20250415172246.79470-4-phi...@linaro.org> --- target/arm/internals.h | 9 + target/arm/hyp_gdbstub.c | 8 2 files chang

Re: [PATCH 4/4] qemu-img: improve queue depth validation in img_bench

Am 27.03.2025 um 17:24 hat ger...@altlinux.org geschrieben: > From: Denis Rastyogin > > This error was discovered by fuzzing qemu-img. > > Currently, running `qemu-img bench -d 0` in img_bench is allowed, > which is a pointless operation and causes qemu-img to hang. > > Signed-off-by: Denis Ras

Re: [PATCH 3/4] qemu-img: prevent stack overflow in bench by using bottom half

Am 27.03.2025 um 17:24 hat ger...@altlinux.org geschrieben: > From: Denis Rastyogin > > This error was discovered by fuzzing qemu-img. > > Previously, new I/O requests were launched synchronously inside the > completion callback `bench_cb`, leading to deep recursion and stack > overflow. This pa

Re: [PATCH 2/4] qemu-img: fix offset calculation in bench

Am 27.03.2025 um 17:24 hat ger...@altlinux.org geschrieben: > From: Denis Rastyogin > > This error was discovered by fuzzing qemu-img. > > The current offset calculation leads to an EIO error > in block/block-backend.c: blk_check_byte_request(): > > if (offset > len || len - offset < bytes) {

[PATCH v3 1/9] target/riscv/kvm: minor fixes/tweaks

Remove an unused 'KVMScratchCPU' pointer argument in kvm_riscv_check_sbi_dbcn_support(). Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will make a future patch diff easier to read, when changes in kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made. Fixes: a

[PATCH v3 8/9] target/riscv: widen scounteren to target_ulong

We want to support scounteren as a KVM CSR. The KVM UAPI defines every CSR size as target_ulong, and our env->scounteren is fixed at 32 bits. The other existing cases where the property size does not match the KVM reg size happens with uint64_t properties, like 'mstatus'. When running a 32 bit CPU

[PATCH v3 2/9] target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()

'reglist' is being g-malloc'ed but never freed. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c

[PATCH v3 5/9] target/riscv/kvm: add kvm_csr_cfgs[]

At this moment we're not checking if the host has support for any specific CSR before doing get/put regs. This will cause problems if the host KVM doesn't support it (see [1] as an example). We'll use the same approach done with the CPU extensions: read all known KVM CSRs during init() to check fo

[PATCH v3 7/9] target/riscv/kvm: add senvcfg CSR

We're missing the senvcfg CSRs which is already present in the KVM UAPI. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm

[PATCH v3 9/9] target/riscv/kvm: add scounteren CSR

Now that CPURISCVState::scounteren is a target_ulong, add support for the scounteren KVM CSR. Reported-by: Andrew Jones Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/kvm/kvm-cpu

[PATCH v3 0/9] target/riscv/kvm: CSR related fixes

Hi, In this version, aside from minor adjustments suggested by Drew in v2, the most relevant change made is left mcounteren untouched in patch 8. We're just changing scounteren to target_ulong as required by KVM. Patches based on alistair/riscv-to-apply.next with a KVM build fix [1]. Patches mi

[PATCH v3 4/9] target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro

We need the reg_id_ulong() helper to be a macro to be able to create a static array of KVMCPUConfig that will hold CSR information. Despite the amount of changes all of them are tedious/trivial: - replace instances of "kvm_riscv_reg_id_ulong" with "KVM_RISCV_REG_ID_ULONG"; - RISCV_CORE_REG(),

[PATCH v3 3/9] target/riscv/kvm: turn u32/u64 reg functions into macros

This change is motivated by a future change w.r.t CSRs management. We want to handle them the same way as KVM extensions, i.e. a static array with KVMCPUConfig objs that will be read/write during init and so on. But to do that properly we must be able to declare a static array that hold KVM regs.

[PULL 35/58] system/datadir: Add new type constant for DTB files

From: BALATON Zoltan Currently DTB files are mixed with ROMs under BIOS type. Separate them under a new type constant and turn defines into an enum while at it. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: Signed-off-by: Philippe Mathieu-Daudé --- include/q

Re: [PATCH 0/8] misc: Prefer evaluating TARGET_BIG_ENDIAN in C

On 17/4/25 15:09, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (8): linux-user/elfload: Use target_needs_bswap() accel/kvm: Use target_needs_bswap() target/mips: Check CPU endianness at runtime using env_is_bigendian() target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile t

[PULL 54/58] accel: Implement accel_init_ops_interfaces() for both system/user mode

We want to build more common code, moving objects from meson's specific_ss[] set to common_ss[]. Since the CONFIG_USER_ONLY definitions isn't applied on the common_ss[] set, it is simpler to add an empty accel_init_ops_interfaces() stub on user emulation, removing any CONFIG_USER_ONLY use in accel-

Re: [PATCH 04/21] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization

On Tue, Mar 18, 2025 at 02:07:55PM +0100, Corvin Köhne wrote: > From: YannickV > > During the emulation startup, all registers are reset, which triggers the > `r_unlock_post_write` function with a value of 0. This led to an > unintended memory access disable, making the devcfg unusable. > > To a

Re: [PATCH 1/3] aio-posix: treat io_uring setup failure as fatal

Am 01.04.2025 um 16:27 hat Stefan Hajnoczi geschrieben: > In the early days of io_uring it was possible for io_uring_setup(2) to > fail due to exhausting RLIMIT_MEMLOCK. QEMU's solution was to fall back > to epoll(7) or ppoll(2) when io_uring could not be used in an > AioContext. > > Nowadays io_u

Re: [PATCH 03/21] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff

On Tue, Mar 18, 2025 at 02:07:54PM +0100, Corvin Köhne wrote: > From: YannickV > > A DMA transfer to destination address `0x` should trigger a > bitstream load via the PCAP interface. Currently, this case is not > intercepted, causing loaders to enter an infinite loop when polling > the s

[PULL 02/58] target/hexagon: Replace MO_TE -> MO_LE

We only build the Hexagon target using little endianness order. The MO_TE definition always expands to MO_LE. Use the latter to simplify. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20250312103238.99981-3-phi...@linaro.org> --- target/hexagon/macros.h

[PULL 01/58] target/hexagon: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace it in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/hexagon); \ done Signed-off-by: Philippe Mathieu-Daudé Revie

Re: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper to get Host's vendor

Hi Zhao, On 4/25/25 1:28 AM, Zhao Liu wrote: > On Wed, Apr 16, 2025 at 02:52:26PM -0700, Dongli Zhang wrote: >> Date: Wed, 16 Apr 2025 14:52:26 -0700 >> From: Dongli Zhang >> Subject: [PATCH v4 01/11] [DO NOT MERGE] i386/cpu: Consolidate the helper >> to get Host's vendor >> X-Mailer: git-send-e

[PULL 33/58] system/vl: Fix type conflict of GLib function pointers

From: Kohei Tokunaga On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_l

[PULL 29/58] hw/intc/i8259: Remove unused DEBUG_PIC define

From: BALATON Zoltan The debug printfs were converted to traces so this define is now unused. Fixes: 0880a87300 (i8259: convert DPRINTFs into trace) Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Message-ID: <20250423101125.b243a55c...@zero.eik

[PULL 26/58] target/mips: Fix MIPS16e translation

From: Hauke Mehrtens Fix a wrong conversion to gen_op_addr_addi(). The framesize should be added like it was done before. This bug broke booting OpenWrt MIPS32 BE malta Linux system images generated by OpenWrt. Cc: qemu-sta...@nongnu.org Fixes: d0b24b7f50e1 ("target/mips: Use gen_op_addr_addi()

[PULL 21/58] target/arm: Handle AArch64 in TYPE_ARM_CPU gdb_arch_name

From: Peter Maydell Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_arch_name to a different function, make the TYPE_ARM_CPU implementation of the method handle AArch64. For the moment we make the "is this AArch64?" function test "is the CPU of TYPE_AARCH64_CPU?", so that this

Re: [RFC PATCH 0/3] single-binary: make QAPI generated files common

Pierrick Bouvier writes: > Note: This RFC was posted to trigger a discussion around this topic, and it's > not expected to merge it as it is. > > Context > === > > Linaro is working towards heterogeneous emulation, mixing several > architectures > in a single QEMU process. The first prerequi

[PULL 53/58] cpus: Move target-agnostic methods out of cpu-target.c

Various methods of cpu-target.c don't use any target-specific knowledge at all and can be built once in the target-agnostic cpu-common.c file. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250417165430.58213-4-phi...@linaro.org> --- cpu-target.c | 77

[PULL 28/58] hw/usb/hcd-xhci: Unmap canceled packet

From: Akihiko Odaki When the Stop Endpoint Command is received, packets running asynchronously are canceled and then all packets are cleaned up. Packets running asynchronously hold the DMA mapping so cleaning the packets leak the mapping. Remove the mapping after canceling packets to fix the leak

[PULL 47/58] target/xtensa: Evaluate TARGET_BIG_ENDIAN at compile time

Rather than evaluating TARGET_BIG_ENDIAN at preprocessing time via #ifdef'ry, do it in C at compile time Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250417131004.47205-6-phi...@linaro.org> --- target/xtensa/translate.c | 10 +- 1 file changed, 5 i

[PULL 34/58] system/memory: Remove DEVICE_HOST_ENDIAN definition

Since the previous commit ("exec/memory.h: make devend_memop "target defines" agnostic") there is a single use of the DEVICE_HOST_ENDIAN definition in ram_device_mem_ops: inline it and remove its definition altogether. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Reviewed

[PULL 36/58] pc-bios: Move device tree files in their own subdir

From: BALATON Zoltan We have several device tree files already and may have more in the future so add a new dtb subdirectory and move device tree files there so they are not mixed with ROM binaries. Signed-off-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Message-ID: <57f179bd3904c1f

[PATCH 1/7] target/riscv: Pass ra to riscv_csr_write_fn

Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 3 +- target/riscv/csr.c | 226 +++-- 2 files changed, 118 insertions(+), 111 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 167909c89b..4d41a66d72 100644 --- a/target/ris

[PULL 55/58] accel: Include missing 'qemu/accel.h' header in accel-internal.h

The "qemu/accel.h" header is implicitly pulled in. Include it explicitly in order to avoid when refactoring unrelated headers: accel/accel-internal.h:13:32: error: unknown type name 'AccelClass' 13 | void accel_init_ops_interfaces(AccelClass *ac); |^

[PULL 51/58] qemu: Introduce target_cpu_type()

Introduce the target_cpu_type() helper to access the CPU_RESOLVING_TYPE target-specific definition from target-agnostic code. Reviewed-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250417165430.58213-2-phi...@linaro.org> --- MAINTAINERS| 2 ++ meson.

[PULL 48/58] hw/mips: Evaluate TARGET_BIG_ENDIAN at compile time

Rather than evaluating TARGET_BIG_ENDIAN at preprocessing time via #ifdef'ry, do it in C at compile time Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250417131004.47205-7-phi...@linaro.org> --- hw/mips/jazz.c| 11 --- hw/mips/malta.c | 21 +++

[PULL 44/58] linux-user/elfload: Use target_needs_bswap()

Check whether we need to swap at runtime using target_needs_bswap(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250417131004.47205-2-phi...@linaro.org> --- linux-user/elfload.c | 63 +++- 1 file changed, 39 inserti

[PULL 14/58] qom: Constify TypeInfo::class_data

All callers now correctly expect a const class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250424194905.82506-5-phi...@linaro.org> --- include/qom/object.h| 2 +- hw/arm/armsse.c |

[PULL 45/58] accel/kvm: Use target_needs_bswap()

Check whether we need to swap at runtime using target_needs_bswap(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250417131004.47205-3-phi...@linaro.org> --- accel/kvm/kvm-all.c | 30 -- 1 file changed, 16 insertions(+), 14 dele

[PULL 56/58] accel: Make AccelCPUClass structure target-agnostic

Move the target-agnostic parts of "accel/accel-cpu-target.h" to "accel/accel-cpu.h". Doing so we need to include missing "hw/core/cpu.h" header in "accel/accel-cpu.h" otherwise we get: include/accel/accel-cpu-target.h:39:28: error: unknown type name 'CPUClass' 39 | void (*cpu_class_ini

[PULL 42/58] accel/tcg: Correct list of included headers in tcg-stub.c

In commit 3549118b498 we moved cpu_loop_exit*() declarations to "exec/cpu-common.h" but neglected to update tcg-stub.c. We missed it because "exec/cpu-common.h" is indirectly pulled in via "exec/exec-all.h" -> "exec/translation-block.h". Include it directly instead of the not necessary "exec/exec-a

[PULL 24/58] target/arm: Replace target_ulong -> hwaddr in ARMMMUFaultInfo

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Henderson Message-Id: <20250415172246.79470-2-phi...@linaro.org> --- target/arm/internals.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/inter

Re: [PATCH] block： change type of bytes from int to int64_t for *bdrv_aio_pdiscard

Am 24.04.2025 um 19:40 hat Eric Blake geschrieben: > On Tue, Apr 22, 2025 at 09:11:51AM +0200, Philippe Mathieu-Daudé wrote: > > Hi Eric, > > > > On 21/4/25 17:03, Eric Blake wrote: > > > On Mon, Apr 21, 2025 at 12:19:14AM +0800, Sunny Zhu wrote: > > > > Keep it consistent with *bdrv_co_pdiscard.

[PULL 57/58] accel: Move target-agnostic code from accel-target.c -> accel-common.c

Various methods of accel-target.c don't use any target-specific knowledge at all and can be built once in the target-agnostic accel-common.c file. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-Id: <20250417165430.58213-8-phi...@linaro.org> --- accel/accel-common.c

[PULL 52/58] cpus: Replace CPU_RESOLVING_TYPE -> target_cpu_type()

Replace the target-specific CPU_RESOLVING_TYPE definition by a call to the target-agnostic target_cpu_type() runtime helper. Since the big "cpu.h" is not required anymore in tcg-all.c, remove it, using the tinier "cpu-param.h" header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick B

[PULL 39/58] meson: Share common C source prefixes

From: Akihiko Odaki gnu_source_prefix defines _GNU_SOURCE for compiler object functions. The definition is universally available in the code base. docs/devel/style.rst also says that the "qemu/osdep.h" header is always included, so files included in the file is also universally available in the

[PULL 12/58] qom: Have class_base_init() take a const data argument

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250424194905.82506-3-phi...@linaro.org> --- include/qom/object.h | 2 +- hw/core/machine.c| 2 +- hw/core/qdev.c | 2 +- hw/pci/pci.c | 2 +- qom/object.c | 2 +- rus

[PULL 58/58] qemu: Convert target_name() to TargetInfo API

Have target_name() be a target-agnostic method, dispatching to a per-target TargetInfo singleton structure. By default a stub singleton is used. No logical change expected. Inspired-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Reviewed-by: Richard Hen

[PULL 50/58] qapi: Rename TargetInfo structure as QemuTargetInfo

The QAPI-generated 'TargetInfo' structure name is only used in a single file. We want to heavily use another structure similarly named. Rename the QAPI one, since structure names are not part of the public API. Suggested-by: Pierrick Bouvier Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pie

[PULL 32/58] contrib/plugins: Fix type conflict of GLib function pointers

From: Kohei Tokunaga On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_l

[PULL 16/58] qom: Make InterfaceInfo[] uses const

Mechanical change using: $ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)') Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250424194905.82506-7-phi...@linaro.org> --- include/qom/object.

[PULL 49/58] hw/microblaze: Evaluate TARGET_BIG_ENDIAN at compile time

Rather than evaluating TARGET_BIG_ENDIAN at preprocessing time via #ifdef'ry, do it in C at compile time Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250417131004.47205-8-phi...@linaro.org> --- hw/microblaze/petalogix_ml605_mmu.c | 12 ++-- hw/micr

[PULL 30/58] hw/core/loader: Fix type conflict of GLib function pointers

From: Kohei Tokunaga On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_l

[PULL 46/58] target/mips: Check CPU endianness at runtime using env_is_bigendian()

Since CPU endianness can be toggled at runtime before resetting, checking the endianness at build time preprocessing the TARGET_BIG_ENDIAN definition isn't correct. We have to call mips_env_is_bigendian() to get the CPU endianness at runtime. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Ric

[PULL 31/58] hw/net/can: Fix type conflict of GLib function pointers

From: Kohei Tokunaga On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_l

[PULL 43/58] target/hexagon: Include missing 'accel/tcg/getpc.h'

Since the macros.h headers call GETPC(), they need to include "accel/tcg/getpc.h", which defines it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland Reviewed-by: Brian Cain Message-Id: <20250424094653.35932-9-phi...@linaro.org> --- target/hexagon/macros.h | 1 + targe

[PATCH 5/7] target/riscv: Pass ra to riscv_csrrw_i128

Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 4 ++-- target/riscv/csr.c | 8 target/riscv/op_helper.c | 9 + 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2c0524d0be..8b84793b15 100644 --- a

[PULL 37/58] meson: Use has_header_symbol() to check getcpu()

From: Akihiko Odaki The use of gnu_source_prefix in the detection of getcpu() was ineffective because the header file that declares getcpu() when _GNU_SOURCE is defined was not included. Pass sched.h to has_header_symbol() so that the existence of the declaration will be properly checked. Cc: qe

[PULL 38/58] meson: Remove CONFIG_STATX and CONFIG_STATX_MNT_ID

From: Akihiko Odaki CONFIG_STATX and CONFIG_STATX_MNT_ID are not used since commit e0dc2631ec4 ("virtiofsd: Remove source"). Cc: qemu-sta...@nongnu.org Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Message-ID: <20250424-buildsys-v1-2-97655e

[PULL 40/58] meson: Use osdep_prefix for strchrnul()

From: Akihiko Odaki macOS SDK may have the symbol of strchrnul(), but it is actually available only on macOS 15.4 or later and that fact is codified in string.h. Include the header file using osdep_prefix to check if the function is available on the deployment target. Cc: qemu-sta...@nongnu.org

[PULL 23/58] target/arm: Handle AArch64 gdb read/write regs in TYPE_ARM_CPU

From: Peter Maydell Instead of having the TYPE_AARCH64_CPU subclass set CPUClass::gdb_read_register and ::gdb_write_register to different methods from those of the TYPE_ARM_CPU parent class, have the TYPE_ARM_CPU methods handle either AArch32 or AArch64 at runtime. Signed-off-by: Peter Maydell

[PULL 41/58] system/kvm: make functions accessible from common code

From: Pierrick Bouvier Signed-off-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20250424232829.141163-8-pierrick.bouv...@linaro.org> Signed-off-by: Philippe Mathieu-Daudé --- include/system/kvm.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[PULL 11/58] hw/misc/edu: Convert type_init() -> DEFINE_TYPES()

Prefer DEFINE_TYPES() macro over type_init() to register QOM types. Initialize the .interfaces struct field as compound literal casted to InterfaceInfo type like the rest of our code base. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20250424194905.82506-2-p

[PULL 18/58] hw/core: Get default_cpu_type calling machine_class_default_cpu_type()

Since commit 62b4a227a33 the default cpu type can come from the valid_cpu_types[] array. Call the machine_class_default_cpu_type() instead of accessing MachineClass::default_cpu_type field. Cc: qemu-sta...@nongnu.org Fixes: 62b4a227a33 ("hw/core: Add machine_class_default_cpu_type()") Signed-off-b

[PULL 20/58] gdbstub: Allow gdb_core_xml_file to be set at runtime

From: Peter Maydell Currently the CPUClass:gdb_core_xml_file setting is a simple 'const char *' which the CPU class must set to a fixed string. Allow the CPU class to instead set a new method gdb_get_core_xml_file() which returns this string. This will allow Arm CPUs to use different XML files

[PULL 19/58] hw/core/cpu: gdb_arch_name string should not be freed

From: Peter Maydell The documentation for the CPUClass::gdb_arch_name method claims that the returned string should be freed with g_free(). This is not correct: in commit a650683871ba728 we changed this method to instead return a simple constant string, but forgot to update the documentation. M

[PULL 03/58] target/i386: Replace MO_TE* -> MO_LE*

The x86 architecture is only implemented as little-endian. The MO_TE definition always expands to MO_LE. Replace: - MO_TEUQ -> MO_LEUQ - MO_TE -> MO_LE Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250312142124.15138-1-phi...@linaro.org> --- target/i38

[PULL 27/58] exec: Rename target_words_bigendian() -> target_big_endian()

In commit 98ed8ecfc9d ("exec: introduce target_words_bigendian() helper") target_words_bigendian() was matching the definition it was depending on (TARGET_WORDS_BIGENDIAN). Later in commit ee3eb3a7ce7 ("Replace TARGET_WORDS_BIGENDIAN") the definition was renamed as TARGET_BIG_ENDIAN but we didn't u

[PULL 08/58] target/s390x: Register CPUClass:list_cpus

Both s390_cpu_list() and s390_set_qemu_cpu_model() are defined in cpu_models.c, move their declarations in the related "cpu_models.h" header. Use full path to header in s390-virtio-ccw.c file. Register s390_cpu_list() as CPUClass:list_cpus callback and remove the cpu_list definition. Reviewed-by:

[PULL 04/58] cpus: Introduce CPUClass::list_cpus() callback

Some targets define cpu_list to a method listing their CPUs on stdout. In order to make list_cpus() generic, introduce the CPUClass::list_cpus() callback. When no callback is registered, list_cpus() defaults to the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Hut

[PULL 06/58] target/ppc: Register CPUClass:list_cpus

Register ppc_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250324185837.46506-4-phi...@linaro.org> --- target/pp

[PULL 17/58] qom/object: Fix type conflict of GLib function pointers

From: Kohei Tokunaga On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_l

[PULL 15/58] qom: Constify TypeInfo::interfaces

Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20250424194905.82506-6-phi...@linaro.org> --- include/hw/virtio/virtio-pci.h | 2 +- include/qom/object.h | 2 +- hw/scsi/megasas.c | 2 +- rust/qemu-api/src/qom.rs | 2 +- 4 files chan

[PULL 07/58] target/sparc: Register CPUClass:list_cpus

Register sparc_cpu_list() as CPUClass:list_cpus callback. Reduce its scope and remove the cpu_list definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250324185837.46506-5-phi...@linaro.org> --- target/

[PULL 09/58] cpus: Remove #ifdef check on cpu_list definition

Since we removed all definitions of cpu_list, the #ifdef check is always true. Remove it, inlining cpu_list(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Zhao Liu Message-Id: <20250324185837.46506-7-phi...@linaro.org> --- cpu-tar

[PULL 10/58] hw/pci-host/designware: Use deposit/extract API

Prefer the safer (less bug-prone) deposit/extract API to access lower/upper 32-bit of 64-bit registers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gustavo Romero Message-Id: <20250331152041.74533-3-phi...@linaro.org> --- hw/pci-host/designware.c | 48 ++--

[PULL 00/58] Misc single binary patches for 2025-04-25

The following changes since commit 019fbfa4bcd2d3a835c241295e22ab2b5b56129b: Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into staging (2025-04-24 13:44:57 -0400) are available in the Git repository at: https://github.com/philmd/qemu.git tags/single-binar

[PATCH 4/7] target/riscv: Pass ra to riscv_csrrw

Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 8 hw/riscv/riscv_hart.c| 2 +- target/riscv/csr.c | 8 target/riscv/op_helper.c | 4 ++-- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4d4

[PATCH 6/7] target/riscv: Move insn_len to internals.h

Signed-off-by: Richard Henderson --- target/riscv/internals.h | 5 + target/riscv/translate.c | 5 - 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 213aff31d8..4570bd50be 100644 --- a/target/riscv/internals.h +++ b/

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