When PMU is enabled in QEMU, there is a chance that PMU virtualization is
completely disabled by the KVM module parameter kvm.enable_pmu=N.
The kvm.enable_pmu parameter is introduced since Linux v5.17.
Its permission is 0444. It does not change until a reload of the KVM
module.
Read the kvm.enabl
Fabiano Rosas writes:
> Markus Armbruster writes:
>
>> Fabiano Rosas writes:
>>
>>> Daniel P. Berrangé writes:
>>>
On Fri, Apr 11, 2025 at 04:14:35PM -0300, Fabiano Rosas wrote:
> Introduce a new MigrationConfigBase, to allow most of the duplication
> in migration.json to be elimi
> -Original Message-
> From: Brian Cain
> Sent: Friday, February 28, 2025 10:26 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsi
On Thu, 17 Apr 2025 01:41:22 +0800
Tomita Moeko wrote:
> On 4/17/25 00:10, Alex Williamson wrote:
> > On Wed, 16 Apr 2025 23:45:08 +0800
> > Tomita Moeko wrote:
> >
> >> On 4/16/25 03:04, Alex Williamson wrote:
> >>> On Wed, 16 Apr 2025 01:36:15 +0800
> >>> Tomita Moeko wrote:
>
>
On 4/16/25 2:50 PM, Michael S. Tsirkin wrote:
On Wed, Apr 16, 2025 at 09:29:23AM -0400, Alejandro Jimenez wrote:
On 4/16/25 7:36 AM, Sairaj Kodilkar wrote:
+static int amdvi_as_to_dte(AMDVIAddressSpace *as, uint64_t *dte);
+
No need to have this function declaration as it is a static
On 08/04/2025 17.55, Zhuoying Cai wrote:
Introduce Secure-IPL (SIPL) facility.
Use the abbreviation CBL (Consolidated-Boot-Loader facility at bit 0 of
byte 136) to represent bytes 136 and 137 for IPL device facilities of the
SCLP Read Info block.
Availability of SIPL facility is determined by b
On 08/04/2025 17.55, Zhuoying Cai wrote:
The secure-IPL-code-loading-attributes facility (SCLAF)
provides additional security during IPL.
Availability of SCLAF is determined by byte 136 bit 3 of the
SCLP Read Info block.
Signed-off-by: Zhuoying Cai
---
...
diff --git a/target/s390x/cpu_featu
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH 1/5] vfio/iommufd: Save host iommu capabilities in
>VFIODevice.caps
>
>On Wed, Apr 16, 2025 at 05:49:09AM +, Duan, Zhenzhong wrote:
>> >-Original Message-
>> >From: Nicolin Chen
>
>> > And I was expecting the
>> >
Function loongarch_tlb_search() and loongarch_map_tlb_entry() works
only in TCG mode, move these functions to directory tcg.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 153 --
target/loongarch/internals.h | 14 ++-
target/loongarch/tcg/tlb_h
Stub function loongarch_get_addr_from_tlb() is added if option
CONFIG_TCG is not enabled, so this function can be called in KVM
only mode.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu_helper.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/target/loongarch/cpu_helper.c b/target
Function get_dir_base_width() is used by loongarch_page_table_walker(),
so it is used by KVM mode also, here move this function from directory
tcg to common directory.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu_helper.c | 28
Function loongarch_map_address is to get physical address from virtual
address, it is used by qmp commands to dump memory from virtual
address.
It is used by kvm mode also, here move function loongarch_map_address()
out of macro CONFIG_TCG. And it is common code, the similar with
function loongarc
Header file helper.h is specified for tcg mode, move this file to
directory tcg. And create new file helper.h to include header
file in tcg mode.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/helper.h | 720 +
target/loonga
Function loongarch_get_addr_from_tlb() is added to get physical address
from TLB tables. TLB table only works in TCG mode, in future this
function will be moved to TCG directory.
Signed-off-by: Bibo Mao
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu_helper.c | 32 +
Get physical address from virtual address is important for qmp command to
dump memory content. In TCG mode, it searches TLB tables firstly and
then do page table walker. In KVM mode, there are no TLB tables and page
table walker is used directly.
Here TLB tables searching is moved to directory tcg
Move the declaration of "rom_size" to an outer scope in aspeed_machine_init()
so it can be reused for setting up the vbootrom region as well.
This avoids introducing a redundant local variable and ensures consistent
ROM sizing logic when both SPI boot and vbootrom are used.
Signed-off-by: Jamin L
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/tests/functional/test_aarch64_aspeed.py
b/tests/functional/test_aarch64_aspeed.py
index 441f7f3919..337d701917 100755
--- a/tests/functi
Move the I2C test case into a common helper function (do_ast2700_i2c_test) so it
can be reused across multiple AST2700-based test cases. This reduces duplication
and improves maintainability.
Signed-off-by: Jamin Lin
---
tests/functional/test_aarch64_aspeed.py | 28 +
1 f
The boot ROM is a minimal implementation designed to load an AST27x0 boot image.
Its source code is available at:
https://github.com/google/vbootrom
Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
---
MAINTAINERS | 1 +
pc-bios/README
Using the vbootrom image support and the boot ROM binary is
now passed via the -bios option, using the image located in
pc-bios/ast27x0_bootrom.bin.
Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
---
docs/system/arm/aspeed.rst | 29 -
1 file changed, 28 insertio
Add the AST2700 functional test to boot using the vbootrom image
instead of manually loading boot components with -device loader.
The boot ROM binary is now passed via the
-bios option, using the image located in pc-bios/ast27x0_bootrom.bin.
Signed-off-by: Jamin Lin
---
tests/functional/test_aar
Introduce a new vbootrom memory region. The region is mapped at address
"0x" and has a size of 128KB, identical to the SRAM region size.
This memory region is intended for loading a vbootrom image file as part of the
boot process.
The vbootrom registered in the SoC's address space using th
Introduce "aspeed_load_vbootrom()" to support loading a virtual boot ROM image
into the vbootrom memory region, using the "-bios" command-line option.
Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
---
include/hw/arm/aspeed.h | 1 +
hw/arm/aspeed.c | 36 +
v1:
Add initial support for AST27x0
The purpose of vbootrom here is to simulate the work of BootMCU SPL (riscv)
in AST2700, because QEMU doesn't support heterogenous architecture yet.
ast27x0_bootrom.bin is a simplified, free (Apache 2.0) boot ROM for
ASPEED AST27x0 BMC SOC. It currently
Introduce a new "vbootrom" field in the AspeedMachineClass to indicate whether
a machine supports the virtual boot ROM region.
Set this field to true by default for the AST2700-A0 and AST2700-A1 EVB
machines.
Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
Tested-by: Nabih Estefan
---
inc
From: Kane-Chen-AS
This introduces a new model for the ASPEED OTP (One-Time Programmable)
memory. The device is implemented as a `SysBusDevice` and provides an
abstracted interface for OTP read, write (program), and default value
initialization.
OTP content is backed by a block device and suppor
From: Kane-Chen-AS
This patch integrates the `aspeed.otpmem` device with the ASPEED
Secure Boot Controller (SBC). The SBC now accepts an OTP backend via
a QOM link property ("otpmem"), enabling internal access to OTP content
for controller-specific logic.
This connection provides the foundation
From: Kane-Chen-AS
Dear reviewers,
This patch series introduces a new model for the ASPEED OTP (One-Time
Programmable) memory and integrates it with the ASPEED Secure Boot
Controller (SBC) and SoC models such as AST1030 and AST2600.
The OTP memory is implemented as a QEMU device (`aspeed.otpmem
From: Kane-Chen-AS
This patch wires up the OTP memory device (`aspeed.otpmem`) into the
AST1030 and AST2600 SoC models. The device is initialized, attached
to a backing block drive (`-drive id=otpmem`) and linked to the SBC
controller via a QOM link.
The default OTP memory image can be generated
The initialization of 'has_architectural_pmu_version',
'num_architectural_pmu_gp_counters', and
'num_architectural_pmu_fixed_counters' is unrelated to the process of
building the CPUID.
Extract them out of kvm_x86_build_cpuid().
In addition, use cpuid_find_entry() instead of cpu_x86_cpuid(), beca
Hi Nabih,
> Subject: Re: [PATCH v3 06/10] pc-bios: Add AST27x0 vBootrom
>
> This patch probably needs to go before patch 5 so the automatic enabling of
> the vbootrom works. Besides that it looks good.
>
Thanks for suggestion and review.
Will update the patch order.
Jamin
> On Tue, Apr 15, 20
On Tue, Mar 18, 2025 at 03:56:24PM +, Jonathan Cameron wrote:
> On Mon, 17 Mar 2025 16:31:29 +
> anisa.su...@gmail.com wrote:
>
> > From: Anisa Su
> >
> > FM DCD Management command 0x5600 implemented per CXL 3.2 Spec Section
> > 7.6.7.6.1
> >
> > Signed-off-by: Anisa Su
> > ---
> > h
From: Nicholas Piggin
IPMI drivers use p/k suffix in variable names depending on bt or kcs.
The pci bt driver must have come from the kcs driver because it's
still using k suffixes in some cases. Rename.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Nicholas Piggin
Message-ID: <2025040114
From: Nicholas Piggin
Mask out unsupported bits and return failure if attempting to set
any. This is not required by the IPMI spec, but it does require that
system software not change bits it isn't aware of.
Signed-off-by: Nicholas Piggin
Message-ID: <20250401140153.685523-6-npig...@gmail.com>
Hi Richard,
On 4/15/25 12:22, Richard Henderson wrote:
v2: 20250107080112.1175095-1-richard.hender...@linaro.org
v3: 20250216231012.2808572-1-richard.hender...@linaro.org
Since it has been 2 months, I don't recall specific changes from v3 to v4.
It's mostly application of r-b tags. There is on
On 4/16/25 17:18, Richard Henderson wrote:
On 4/16/25 16:38, Pierrick Bouvier wrote:
The only concern I have is that we could create silent "performance" related
bugs, where a
specific feature is deactivated because of a bad combination, but it's inherent
to this
approach and not a blocker.
On 4/16/25 16:38, Pierrick Bouvier wrote:
The only concern I have is that we could create silent "performance" related bugs, where a
specific feature is deactivated because of a bad combination, but it's inherent to this
approach and not a blocker.
I think I know what you mean, and the way I s
It's the right way to do it now, and it handles multiple instances
properly. I need multiple instances for some testing I'm doing so this
is the right thing to do.
Tested by doing:
(qemu) migrate -d exec:cat>filen.mig
before and after the fix, then:
scripts/analyze-migration.py -d desc -
From: Nicholas Piggin
If the dont-log flag is set in the 'timer use' field for the
'set watchdog' command, a watchdog timeout will not get logged as
a timer use expiration.
Signed-off-by: Nicholas Piggin
Message-ID: <20250401140153.685523-5-npig...@gmail.com>
Signed-off-by: Corey Minyard
---
From: Nicholas Piggin
Linux issues this command when booting a powernv machine.
Signed-off-by: Nicholas Piggin
Message-ID: <20250401140153.685523-4-npig...@gmail.com>
Signed-off-by: Corey Minyard
---
hw/ipmi/ipmi_bmc_sim.c | 68 --
hw/ipmi/ipmi_bt.c
From: Nicholas Piggin
This requires some adjustments to callers to avoid possible behaviour
changes for PCI devices.
Signed-off-by: Nicholas Piggin
Message-ID: <20250401140153.685523-3-npig...@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé
[Rename pci_ipmi_bt_get_fwinfo to pci_ipmi_kcs_get_fwi
> -Original Message-
> From: Brian Cain
> Sent: Wednesday, April 16, 2025 4:22 PM
> To: ltaylorsimp...@gmail.com; 'Matheus Tavares Bernardino'
>
> Cc: qemu-devel@nongnu.org; richard.hender...@linaro.org;
> phi...@linaro.org; a...@rev.ng; a...@rev.ng;
> marco.lie...@oss.qualcomm.com; al
On 4/14/2025 3:59 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Matheus Tavares Bernardino
Sent: Monday, April 14, 2025 12:10 PM
To: ltaylorsimp...@gmail.com
Cc: brian.c...@oss.qualcomm.com; qemu-devel@nongnu.org;
richard.hender...@linaro.org; phi...@linaro.org;
matheu
Ping?
Any chance to accept this property? It is acked by Stefano Garzarella.
It helped me test vhost-scsi event queue and live migration recently.
https://lore.kernel.org/all/20250403063028.16045-9-dongli.zh...@oracle.com/
Thank you very much!
Dongli Zhang
On 2/11/25 8:26 AM, Stefano Garzarel
Currently, AMD PMU support isn't determined based on CPUID, that is, the
"-pmu" option does not fully disable KVM AMD PMU virtualization.
To minimize AMD PMU features, remove PERFCORE when "-pmu" is configured.
To completely disable AMD PMU virtualization will be implemented via
KVM_CAP_PMU_CAPAB
On 4/16/25 8:14 AM, Sairaj Kodilkar wrote:
+
+ /* DMA address translation support */
+ IOMMUNotifierFlag notifier_flags;
+ /* entry in list of Address spaces with registered notifiers */
+ QLIST_ENTRY(AMDVIAddressSpace) next;
+ /* DMA address translation active */
+ bool add
On 4/8/25 11:55 AM, Zhuoying Cai wrote:
> If secure boot in audit mode or True Secure IPL mode is enabled without
> specifying a boot device, the boot process will terminate with an error.
>
> Signed-off-by: Zhuoying Cai
> ---
> hw/s390x/ipl.c | 10 ++
> 1 file changed, 10 insertions(+)
> -Original Message-
> From: Brian Cain
> Sent: Wednesday, April 16, 2025 1:43 PM
> To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org;
> quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; alex.ben...@l
QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
and kvm_put_msrs() to restore them to KVM. However, there is no support for
AMD PMU registers. Currently, pmu_version and num_pmu_gp_counters are
initialized based on cpuid(0xa), which does not apply to AMD processors.
For A
Since perfmon-v2, the AMD PMU supports additional registers. This update
includes get/put functionality for these extra registers.
Similar to the implementation in KVM:
- MSR_CORE_PERF_GLOBAL_STATUS and MSR_AMD64_PERF_CNTR_GLOBAL_STATUS both
use env->msr_global_status.
- MSR_CORE_PERF_GLOBAL_CTRL
From: Xiaoyao Li
Introduce kvm_arch_pre_create_vcpu(), to perform arch-dependent
work prior to create any vcpu. This is for i386 TDX because it needs
call TDX_INIT_VM before creating any vcpu.
The specific implementation of i386 will be added in the future patch.
Signed-off-by: Xiaoyao Li
Acke
PMU MSRs are set by QEMU only at levels >= KVM_PUT_RESET_STATE,
excluding runtime. Therefore, updating these MSRs without stopping events
should be acceptable.
In addition, KVM creates kernel perf events with host mode excluded
(exclude_host = 1). While the events remain active, they don't increme
This patchset addresses four bugs related to AMD PMU virtualization.
1. The PerfMonV2 is still available if PERCORE if disabled via
"-cpu host,-perfctr-core".
2. The VM 'cpuid' command still returns PERFCORE although "-pmu" is
configured.
3. The third issue is that using "-cpu host,-pmu" does no
AMD does not have what is commonly referred to as an architectural PMU.
Therefore, we need to rename the following variables to be applicable for
both Intel and AMD:
- has_architectural_pmu_version
- num_architectural_pmu_gp_counters
- num_architectural_pmu_fixed_counters
For Intel processors, th
When the PERFCORE is disabled with "-cpu host,-perfctr-core", it is
reflected in in guest dmesg.
[0.285136] Performance Events: AMD PMU driver.
However, the guest CPUID indicates the PerfMonV2 is still available.
CPU:
Extended Performance Monitoring and Debugging (0x8022):
AMD p
From: Zhao Liu
Extend host_cpu_vendor_fms() to help more cases to get Host's vendor
information.
Cc: Dongli Zhang
Signed-off-by: Zhao Liu
---
This patch is already queued by Paolo.
https://lore.kernel.org/all/20250410075619.145792-1-zhao1@intel.com/
I don't need to add my Signed-off-by.
Although AMD PERFCORE and PerfMonV2 are removed when "-pmu" is configured,
there is no way to fully disable KVM AMD PMU virtualization. Neither
"-cpu host,-pmu" nor "-cpu EPYC" achieves this.
As a result, the following message still appears in the VM dmesg:
[0.263615] Performance Events: AMD
On Tue, Apr 15, 2025 at 06:59:15PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 11.04.25 04:04, Eric Blake wrote:
> > When mirroring, the goal is to ensure that the destination reads the
> > same as the source; this goal is met whether the destination is sparse
> > or fully-allocated. However,
On Fri, Apr 11, 2025 at 10:54:57PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 11.04.25 04:04, Eric Blake wrote:
> > When doing a sync=full mirroring, QMP drive-mirror requests full
> > zeroing if it did not just create the destination, and blockdev-mirror
> > requests full zeroing unconditiona
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index bfe63649db..392b51196a 100644
--- a/target/sparc/translate.c
On Mon, Mar 17, 2025 at 04:31:33PM +, anisa.su...@gmail.com wrote:
> From: Anisa Su
>
> FM DCD Management command 0x5602 implemented per CXL r3.2 Spec Section
> 7.6.7.6.3
>
> Signed-off-by: Anisa Su
> ---
> hw/cxl/cxl-mailbox-utils.c | 100 +++
> hw/mem/c
On 4/8/25 11:55 AM, Zhuoying Cai wrote:
> DIAG 320 subcode 2 provides certificates that are in the
> certificate store.
>
> The subcode value is denoted by setting the second-left-most bit
> of an 8-byte field.
>
> The verification-certificate-block (VCB) contains the output data
> when the opera
On 4/15/25 12:25, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 46 +++
tcg/aarch64/tcg-target.c.inc | 113 ---
tcg/arm/tcg-target.c.inc | 126 ---
tcg/i386/tcg-target
On 4/15/25 12:25, Richard Henderson wrote:
The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 4
tcg/aarch64/tcg-target-has.h | 1 -
tcg/arm/tcg-target-has.h | 1 -
tc
This patch probably needs to go before patch 5 so the automatic
enabling of the vbootrom works. Besides that it looks good.
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> The boot ROM is a minimal implementation designed to load an AST27x0 boot
> image.
> Its source code is available at:
>
On 4/15/25 12:25, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 -
tcg/aarch64/tcg-target.c.inc | 45 ---
tcg/arm/tcg-target.c.inc | 61 -
tcg/i386/tcg-target.c.inc| 71
On 4/15/25 12:25, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 32 +++-
tcg/aarch64/tcg-target.c.inc | 30 +--
tcg/arm/tcg-target.c.inc | 63 +++-
tcg/i386/tcg-target.c.inc
On 4/15/25 12:25, Richard Henderson wrote:
Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two
inputs or outputs are required. This simplifies the processing of
i64/i128 depending on host word size.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 16 ++---
On 4/15/25 12:25, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 37 ++
tcg/aarch64/tcg-target.c.inc | 52 +++---
tcg/arm/tcg-target.c.inc | 72 +--
tcg/i386/tcg-target.c.inc| 114 ++
On 4/15/25 12:25, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 15 --
tcg/optimize.c | 28 +++--
tcg/tcg-op.c | 14 ++---
tcg/tcg.c| 45 +
On 4/15/25 12:25, Richard Henderson wrote:
This will enable removing INDEX_op_qemu_st8_*_i32,
by exposing the operand size to constraint selection.
Signed-off-by: Richard Henderson
---
tcg/tcg-op-ldst.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg-op-ld
On 4/15/25 12:25, Richard Henderson wrote:
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 19 +---
tcg/optimize.c | 27 -
tcg/tcg-op.c | 24 +++
tcg/tcg.c| 64
On 4/15/25 12:25, Richard Henderson wrote:
Split these functions out from tcg_out_op.
Define outop_goto_ptr generically.
Call tcg_out_goto_ptr from tcg_reg_alloc_op.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12
tcg/aarch64/tcg-target.c.inc | 12
On 4/15/25 12:25, Richard Henderson wrote:
Here we cannot rely on the default copied from
tcg_op_insert_{after,before}, because the relevant
op could be typeless, such as INDEX_op_call.
Fixes: ...
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 3 +++
1 file changed, 3 insertions(+)
diff -
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Introduce a new "vbootrom" field in the AspeedMachineClass to indicate whether
> a machine supports the virtual boot ROM region.
>
> Set this field to true by default for the AST2700-A0 and AST2700-A1 EVB
> machines.
>
> Signed-off-by: Jamin Lin
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> The variable "sram_name" was only used for naming the SRAM memory region.
> Rename it to "name" for consistency with similar code and avoid unnecessary
> new local variable declarations.
>
> Signed-off-by: Jamin Lin
> Reviewed-by: Cédric Le Goa
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Introduce a new vbootrom memory region. The region is mapped at address
> "0x" and has a size of 128KB, identical to the SRAM region size.
> This memory region is intended for loading a vbootrom image file as part of
> the
> boot proces
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Using the vbootrom image support and the boot ROM binary is
> now passed via the -bios option, using the image located in
> pc-bios/ast27x0_bootrom.bin.
>
> Signed-off-by: Jamin Lin
Reviewed-by: Nabih Estefan
> ---
> docs/system/arm/aspeed.r
This has to happen after we have the bootrom in QEMU or it will fail
on the default cases. Besides that it looks good.
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Introduce "aspeed_load_vbootrom()" to support loading a virtual boot ROM image
> into the vbootrom memory region, using the "
On Tue, Apr 15, 2025 at 8:43 PM Jamin Lin wrote:
>
> Move the declaration of `rom_size` to an outer scope in aspeed_machine_init()
> so it can be reused for setting up the vbootrom region as well.
>
> This avoids introducing a redundant local variable and ensures consistent
> ROM sizing logic when
On 4/15/25 12:24, Richard Henderson wrote:
Propagate known carry when possible, and simplify the opcodes
to not require carry-in when known. The result will be cleaned
up further by the subsequent liveness analysis pass.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 319 +
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 8 ++--
target/arm/tcg/translate.c | 17 +++--
2 files changed, 5 insertions(+), 20 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 1 -
tcg/aarch64/tcg-target-has.h | 8 ++--
tcg/aarch64/tcg-target.c.inc | 75
3 files changed, 4 insertions(+), 80 deletions(-)
dif
On 4/15/25 12:25, Richard Henderson wrote:
Split these functions out from tcg_out_op.
Call it directly from tcg_gen_code.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc | 6 +-
tcg/arm/tcg-target.c.inc | 8
On 4/16/2025 12:54 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Brian Cain
Sent: Friday, February 28, 2025 10:26 PM
To: qemu-devel@nongnu.org
Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...
On 4/15/25 12:24, Richard Henderson wrote:
Create a function for performing an add with carry-in
and producing carry out. The carry-out result is boolean.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 4 ++
include/tcg/tcg-op.h| 2 +
tcg/tcg-op.c
On 4/15/25 12:25, Richard Henderson wrote:
Most tcg backends already have a function for this;
the rest can split one out from tcg_out_op.
Call it directly from tcg_gen_code.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 4
tcg/aarch64/tcg-target.c.inc |
On 4/15/25 12:25, Richard Henderson wrote:
All uses have been replaced by add/sub carry opcodes.
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 5 --
tcg/aarch64/tcg-target-has.h | 5 --
tcg/arm/tcg-target-has.h | 4 --
tcg/i386/tcg-target-has.h
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tci.c| 54
tcg/tci/tcg-target-opc.h.inc | 1 +
tcg/tci/tcg-target.c.inc | 69 +++-
3 files changed, 116 insertions(+), 8
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target-has.h | 8 ++---
tcg/tci.c| 66 +++-
tcg/tci/tcg-target.c.inc | 28 -
3 files changed, 9 insertions(+), 93 deletions(-)
di
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target-con-set.h | 6 +-
tcg/sparc64/tcg-target-has.h | 8 +-
tcg/sparc64/tcg-target.c.inc | 169 +++
3 files changed, 19 insertions(+), 164 deletions(-)
On 4/15/25 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/ppc/translate.c | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a52cbc869a..e082d50977 100644
--- a/target/ppc/translate
On 4/15/25 12:24, Richard Henderson wrote:
Pass the sparc COND_* value not the tcg TCG_COND_* value.
This makes the usage within add2/sub2 clearer.
Signed-off-by: Richard Henderson
---
tcg/sparc64/tcg-target.c.inc | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
On 4/15/25 12:24, Richard Henderson wrote:
We have replaced this with support for add/sub carry.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target-con-set.h | 2 --
tcg/s390x/tcg-target-has.h | 8 +++---
tcg/s390x/tcg-target.c.inc | 50 --
On Wed, Apr 16, 2025 at 8:07 PM Daniel P. Berrangé wrote:
>
> On Wed, Apr 16, 2025 at 07:19:29PM +0300, Yuri Nesterov wrote:
> > Currently, there is a special case for usb-host devices added using the
> > hostbus= and hostaddr= properties to avoid adding them to the hotplug
> > watchlist, since th
On Tue, Apr 15, 2025 at 07:46:14PM +0100, Alex Bennée wrote:
> Manos Pitsidianakis writes:
>
> > A hang was observed when running a small kernel that exercised VIRTIO
> > GPU under TCG. This is an edge-case and won't happen under typical
> > conditions.
>
> Should I (or MST?) pull these into a
On 4/15/25 23:55, Philippe Mathieu-Daudé wrote:
@@ -2457,7 +2457,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo,
TCGReg datahi,
switch (memop & MO_SIZE) {
case MO_8:
- /* This is handled with constraints on INDEX_op_qemu_st8_i32. */
+ /* This is ha
On 4/15/25 12:24, Richard Henderson wrote:
We have replaced this with support for add/sub carry.
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target-con-set.h | 2 --
tcg/arm/tcg-target-has.h | 4 +--
tcg/arm/tcg-target.c.inc | 47
3 files
On 4/15/25 12:25, Richard Henderson wrote:
All integer opcodes are now converted to TCGOutOp.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 +++-
tcg/aarch64/tcg-target.c.inc | 7 ---
tcg/arm/tcg-target.c.inc
On 4/15/25 12:24, Richard Henderson wrote:
Use this in gen_addc and gen_rsubc, both of which need
add with carry-in and carry-out.
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/microbla
1 - 100 of 223 matches
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