> 2025年3月25日 17:51，Stefano Garzarella 写道：
>
> On Tue, Mar 25, 2025 at 04:39:46PM +0800, Haoqian He wrote:
>>> 2025年3月24日 22:31，Stefano Garzarella 写道：
>>> On Thu, Mar 20, 2025 at 08:21:30PM +0800, Haoqian He wrote:
> 2025年3月19日 23:20，Stefano Garzarella 写道：
> On Fri, Mar 14, 2025 at 06:
This patch adds the new VM state change cb type `VMChangeStateHandlerWithRet`,
which has return value for `VMChangeStateEntry`.
Thus, we can register a new VM state change cb with return value for device.
Note that `VMChangeStateHandler` and `VMChangeStateHandlerWithRet` are mutually
exclusive and
This patch captures the error of vhost_virtqueue_stop() in vhost_dev_stop()
and returns the error upward.
Specifically, if QEMU is disconnected from the vhost backend, some actions
in vhost_dev_stop() will fail, such as sending vhost-user messages to the
backend (GET_VRING_BASE, SET_VRING_ENABLE)
At the end of the VM live migration, the vhost device will be stopped.
Currently, if the vhost-user backend crashes, vhost device's set_status()
would not return failure, live migration won't perceive the disconnection
with the backend. After the live migration is successful, the stale inflight
IO
I hit following error which testing migration in pure RoCE env:
"-incoming rdma:[::]:8089: RDMA ERROR: You only have RoCE / iWARP devices in
your
systems and your management software has specified '[::]', but IPv6 over RoCE /
iWARP is not supported in Linux.#012'."
In our setup, we use rdma bind
Hi everyone,
The QEMU v7.2.17 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-7.2.17.tar.xz
https://download.qemu.org/qemu-7.2.17.tar.xz.sig (signature)
v7.2.17 is now tagged in t
Hi everyone,
The QEMU v9.2.3 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-9.2.3.tar.xz
https://download.qemu.org/qemu-9.2.3.tar.xz.sig (signature)
v9.2.3 is now tagged in the o
Hi everyone,
The QEMU v8.2.10 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-8.2.10.tar.xz
https://download.qemu.org/qemu-8.2.10.tar.xz.sig (signature)
v8.2.10 is now tagged in t
We have some users of the PL011 struct which embed it directly into
their own state structs. This means that the Rust version of the
device must have a state struct that is the same size or smaller
than the C struct.
In commit 9b642097d6b7 ("rust: pl011: switch to safe chardev operation")
the Rust
On Wed, Mar 26, 2025 at 06:40:10PM +0100, Eric Auger wrote:
> On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> > From: Nicolin Chen
> >
> > If a vSMMU is configured as a accelerated one, HW IOTLB will be used
> > and all cache invalidation should be done to the HW IOTLB too, v.s.
> > the emulated iot
John Snow writes:
> On Wed, Mar 26, 2025 at 2:08 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > A few transitive dependencies were left floating; as a result, pip's
>> > dependency solver can pull in newer dependencies, which we don't
>> > want. Pin them down.
>> >
>> > Signed-off-b
On Wed, Mar 26, 2025 at 5:44 PM Mi, Dapeng wrote:
>
>
> On 3/26/2025 2:46 PM, Dongli Zhang wrote:
> > Hi Dapeng,
> >
> > PATCH 1-4 from the below patchset are already reviewed. (PATCH 5-10 are for
> > PMU
> > registers reset).
> >
> > https://lore.kernel.org/all/20250302220112.17653-1-dongli.zh..
>-Original Message-
>From: Cédric Le Goater
>Subject: [PATCH for-10.1 13/32] vfio: Move VFIOAddressSpace helpers into
>container-base.c
>
>VFIOAddressSpace is a common object used by VFIOContainerBase which is
>declared in "hw/vfio/vfio-container-base.h". Move the VFIOAddressSpace
>relat
On 3/27/2025 10:15 AM, Mingwei Zhang wrote:
> On Wed, Mar 26, 2025 at 5:44 PM Mi, Dapeng wrote:
>>
>> On 3/26/2025 2:46 PM, Dongli Zhang wrote:
>>> Hi Dapeng,
>>>
>>> PATCH 1-4 from the below patchset are already reviewed. (PATCH 5-10 are for
>>> PMU
>>> registers reset).
>>>
>>> https://lore.k
From: Qiang Yu
0 is used as DRM_FORMAT_MOD_LINEAR already.
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
---
hw/display/vhost-user-gpu.c | 3 ++-
hw/display/virtio-gpu-udmabuf.c | 4 +++-
ui/egl-helpers.c| 3 ++-
3 files changed, 7 insertions(+), 3 deletions(-)
d
From: Qiang Yu
It's used already, just check it explicitly.
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
---
ui/egl-helpers.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c
index d194d004b7..432863d702 100644
--- a/
From: Qiang Yu
We need spice version >= 0.15.3 which has spice_qxl_gl_scanout2
API for multi plane scanout support.
v2:
* use new dmabuf API and check length
* check spice_qxl_gl_scanout2 present instead of
bump spice version dependency
Signed-off-by: Qiang Yu
---
meson.build|
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier with this MR:
* https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658
The side effect is some texture will become multi-plane which
breaks qemu. Because qemu currently only support single plane
texture.
For example,
From: Qiang Yu
v2:
* use new dmabuf API and check length
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
---
include/ui/egl-helpers.h | 5 ++-
ui/dbus-listener.c | 19 +
ui/egl-helpers.c | 91 ++--
ui/spice-display.c |
From: Qiang Yu
mesa/radeonsi is going to support explicit modifier which
may export a multi-plane texture. For example, texture with
DCC enabled (a compressed format) has two planes, one with
compressed data, the other with meta data for compression.
v2:
* change API qemu_dmabuf_get_fd/offset/
From: Qiang Yu
To handle multi plane.
v3:
* rename interface
* add x/y/backing_width/backing_height arg
v2:
* use new dmabuf API and check length
Reviewed-by: Marc-André Lureau
Signed-off-by: Qiang Yu
---
ui/dbus-display1.xml | 45 +
ui/dbus-listener.c | 112 +++
Recently, we removed ipv6 restriction[0] from RDMA migration, add a
test for it.
[0]
https://lore.kernel.org/qemu-devel/20250326095224.9918-1-jinpu.w...@ionos.com/
Cc: Jack Wang
Cc: Michael R. Galaxy
Cc: Peter Xu
Cc: Yu Zhang
Signed-off-by: Li Zhijian
---
This test is added based on [1]
S
On 3/26/2025 2:46 PM, Dongli Zhang wrote:
> Hi Dapeng,
>
> PATCH 1-4 from the below patchset are already reviewed. (PATCH 5-10 are for
> PMU
> registers reset).
>
> https://lore.kernel.org/all/20250302220112.17653-1-dongli.zh...@oracle.com/
>
> They require only trivial modification. i.e.:
>
> h
Please fix this compiling error.
cc -m64 -mcx16 -Ilibcommon.a.p -Isubprojects/libvduse -I../subprojects/libvduse
-I/usr/include/p11-kit-1 -I/usr/include/pixman-1 -I/usr/include/libpng16
-I/usr/include/spice-server -I/usr/include/spice-1 -I/usr/include/libusb-1.0
-I/usr/include/glib-2.0 -I/usr
Instead of TARGET_INSN_START_EXTRA_WORDS, use
TCGContext::insn_start_words().
Define TARGET_INSN_START_WORDS_MAX and reduce
TARGET_INSN_START_EXTRA_WORDS scope.
Unify tcg_gen_insn_start() prototypes.
(preparatory for heterogeneous emulation)
Philippe Mathieu-Daudé (12):
tcg: Declare TARGET_INSN
On Wed, Mar 26, 2025 at 1:34 PM wrote:
>
> From: Qiang Yu
>
> v2:
> * use new dmabuf API and check length
>
> Signed-off-by: Qiang Yu
Reviewed-by: Marc-André Lureau
> ---
> include/ui/egl-helpers.h | 5 ++-
> ui/dbus-listener.c | 19 +
> ui/egl-helpers.c | 91 +++
On Tue, Mar 25, 2025 at 09:49:38PM +0100, ~h0lyalg0rithm wrote:
> From: Suraj Shirvankar
>
Please include the rationale for this change in the commit description.
This way anyone reading the git log will be able to understand the
intent behind this change. Something like:
IORING_SETUP_SINGLE_
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
second release candidate for the QEMU 10.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-10.0.0-rc1.tar.xz
http://download.qe
Hello Jinqian
On 3/25/25 09:00, yangjinqian via wrote:
Hi,
I'm observing intermittent failures when enabling the HNS3 network port in VM
using
QEMU with the mainline kernel.
Would you mind opening a gitlab issue with more details on the
context, host, guest, HW ?
https://gitlab.com/qem
Hi,
> > >2) The security posture of the system may be different between 2
> > > validly
> > > signed images. Think of Daniel's example of verbose kernel output. Maybe I
> > > consider verbose kernel output already inacceptable, while RH thinks it's
> > > an
> > > ok posture to have. The us
This form is used to annotate a return type without an accompanying
description, for when there is no "Returns:" information in the source
doc, but we have a return type we want to generate a cross-reference to.
The syntax is:
:return-nodesc: TypeName
It's primarily necessary because Sphinx alwa
On Wed, Mar 26, 2025 at 05:13:50PM -0300, Fabiano Rosas wrote:
> Michael Roth writes:
>
> > Quoting Tom Lendacky (2025-03-26 14:21:31)
> >> On 3/26/25 13:46, Tom Lendacky wrote:
> >> > On 3/7/25 12:15, Fabiano Rosas wrote:
> >> >> From: Steve Sistare
> >> >>
> >> >> Unlike cpr-reboot mode, cpr-t
Excellent find. Thank you very much for checking on the history.
Hopefully my comments were not too hard to read. =)
FYI: I've since left Akamai last year and now work at Nvidia.
Reviewed-by: Michael Galaxy
On 3/26/25 04:52, Jack Wang wrote:
I hit following error which testing migration in
On Wed, Mar 26, 2025 at 3:18 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Tue, Mar 25, 2025 at 4:05 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > The pylint config is being left in place because the settings differ
> >> > enough from the python/ directory set
On Wed, Mar 26, 2025 at 2:13 AM Markus Armbruster wrote:
> John Snow writes:
>
> > On Tue, Mar 25, 2025 at 3:53 AM Markus Armbruster
> wrote:
> >
> >> John Snow writes:
> >>
> >> > Update the python tests to also check qapi. No idea why I didn't do
> this
> >> > before. I guess I was counting
On Tue, Mar 25, 2025 at 5:42 AM Markus Armbruster wrote:
> John Snow writes:
>
> > The new qapidoc transmogrifier can generate "Returns" statements with
> > type information just fine, so we can remove it from the source where it
> > doesn't add anything particularly novel or helpful and just re
Michael Roth writes:
> Quoting Tom Lendacky (2025-03-26 14:21:31)
>> On 3/26/25 13:46, Tom Lendacky wrote:
>> > On 3/7/25 12:15, Fabiano Rosas wrote:
>> >> From: Steve Sistare
>> >>
>> >> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
>> >> in the migration stream file
On Wed, Mar 26, 2025 at 2:08 AM Markus Armbruster wrote:
> John Snow writes:
>
> > A few transitive dependencies were left floating; as a result, pip's
> > dependency solver can pull in newer dependencies, which we don't
> > want. Pin them down.
> >
> > Signed-off-by: John Snow
>
> What problem
This patch changes the qapidoc transmogrifier to generate Return value
documentation for any command that has a return value but hasn't
explicitly documented that return value.
Signed-off-by: John Snow
---
docs/sphinx/qapidoc.py | 14 --
scripts/qapi/parser.py | 15 +++
s
Well, I tried. Maybe not very hard. Sorry!
Signed-off-by: John Snow
---
qapi/block-core.json | 6 +++---
qapi/block-export.json | 2 +-
qapi/block.json | 2 +-
qapi/control.json| 5 ++---
qapi/dump.json | 5 ++---
qapi/introspect.json | 6 +++---
qapi/job.jso
The new qapidoc transmogrifier can generate "Returns" statements with
type information just fine, so we can remove it from the source where it
doesn't add anything particularly novel or helpful and just repeats the
type info.
This patch does not touch Returns: lines that add some information
(pote
v2: fix multi-return-sections bug :(
John Snow (4):
docs/qapi-domain: add return-nodesc
docs, qapi: generate undocumented return sections
qapi: remove trivial "Returns:" sections
qapi: rephrase return docs to avoid type name
docs/devel/qapi-domain.rst | 30 ++
Quoting Tom Lendacky (2025-03-26 14:21:31)
> On 3/26/25 13:46, Tom Lendacky wrote:
> > On 3/7/25 12:15, Fabiano Rosas wrote:
> >> From: Steve Sistare
> >>
> >> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
> >> in the migration stream file and recreate them later, becau
On Wed, Mar 26, 2025 at 06:18:49PM +0100, Eric Auger wrote:
> > @@ -561,6 +561,16 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg
> > *cfg,
> >
> > decode_ste_config(cfg, config);
> >
> > + /* S1DSS.Terminate is same as Config.abort for default stream */
>
> S1DSS. Termination
On Wed, Mar 26, 2025 at 03:16:18PM +0100, Eric Auger wrote:
> > @@ -1395,6 +1403,13 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
> >
> > trace_smmuv3_cmdq_cfgi_cd(sid);
> > smmuv3_flush_config(sdev);
> > +
> > +if (smmuv3_accel_batch_cmds(sdev->smmu, sde
On 3/26/25 13:46, Tom Lendacky wrote:
> On 3/7/25 12:15, Fabiano Rosas wrote:
>> From: Steve Sistare
>>
>> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
>> in the migration stream file and recreate them later, because the physical
>> memory for the blocks is pinned and
On 26/03/2025 15.18, Hanna Czenczek wrote:
On 26.03.25 13:38, Thomas Huth wrote:
From: Thomas Huth
This reverts commit e2668ba1ed44ad56f2f1653ff5f53b277d534fac.
This commit made test 162 fail occasionally with:
162 fail [13:06:40] [13:06:40] 0.2s (last: 0.2s) output mismatch
On Wed, Mar 26, 2025 at 02:38:04PM +0100, Eric Auger wrote:
> > +/* Update batch->ncmds to the number of execute cmds */
> > +int smmuv3_accel_issue_cmd_batch(SMMUState *bs, SMMUCommandBatch *batch)
> > +{
> > +SMMUv3AccelState *s_accel = ARM_SMMUV3_ACCEL(bs);
> > +uint32_t total = batch->n
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
mips_cpu_is_64bit() returns whether the CPU is a
32-bit or a 64-bit one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-qom.h | 2 ++
target/mips/cpu.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/target/mips/cpu-q
Am 19. März 2025 18:06:14 UTC schrieb Peter Maydell :
>On Tue, 18 Mar 2025 at 20:57, Bernhard Beschow wrote:
>>
>> TYPE_FSL_IMX8MP is created using object_new(), so must be realized with
>> qdev_realize_and_unref() to keep the reference counting intact.
>>
>> Signed-off-by: Bernhard Beschow
>>
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Use the provided smmuv3-accel helper functions to issue the
> command to physical SMMUv3.
>
> Signed-off-by: Nicolin Chen
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/smmuv3-internal.h | 11
> hw/arm/smmuv3.c
AioContext's glib integration only supports ppoll(2) file descriptor
monitoring. epoll(7) and io_uring(7) disable themselves and switch back
to ppoll(2) when the glib event loop is used. The main loop thread
cannot use epoll(7) or io_uring(7) because it always uses the glib event
loop.
Future QEMU
This series hooks the epoll and io_uring file descriptor monitoring
implementations up to the glib event loop so that even the main loop thread can
use them. Until now the main loop thread was stuck using ppoll(2) because the
glib event loop semantics weren't supported by fdmon-epoll.c and
fdmon-io
On 21/03/25, Philippe Mathieu-Daudé wrote:
> Hi,
>
> In this series we replace the TCG_GUEST_DEFAULT_MO definition
> from "cpu-param.h" by a 'guest_default_memory_order' field in
> TCGCPUOps.
>
> Since tcg_req_mo() now accesses tcg_ctx, this impact the
> cpu_req_mo() calls in accel/tcg/{cputlb,us
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled
frontends, otherwise we use a default value of TCG_MO_ALL.
In order to simplify, require the definition for all targets,
defining it for hexagon, m68k, rx, sh4 and tricore.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johanss
On 3/7/25 12:15, Fabiano Rosas wrote:
> From: Steve Sistare
>
> Unlike cpr-reboot mode, cpr-transfer mode cannot save volatile ram blocks
> in the migration stream file and recreate them later, because the physical
> memory for the blocks is pinned and registered for vfio. Add a blocker
> for vo
test-nested-aio-poll relies on internal details of how fdmon-poll.c
handles AioContext polling. Skip it when other fdmon implementations are
in use.
Note that this test is only built on POSIX systems so it is safe to
include "util/aio-posix.h".
Signed-off-by: Stefan Hajnoczi
---
tests/unit/test
The io_uring(7) file descriptor monitor cannot enter polling mode
because it needs to submit a POLL_ADD SQE every time a file descriptor
becomes active. Submitting SQEs only happens in FDMonOps->wait() outside
of polling mode.
Fix this using the multi-shot mechanism introduced in Linux 5.13 and
li
On Mon, 2025-03-10 at 16:14 +0100, Philippe Mathieu-Daudé wrote:
> The storage keys are part of the machine memory.
>
> Introduce the TYPE_DUMP_SKEYS_INTERFACE type,
> allowing machine using storage keys to dump them
> when a DumpSKeysInterface::qmp_dump_skeys() callback
> is provided.
>
> Signed
There is no need for aio_context_use_g_source() now that epoll(7) and
io_uring(7) file descriptor monitoring works with the glib event loop.
AioContext doesn't need to be notified that GSource is being used.
Signed-off-by: Stefan Hajnoczi
---
include/block/aio.h | 3 ---
tests/uni
On 3/25/25 10:40, Philippe Mathieu-Daudé wrote:
mips_env_64bit_enabled() returns whether the CPU is running
in 32-bit or 64-bit (behavior which might change at runtime).
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/internal.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> Now that we can have multiple user-creatable smmuv3-accel devices,
> each associated with different pci buses, update IORT ID mappings
> accordingly.
>
> Signed-off-by: Shameer Kolothum
> ---
> hw/arm/virt-acpi-build.c | 113 +++
On 3/25/25 10:40, Philippe Mathieu-Daudé wrote:
mips_cpu_is_64bit() returns whether the CPU is a
32-bit or a 64-bit one.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/cpu-qom.h | 2 ++
target/mips/cpu.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/target/mips/cpu-q
Hi,
Recently on s390x we have enabled mmap support for vfio-pci devices [1].
This allows us to take advantage and use userspace drivers on s390x. However,
on s390x we have special instructions for MMIO access. Starting with z15
(and newer platforms) we have new PCI Memory I/O (MIO) instructions w
Starting with z15 (or newer) we can execute mmio
instructions from userspace. On older platforms
where we don't have these instructions available
we can fallback to using system calls to access
the PCI mapped resources.
This patch adds helper functions for mmio reads
and writes for s390x.
Signed-
On s390x we can now support userspace mmio and mmap
from vfio. This patch uses s390x mmio support to
enable the NVMe userspace driver for s390x.
Signed-off-by: Farhan Ali
---
block/nvme.c | 95 ++--
1 file changed, 77 insertions(+), 18 deletions(-)
Louis-Vincent DERIAN writes:
> Hello,
>
>
>
> My name is Louis-Vincent DERIAN, and I work for STMicroelectronics. We are
> interested in using your software to facilitate
> our development and testing processes. However, we need to know if
> QEMU has ISO 26262 certification.
The QEMU project
On 3/25/25 15:44, Richard Henderson wrote:
Now that we can handle the MCU allocating only a portion of the
first page to i/o, increase the page size. Choose 10 as larger
than the i/o on every MCU, just so that this path is tested.
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h |
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 16
target/arm/cpu.c | 15 +--
target/arm/cpu.h | 2 --
target/arm/cpu64.c
On Wed, Mar 26, 2025 at 06:13:44PM +0100, Kevin Wolf wrote:
> Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben:
> > From: Suraj Shirvankar
> >
> > Signed-off-by: Suraj Shirvankar
> > ---
> > util/fdmon-io_uring.c | 8 +++-
> > 1 file changed, 7 insertions(+), 1 deletion(-)
>
> As Stef
From: Eric Auger
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory generates target/arm/cpu-sysregs.h.inc
containing d
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18
target/arm/cpu.h | 6 ---
target/arm/cpu64.c| 16 +++
targ
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +-
target/arm/cpu.c | 24 +++
target/arm/cpu.h | 7 --
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> If a vSMMU is configured as a accelerated one, HW IOTLB will be used
> and all cache invalidation should be done to the HW IOTLB too, v.s.
> the emulated iotlb. In this case, an iommu notifier isn't registered,
> as the device
Generated against Linux 6.14-rc1.
Reviewed-by: Sebastian Ott
Signed-off-by: Cornelia Huck
---
target/arm/cpu-sysregs.h.inc | 43 +---
1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
hw/intc/armv7m_nvic.c | 5 +-
target/arm/cpu-features.h | 10 ++--
target/arm/cpu.c | 8 +--
target/arm/cpu.h | 3 -
target/arm/c
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c| 7 ++-
target/arm/helper.c | 2 +-
target/arm/kvm
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 74 +++
target/arm/cpu.h | 4 ---
target/arm/cpu64.c| 8 ++---
target/arm/h
From: Eric Auger
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 40 -
target/arm/cpu.c | 29
target/arm/cpu.h | 2 --
From: Eric Auger
Also add kvm add accessors for storing host features into idregs.
Reviewed-by: Richard Henderson
Reviewed-by: Sebastian Ott
Signed-off-by: Eric Auger
Signed-off-by: Cornelia Huck
---
target/arm/cpu-features.h | 57 ---
target/arm/cpu-sysr
Next iteration of the id register patches; only small changes.
Changed from v3:
- added R-bs (thanks!)
- added missing SPDX header
- merged patch introducing accessors for kvm to the first user
- skip over sysregs outside of the id register range when generating
register definitions again
Also
From: Eric Auger
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named
Am 25.03.2025 um 21:49 hat ~h0lyalg0rithm geschrieben:
> From: Suraj Shirvankar
>
> Signed-off-by: Suraj Shirvankar
> ---
> util/fdmon-io_uring.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
As Stefan already mentioned, the commit message should say why we want
to set this fl
On 26/03/25 16:12, Cédric Le Goater wrote:
[ ... ]
You could use a buildroot image instead. :
https://github.com/buildroot/buildroot/blob/master/configs/qemu_ppc64le_powernv8_defconfig
Images pushed here :
https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-
On 26/03/25 13:39, Cédric Le Goater wrote:
On 3/25/25 18:38, Aditya Gupta wrote:
<...snip...>
On 25/03/25 22:45, Cédric Le Goater wrote:
One nice about it IIRC was being able to tune the number of
PHBs per chip, which reduced booting time (for 16s) and also
provided support to test various ch
Hi,
On 3/11/25 3:10 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> With nested translation, the underlying HW could support those two fields.
> Allow them according to the updated idr registers after the hw_info ioctl.
s/idr/IDR
>
> When substreams are enabled (S1CDMax != 0), S1DSS field de
Hello,
My name is Louis-Vincent DERIAN, and I work for STMicroelectronics. We are
interested in using your software to facilitate our development and testing
processes. However, we need to know if QEMU has ISO 26262 certification.
Could you please provide us with information about the ISO 26262
On Wed, Mar 26, 2025 at 04:52:54PM +0100, Valentin David wrote:
> Without it, it seems the data gets garbage at the end of the string.
>
> Signed-off-by: Valentin David
> ---
> hw/smbios/smbios.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c
>
On 25/03/25, Philippe Mathieu-Daudé wrote:
> - Remove the TARGET_MIPS64 use in 'cpu-qom.h' to
> make it target agnostic
> - Introduce mips_cpu_is_64bit() as a runtime check
> for compile time TARGET_MIPS64 definition
> - Replace the ldtul_p() gdbstub call by ldn_p()
> - Rename few symbols to av
On Wed, Mar 26, 2025 at 05:22:30PM +0100, Marco Cavenati wrote:
> The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
> 'whence' parameter instead of the 'offset' parameter when calculating the
> new position.
>
> Fixes: 65cf200a51ddc6d0a28ecceac30dc892233cddd7 ("migration: intro
On Tue, Mar 25, 2025 at 1:47 PM John Snow wrote:
>
>
> On Tue, Mar 25, 2025 at 5:41 AM Markus Armbruster
> wrote:
>
>> John Snow writes:
>>
>> > This patch changes the qapidoc transmogrifier to generate Return value
>> > documentation for any command that has a return value but hasn't
>> > expl
The SEEK_CUR case in qio_channel_block_seek was incorrectly using the
'whence' parameter instead of the 'offset' parameter when calculating the
new position.
Fixes: 65cf200a51ddc6d0a28ecceac30dc892233cddd7 ("migration: introduce a
QIOChannel impl for BlockDriverState VMState")
Signed-off-by: Mar
On Wed, Mar 26, 2025 at 05:26:32PM +0800, zoudongjie wrote:
> From: Zhu Yangyang
>
> Calling qmp_block_set_io_throttle() will be blocked for a long time
> when a network disk is configured and the network failure is just about
> to occur.
>
> This series add a timeout parameter for qmp_block_set
This silently fixes issues resulting from trying to allocate 0 bytes.
Fixes error, for example, for writing byte 0x20 to port 0x3c0, then word 0xf09
to port 0x3b4 when CPU is initiated, which shouldn't break.
Signed-off-by: donno2048
---
util/memfd.c | 10 +++---
1 file changed, 7 insertio
On 3/26/25 15:38, Steven Sistare wrote:
On 3/26/2025 3:51 AM, Cédric Le Goater wrote:
Gather all CPR related declarations into "vfio-cpr.h" to reduce exposure
of VFIO internals in "hw/vfio/vfio-common.h". These were introduced in
commit d9fa4223b30a ("vfio: register container for cpr").
Order f
On 3/25/25 15:43, Richard Henderson wrote:
This define isn't used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 84a8f5cc8c..b49e7a7056 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
Hello Marc-André and all,
I am trying to debug an issue where I am unable to get copy-paste to work with
libvirt, qemu and VNC (no spice).
The qemu command line that results from the libvirt vdagent and vnc
configuration contains:
-chardev socket,id=charchannel0,fd=52,server=on,wait=off \
-dev
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. In
particular because type array declared with such macro
are easier to review.
In few commits we are going to add more types, so replace
th
On 3/25/25 15:44, Richard Henderson wrote:
If i/o does not cover the entire first page, allocate a portion
of ram as an i/o device, so that the entire first page is i/o.
While memory_region_init_ram_device_ptr is happy to allocate
the RAMBlock, it does not register the ram for migration.
Do this
On 3/25/25 08:40, Philippe Mathieu-Daudé wrote:
MIPS MMU API declared in tcg-internal.h has public linkage.
In order to avoid name clashing with other targets, prefix
the API with 'mips_'.
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/tcg-internal.h | 2 +-
target/mips/cpu.c
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