From: Santiago Monserrat Campanello
semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Reviewed-by: Alistair Francis
Reviewed-by: Thomas Huth
Message-ID: <20250305102632.91376-1-santimons...@gmail.com>
S
From: Richard Henderson
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_ch
From: Richard Henderson
The third argument of the syscall contains the size of the
cpu mask in bytes, not bits. Nor is the size rounded up to
a multiple of sizeof(abi_ulong).
Cc: qemu-sta...@nongnu.org
Reported-by: Andreas Schwab
Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe
From: Deepak Gupta
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.2.1. Shadow Stack Poin
From: Nicholas Piggin
Facility interrupt checks in general should come after the ISA version
check, because the facility interrupt and facility type themselves are
ISA dependent and should not appear on CPUs where the instruction does
not exist at all.
This resolves a QEMU crash booting NetBSD/m
From: Nicholas Piggin
DSRR0/1 registers are in the BookE ISA not e200 specific, so
remove the duplicate e200 register definitions.
Cc: Roman Kapl
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768
Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging")
Signed-
From: Chao Liu
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting, it was found that
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
On Tue, Mar 25, 2025 at 2:37 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Tue, Mar 25, 2025 at 7:26 AM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 10:06 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
> > > >
> > > > On Mon, Mar 24, 20
From: Steven Lee
Updated the IRQ handler mask check to AND with select variable.
This ensures that the interrupt service routine is correctly triggered
for the interrupts within the same irq group.
For example, both `eth0` and the debug UART are handled in `GICINT132`.
Without this fix, the debu
From: Nicholas Piggin
DSRR0/1 registers are in the BookE ISA not e200 specific, so
remove the duplicate e200 register definitions.
Cc: Roman Kapl
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768
Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging")
Signed-
From: Richard Henderson
The third argument of the syscall contains the size of the
cpu mask in bytes, not bits. Nor is the size rounded up to
a multiple of sizeof(abi_ulong).
Cc: qemu-sta...@nongnu.org
Reported-by: Andreas Schwab
Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe
From: Jamin Lin
The maximum padding size is either 64 or 128 bytes and should always be smaller
than "req_len". If "padding_size" exceeds "req_len", then
"req_len - padding_size" underflows due to "uint32_t" data type, leading to a
large incorrect value (e.g., `0xFFXX`). This causes an out-of
From: Philippe Mathieu-Daudé
These warnings are breaking some build configurations since 2 months
now (https://gitlab.com/qemu-project/qemu/-/issues/2575):
ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated:
first deprecated in macOS 15.0 - use NSView.displayLink(targe
From: Nicholas Piggin
DSRR0/1 registers are in the BookE ISA not e200 specific, so
remove the duplicate e200 register definitions.
Cc: Roman Kapl
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2768
Fixes: 0e3bf4890906 ("ppc: add DBCR based debugging")
Signed-
Fixes: 9bc9e9511944 (make-release: switch to .xz format by default)
Signed-off-by: Michael Tokarev
Reviewed-by: Philippe Mathieu-Daudé
(cherry picked from commit 14fb6dbbc50f43057202c685c3aa017287cca37f)
Signed-off-by: Michael Tokarev
diff --git a/Makefile b/Makefile
index b65b0bd41a..c92a3cf78
From: Konstantin Shkolnyy
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Reviewed-by: Michael S.
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
From: Harsh Prateek Bora
When POWER10 CPU was made as default, we missed keeping POWER9 as
default for older pseries releases (pre-9.0) at that time.
This caused breakge in default cpu evaluation for older pseries
machines and hence this fix.
Fixes: 51113013f3 ("ppc/spapr: change pseries machine
From: Chao Liu
Some vector instructions are special, such as the vlm.v instruction,
where setting its vl actually sets evl = (vl + 7) >> 3. To improve
maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to
check for the condition vstart >= vl. This function will also handle
cases inv
The following patches are queued for QEMU stable v9.2.3:
https://gitlab.com/qemu-project/qemu/-/commits/staging-9.2
Patch freeze is 2025-03-24 (frozen), and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/9.2
Please respond here or CC qemu-sta...@nongnu.org on any addi
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
From: Konstantin Shkolnyy
Add .set_vnet_le() function that always returns success, assuming that
vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and
outputs the message:
"backend does not support LE vnet headers; falling back on userspace virtio"
Reviewed-by: Michael S.
From: Santiago Monserrat Campanello
semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Reviewed-by: Alistair Francis
Reviewed-by: Thomas Huth
Message-ID: <20250305102632.91376-1-santimons...@gmail.com>
S
From: Guo Hongyu
Refer to the link below for a description of the vldi instructions:
https://jia.je/unofficial-loongarch-intrinsics-guide/lsx/misc/#synopsis_88
Fixed errors in vldi instruction implementation.
Signed-off-by: Guo Hongyu
Tested-by: Xianglai Li
Signed-off-by: Xianglai Li
Reviewed
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
From: Richard Henderson
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_ch
From: Richard Henderson
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_ch
From: Richard Henderson
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: qemu-sta...@nongnu.org
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson
The following patches are queued for QEMU stable v7.2.17:
https://gitlab.com/qemu-project/qemu/-/commits/staging-7.2
Patch freeze is 2025-03-24 (frozen), and the release is planned for 2025-03-26:
https://wiki.qemu.org/Planning/7.2
Please respond here or CC qemu-sta...@nongnu.org on any add
From: Joe Komlodi
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipe
Temporary variable ret is assigned at last line and return, it can
be removed and return directly.
Signed-off-by: Bibo Mao
Reviewed-by: Markus Armbruster
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/tcg/tlb_helper.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff -
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/xlnx-zynqmp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index d6022ff2d3d..ec2b3a41eda 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-
Hi
On Tue, Mar 25, 2025 at 7:26 AM Qiang Yu wrote:
>
> On Mon, Mar 24, 2025 at 10:06 PM Marc-André Lureau
> wrote:
> >
> > Hi
> >
> > On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
> > >
> > > On Mon, Mar 24, 2025 at 6:04 PM Marc-André Lureau
> > > wrote:
> > > >
> > > > Hi
> > > >
> > > > On
On 3/24/25 22:08, Michael Tokarev wrote:
24.03.2025 23:46, Cédric Le Goater wrote:
Is there anything in there worth to pick up for stable series?
you are fast !
I was just about to send final announcements for a bunch of next
stable releases, and noticed another pull request has been merged
On 3/23/25 10:37, Richard Henderson wrote:
Not that AVR has memory paging traps, but it's better
form to allow the memory operation to finish before
updating the cpu register.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 32 +++-
1 file changed, 1
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero; also allow folding
stack pointer offsets into the arithmetic.
So far, all offsets are 0.
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 42 --
1 file change
From: Thomas Huth
This test currently fails if the "dbus" display has not been compiled
into the binary (which can happen when CFI has been enabled, for example).
Check for the error message to skip the test in that case.
While we're at it, also make sure that this test is covered in the
right s
On Tue, Mar 25, 2025 at 9:51 AM Thomas Huth wrote:
>
> From: Thomas Huth
>
> We've got a dedicated section for UI options nowadays, so the
> D-Bus display should get reported here, too.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Marc-André Lureau
> ---
> meson.build | 2 +-
> 1 file changed
From: Thomas Huth
We've got a dedicated section for UI options nowadays, so the
D-Bus display should get reported here, too.
Signed-off-by: Thomas Huth
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 41f68d38069..205fb43bf7b 1
bibo mao writes:
> Markus,
>
> Thanks for your reviewing and guidance.
You're welcome!
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index d4705210370..d4d05d82315 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -20,7 +2
On 24/03/2025 19.58, Philippe Mathieu-Daudé wrote:
Both s390_cpu_list() and s390_set_qemu_cpu_model() are
defined in cpu_models.c, move their declarations in the
related "cpu_models.h" header. Use full path to header
in s390-virtio-ccw.c file.
Suggested-by: Thomas Huth
Signed-off-by: Philippe M
On 24/03/2025 20.04, Philippe Mathieu-Daudé wrote:
On 24/3/25 20:02, Richard Henderson wrote:
On 3/24/25 11:58, Philippe Mathieu-Daudé wrote:
Register s390_cpu_list() as CPUClass:list_cpus callback
and remove the cpu_list definition.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/cp
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8a1a8faf6b..ab7412772bc 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -971,7 +971,6 @@ str
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386/cpu.h | 1 +
target/loongarch/cpu.h | 1 +
target/m68k/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index 98a69846119..854498ac51c 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -140,7 +140,7 @@ s
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h | 3 ---
include/exec/exec-all.h | 1 +
include/exec/tlb-flags.h| 1 +
linux-user/sparc/target_syscall.h | 2 ++
hw/alpha/dp
On 3/24/25 21:58, Pierrick Bouvier wrote:
This series focuses on removing compilation units duplication in hw/arm. We
start with this architecture because it should not be too hard to transform it,
and should give us some good hints on the difficulties we'll meet later.
We first start by making
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/digic_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index 2492fafeb85..466b8b84c0e 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
Remove kvm unused headers.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/xlnx-versal.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index 278545a3f7b..f0b383b29ee 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
target/ppc/mmu-hash64.h | 2 ++
target/i386/tcg/system/excp_helper.c | 1 +
target/i386/xsave_helper.c | 1 +
target/riscv/vector_helper.c | 1 +
5 files
Implement the register command of "ibm,configure-kernel-dump" RTAS call.
The register just verifies the structure of the fadump memory structure
passed by kernel, and set fadump_registered in spapr state to true.
We also store the passed fadump memory structure, which will later be
used for preser
Now we eliminated poisoned identifiers from headers, this file can now
be compiled once for all arm targets.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/boot.c | 1 +
hw/arm/meson.build | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/h
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index eb029b65552..4a2cac1252d 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -19,7 +1
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
accel/tcg/tb-internal.h | 1 -
include/exec/cpu-all.h | 22 --
include/hw/core/cpu.h | 2 +-
include/qemu/bswap.h| 2 +-
target/alpha/cpu.h | 2 --
target/arm/cpu.h| 2 --
target/avr/c
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/arm/meson.build | 112 ++---
1 file changed, 56 insertions(+), 56 deletions(-)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 9e8c96059eb..09b1cfe5b57 100644
--- a/hw/arm/me
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
accel/tcg/internal-target.h | 1 +
include/exec/poison.h | 1 +
accel/
Do not rely on target dependent type, but use a fixed type instead.
Since the original type is unsigned, it should be safe to extend its
size without any side effect.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 10 --
target/arm/tcg/hflag
Directly condition associated calls in target/arm/helper.c for now.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h| 8
target/arm/helper.c | 6 ++
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/c
Those files will be compiled once per base architecture ("arm" in this
case), instead of being compiled for every variant/bitness of
architecture.
We make sure to not include target cpu definitions (exec/cpu-defs.h) by
defining header guard directly. This way, a given compilation unit can
access a
Now we made sure important defines are included using their direct
path, we can remove cpu.h from cpu-all.h.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
accel/tcg/cpu-exec.c | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --gi
This define is used only in accel/kvm/kvm-all.c, so we push directly the
definition there. Add more visibility to kvm_arch_on_sigbus_vcpu() to
allow removing this define from any header.
The architectures defining KVM_HAVE_MCE_INJECTION are i386, x86_64 and
aarch64.
Reviewed-by: Richard Henderson
We include this header where needed. When includes set already have
ifdef CONFIG_USER_ONLY, we add it here, else, we don't condition the
include.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
hw/s390x/ipl.h | 1 +
include/exec/cpu-all.h |
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index e5d852fbe2c..db44c0d3016 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -23,7 +2
We prepare to remove cpu.h from cpu-all.h, which will transitively
remove it from accel/tcg/tb-internal.h, and thus from most of tcg
compilation units.
Note: this was caught by a test regression for s390x-softmmu.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 63
include/exec/tlb-flags.h | 87
accel/tcg/cputlb.c | 1 +
accel/tcg/user-exec.c| 1 +
sem
This series focuses on removing compilation units duplication in hw/arm. We
start with this architecture because it should not be too hard to transform it,
and should give us some good hints on the difficulties we'll meet later.
We first start by making changes in global headers to be able to not
We introduce later a mechanism to skip cpu definitions inclusion, so we
can detect it here, and call the correct runtime function instead.
Signed-off-by: Pierrick Bouvier
---
include/exec/target_page.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/exec/target_page.h b/include/ex
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 4
cpu-target.c | 4
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 74017a5ce7c..b1067259e6b 100644
--- a/include/
To eliminate TARGET_AARCH64, we need to make various definitions common
between 32 and 64 bit Arm targets.
Added registers are used only by aarch64 code, and the only impact is on
the size of CPUARMState, and added zarray
(ARMVectorReg zarray[ARM_MAX_VQ * 16]) member (+64KB)
It could be eventually
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 2 --
include/exec/cpu_ldst.h | 1 +
target/alpha/cpu.h | 1 +
target/arm/cpu.h| 1 +
target/avr/cpu.h| 1 +
target/hexagon/cpu.h| 1 +
target/hppa/cpu.h | 1 +
target/i386
We prevent common code to use this define by mistake.
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
---
include/exec/poison.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index f267da60838..a09e0c12631 100644
--- a/include/
On Mon, Mar 24, 2025 at 9:45 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Mon, Mar 24, 2025 at 5:27 PM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 6:09 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 12:19 PM wrote:
> > > >
> > > > From: Qiang Yu
> > > >
> >
The following macros:
- qemu_put_betl()
- qemu_get_betl()
- qemu_put_betls()
- qemu_get_betls()
- qemu_put_sbetl()
- qemu_get_sbetl()
- qemu_put_sbetls()
- qemu_get_sbetls()
are used twice. Expand tl -> 32/64 and remove them.
Philippe Mathieu-Daudé (3):
target/mips: Inline qemu_get_bet
On 3/23/25 10:37, Richard Henderson wrote:
Match the prototype of cpu_memory_rw_debug().
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 2 +-
target/sparc/cpu.h| 2 +-
target/sparc/mmu_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a
On Mon, Mar 24, 2025 at 10:06 PM Marc-André Lureau
wrote:
>
> Hi
>
> On Mon, Mar 24, 2025 at 5:20 PM Qiang Yu wrote:
> >
> > On Mon, Mar 24, 2025 at 6:04 PM Marc-André Lureau
> > wrote:
> > >
> > > Hi
> > >
> > > On Mon, Mar 24, 2025 at 12:19 PM wrote:
> > > >
> > > > From: Qiang Yu
> > > >
>
Signed-off-by: Pierrick Bouvier
---
include/exec/cpu-all.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index eb029b65552..4a2cac1252d 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -19,7 +19,6 @@
#ifndef CPU_ALL_H
#defi
According to PAPR:
R1–7.3.30–3. When the platform receives an ibm,os-term RTAS call, or
on a system reset without an ibm,nmi-interlock RTAS call, if the
platform has a dump structure registered through the
ibm,configure-kernel-dump call, the platform must process each
registere
On 3/24/2025 8:53 PM, ltaylorsimp...@gmail.com wrote:
-Original Message-
From: Anton Johansson
Sent: Wednesday, March 12, 2025 2:46 PM
To: qemu-devel@nongnu.org
Cc: a...@rev.ng; ltaylorsimp...@gmail.com; brian.c...@oss.qualcomm.com;
phi...@linaro.org
Subject: [PATCH 2/2] target/hexag
Markus,
Thanks for your reviewing and guidance.
Regards
Bibo Mao
On 2025/3/24 下午2:05, Markus Armbruster wrote:
Bibo Mao writes:
In function virt_cpu_plug(), Object cpuslot::cpu is set at last
only when there is no any error, otherwise it is problematic that
cpuslot::cpu is set in advance ho
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index e4011004b4..538fcbc215 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -
24.03.2025 23:46, Cédric Le Goater wrote:
Is there anything in there worth to pick up for stable series?
you are fast !
I was just about to send final announcements for a bunch of next
stable releases, and noticed another pull request has been merged.. :)
- "aspeed: Fix maximum number of
I noticed that analyze_packet is marking the implicit pred reads after
marking all the writes. However, the semantics of the instrucion and
packet are to do all the reads, then do the operation, then do all the
writes.
Here is the old code
static void analyze_packet(DisasContext *ctx)
{
Packe
Hi,
Any other concerns for this series?
Thanks
Suravee
On 3/4/2025 9:17 PM, Suravee Suthikulpanit wrote:
Currently, amd-iommu device does not support migration. This series addresses
an issue due hidden AMDVI-PCI device enumeration. Then introduces migratable
VMStateDescription, which saves ne
Currently, the QEMU-emulated AMD IOMMU device use PCI vendor id 0x1022
(AMD) with device id zero (undefined). Eventhough this does not cause any
functional issue for AMD IOMMU driver since it normally uses information
in the ACPI IVRS table to probe and initialize the device per
recommendation in t
Hi Michael,
Gentile ping.
Regards,
Mauro
Em Fri, 7 Mar 2025 20:14:29 +0100
Mauro Carvalho Chehab escreveu:
> Hi Michael,
>
> I'm sending v8 to avoid a merge conflict with v7 due to this
> changeset:
>
>611f3bdb20f7 ("hw/acpi/ghes: Make static")
>
> As ghes_record_cper_errors() was wri
> -Original Message-
> From: Anton Johansson
> Sent: Wednesday, March 12, 2025 2:46 PM
> To: qemu-devel@nongnu.org
> Cc: a...@rev.ng; ltaylorsimp...@gmail.com; brian.c...@oss.qualcomm.com;
> phi...@linaro.org
> Subject: [PATCH 2/2] target/hexagon: Drop `ident` postprocess step
>
> The
On 3/24/25 18:22, Richard Henderson wrote:
On 3/24/25 14:31, Pierrick Bouvier wrote:
On 3/23/25 12:48, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 12
1 file changed, 8 insertions(+), 4 deletions(
On 3/23/25 10:37, Richard Henderson wrote:
Avoid direct use of address_space_memory.
Make use of the softmmu cache of the i/o page.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Pierrick Bouvier
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/cpu-param.h | 8 +--
hw/avr/atmega.c| 54 ++
2 files changed, 35 insertions(+), 27 deletions(-)
diff --git a/target/avr/cpu-param.h b/target/avr/cp
On 3/23/25 10:37, Richard Henderson wrote:
We want to be able to do more common work on MachineClass.
Pass the class name as a string in .class_data.
Signed-off-by: Richard Henderson
---
hw/avr/arduino.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
Reviewed-by: P
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero when accessing from gdb.
Signed-off-by: Richard Henderson
---
target/avr/cpu.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 080f6f3
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 7cfd3d1093..9608e59584 100644
--- a/target/avr/helper.c
+++ b/ta
On 3/23/25 10:37, Richard Henderson wrote:
Prepare for offset_io being non-zero in do_stb.
Signed-off-by: Richard Henderson
---
target/avr/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/avr/helper.c b/target/avr/helper.c
index 9608e59584..3323f32c22 100
On 3/23/25 10:37, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
hw/avr/atmega.h | 20
hw/avr/atmega.c | 22 +-
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/avr/atmega.h b/hw/avr/atmega.h
index a99ee15c7e..f031e6c
On 3/24/25 14:11, Pierrick Bouvier wrote:
On 3/23/25 12:37, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
This does not hurt, even if they are not used.
Signed-off-by: Pierrick Bouvier
---
target/arm/cpu.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/a
On 3/24/25 14:31, Pierrick Bouvier wrote:
On 3/23/25 12:48, Richard Henderson wrote:
On 3/20/25 15:29, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
hw/arm/armv7m.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/hw/arm/armv7m.c b/hw/arm/armv
On 3/23/25 10:37, Richard Henderson wrote:
This define isn't really used.
Signed-off-by: Richard Henderson
---
target/avr/cpu.h| 2 --
target/avr/helper.c | 3 +--
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 06f5ae4d1b..84a8f5c
1 - 100 of 307 matches
Mail list logo
