[PATCH] target/riscv: silent warnings about Smdbltrp/Smrnmi being disabled

As raised by Richard Henderson, these warnings are displayed in user only as well. Disable them for CONFIG_USER_ONLY. Signed-off-by: Clément Léger --- target/riscv/tcg/tcg-cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index

Re: [PATCH 1/1] mem/cxl-type3: Add a default value of sn

On Tue, Feb 11, 2025 at 09:26:55AM +, Jonathan Cameron wrote: > On Tue, 11 Feb 2025 10:24:13 +0800 > Yuquan Wang wrote: > > > The previous default value of sn is UI64_NULL which would cause the > > cookie of nd_interleave_set be '0' and the "invalid interleave-set > > -cookie" failure in labe

Re: [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum

On 12/02/2025 23.34, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 17:23, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 14:53, Philippe Mathieu-Daudé wrote: On 12/2/25 13:56, BALATON Zoltan wrote: On Wed, 12 Feb 2025

Re: [PATCH v2] vdpa: Fix endian bugs in shadow virtqueue

On Wed, Feb 12, 2025 at 5:49 PM Konstantin Shkolnyy wrote: > > VDPA didn't work on a big-endian machine due to missing/incorrect > CPU<->LE data format conversions. > Fixes: 10857ec0ad ("vhost: Add VhostShadowVirtqueue") > Signed-off-by: Konstantin Shkolnyy Acked-by: Eugenio Pérez Thanks! >

Re: [PATCH v2] vdpa: Fix endian bugs in shadow virtqueue

On Wed, Feb 12, 2025 at 7:11 PM Philippe Mathieu-Daudé wrote: > > On 12/2/25 17:49, Konstantin Shkolnyy wrote: > > VDPA didn't work on a big-endian machine due to missing/incorrect > > CPU<->LE data format conversions. > > > > Signed-off-by: Konstantin Shkolnyy > > --- > > Changes in v2: Change d

Re: [PULL 05/12] vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()

13.02.2025 09:32, Cédric Le Goater wrote: .. This seems to be a qemu-stable material (for 9.2). Please let me know if it is not. For 9.0 and above. It applies cleanly. Yup, - I thought it wont be clear. 9.0 & 9.1 are end-of-line at this point, only 9.2 is relevant now. Also 7.2 and 8.2 are s

Re: [PULL 05/12] vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()

On 2/12/25 20:12, Michael Tokarev wrote: 11.02.2025 17:33, Cédric Le Goater wrote: From: Zhenzhong Duan When iommufd_cdev_ram_block_discard_disable() fails for whatever reason, errp should be set or else SIGSEV is triggered in vfio_realize() when error_prepend() is called. By this chance, use

Re: [PATCH v8 10/10] docs/system: virtio-gpu: Document host/guest requirements

On 2025/02/10 1:56, Dmitry Osipenko wrote: From: Alex Bennée This attempts to tidy up the VirtIO GPU documentation to make the list of requirements clearer. There are still a lot of moving parts and the distros have some catching up to do before this is all handled automatically. Signed-off-by

Re: [PATCH v5 8/8] docs/system: Expand the virtio-gpu documentation

On 2025/02/10 6:03, Dmitry Osipenko wrote: On 2/6/25 08:41, Akihiko Odaki wrote: On 2025/02/06 2:40, Dmitry Osipenko wrote: On 2/3/25 08:31, Akihiko Odaki wrote: ... Requirements don't vary much. For example virglrenderer minigbm support is mandatory for crosvm, while for QEMU it's not. Is t

[PATCH v3 25/28] tests/functional/aspeed: Update test ASPEED SDK v09.05

Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed.py b/tests/functional/test_aarch64_aspeed.py index aa817afa4e..788dd29a6d 100755 --- a/tests/functional/test_aarch64

[PATCH v3 10/28] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address

The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to derive the IRQ index numbers. However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ pin to 10 output IRQ pins. The pin nu

[PATCH v3 13/28] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller

Introduce a new ast2700 INTCIO class to support AST2700 INTCIO. Added new register definitions for INTCIO, including enable and status registers for IRQs GICINT192 through GICINT197. Created a dedicated IRQ array for INTCIO, supporting six input pins and six output pins, aligning with the newly def

[PATCH v3 27/28] tests/functional/aspeed: Add test case for AST2700 A1

Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 7 +++ 1 file changed, 7 insertions(+) diff --git a/tests/functional/test_aarch64_aspeed.py b/tests/functional/test_aarch64_aspeed.py index ad2774be15..2afc50265a 100755 --- a/tests/functional/test_aarch64_aspeed.py +++

[PATCH v3 18/28] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1

The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging from 192 to 201. Add a new IRQ map table for AST2700 A1. Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC. Introduce "asp

[PATCH v3 26/28] tests/functional/aspeed: Renamed test case and machine for AST2700 A0

Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed.py b/tests/functional/test_aarch64_aspeed.py index 788dd29a6d..ad2774be15 100755 --- a/tests/functional/test_aarch

[PATCH v3 22/28] hw/arm/aspeed_ast27x0: Add HACE support for AST2700

The HACE controller between AST2600 and AST2700 are almost identical. The HACE controller registers base address starts at 0x1207_ and its alarm interrupt is connected to GICINT4. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery --- hw/arm/aspeed_ast27x0.c | 15 +++ 1 file c

[PATCH v3 21/28] hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test

Currently, it does not support the CRYPT command. Instead, it only sends an interrupt to notify the firmware that the crypt command has completed. It is a temporary workaround to resolve the boot issue in the Crypto Manager Self Test. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 12 +

[PATCH v3 05/28] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number

To improve readability, sort the IRQ table by IRQ number. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 50 - 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 6e3375f5d3..4862b

[PATCH v3 20/28] hw/misc/aspeed_hace: Add AST2700 support

Introduce a new ast2700 class to support AST2700. Signed-off-by: Jamin Lin Reviewed-by: Andrew Jeffery --- hw/misc/aspeed_hace.c | 20 include/hw/misc/aspeed_hace.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c

[PATCH v3 28/28] docs/specs: add aspeed-intc

Add AST2700 INTC design guidance and its block diagram. Signed-off-by: Jamin Lin --- docs/specs/aspeed-intc.rst | 136 + docs/specs/index.rst | 1 + 2 files changed, 137 insertions(+) create mode 100644 docs/specs/aspeed-intc.rst diff --git a/docs/sp

[PATCH v3 09/28] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices

Refactors the INTC to distinguish between input and output pin indices, improving interrupt handling clarity and accuracy. Updated the functions to handle both input and output pin indices. Added detailed logging for input and output pin indices in trace events. These changes ensure that the INTC

[PATCH v3 03/28] hw/intc/aspeed: Add object type name to trace events for better debugging

Currently, these trace events only refer to INTC. To simplify the INTC model, both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions. However, it is difficult to recognize whether these trace events are comes from INTC or INTCIO. To make these trace events more readable, adds o

[PATCH v3 24/28] tests/functional/aspeed: Introduce start_ast2700_test API and update hwmon path

Added a new method `start_ast2700_test` to the `AST2x00MachineSDK` class and this method centralizes the logic for starting the AST2700 test, making it reusable for different test cases. Modified the hwmon path to use a wildcard to handle different SDK versions: "cat /sys/bus/i2c/devices/1-004d/hw

[PATCH v3 04/28] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0

Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ table and machine name. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 8 hw/arm/aspeed_ast27x0.c | 8 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/

[PATCH v3 23/28] test/functional/aspeed: Introduce new function to fetch assets

This method simplifies the process of fetching and extracting assets from the Aspeed GitHub repository. Signed-off-by: Jamin Lin --- tests/functional/test_aarch64_aspeed.py | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tests/functional/test_aarch64_aspeed.py b/tes

[PATCH v3 08/28] hw/intc/aspeed: Add support for multiple output pins in INTC

Added support for multiple output pins in the INTC controller to accommodate the AST2700 A1. Introduced "num_outpins" to represent the number of output pins. Updated the IRQ handling logic to initialize and connect output pins separately from input pins. Modified the "aspeed_soc_ast2700_realize" f

[PATCH v3 17/28] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1

The design of INTC controllers has significantly changed in AST2700 A1. There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the limitation of interrupt numbers of processors, the interrupts are merged e

[PATCH v3 11/28] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication

The behavior of the INTC set IRQ is almost identical between INTC and INTCIO. To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function to handle both INTC and INTCIO IRQ behavior. Signed-off-by: Jamin Lin --- hw/intc/aspeed_intc.c | 62 -

[PATCH v3 00/28] Support AST2700 A1

v1: 1. Refactor INTC model to support both INTC0 and INTC1. 2. Support AST2700 A1. 3. Create ast2700a0-evb machine. v2: To streamline the review process, split the following patch series into three parts. https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jam

[PATCH v3 14/28] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions

Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to identify the A1 silicon revisions. Signed-off-by: Jamin Lin --- hw/misc/aspeed_scu.c | 2 ++ include/hw/misc/aspeed_scu.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/a

[PATCH v3 19/28] hw/misc/aspeed_hace: Fix coding style

Fix coding style issues from checkpatch.pl. Signed-off-by: Jamin Lin --- hw/misc/aspeed_hace.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index e3f7df2e86..18b85081c7 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/m

[PATCH v3 12/28] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling

This update introduces support for handling multi-output IRQs in the AST2700 interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps 1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a specific IRQ. Implemented "aspeed_intc_set_irq_handler_multi_out

[PATCH v3 02/28] hw/intc/aspeed: Introduce helper functions for enable and status registers

The behavior of the enable and status registers is almost identical between INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds "aspeed_intc_enable_handler" functions to handle enable register write behavior and "aspeed_intc_status_handler" functions to handle status register write be

[PATCH v3 07/28] hw/intc/aspeed: Rename num_ints to num_inpins for clarity

To support AST2700 A1, some registers of the INTC(CPU Die) support one input pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC controller code for better clarity and consistency in naming conventions. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 2 +- h

[PATCH v3 15/28] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700

According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AS

[PATCH v3 06/28] hw/intc/aspeed: Support different memory region ops

The previous implementation set the "aspeed_intc_ops" struct, containing read and write callbacks, to be used when I/O is performed on the INTC region. Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used for INTC (CPU Die). To support the INTCIO (IO Die) model, introduces

[PATCH v3 16/28] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping

Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0. These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197. Updates the interrupt mapping to include support for AST2700 A1 by extending the existing mappings to the new GIC range. Signed-off-by: Jamin Lin --- hw/arm/as

[PATCH v3 01/28] hw/intc/aspeed: Support setting different memory and register size

According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB (0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400) of register space. Introduced a new class attribute "mem_size" to set different memory sizes for the INTC models in AST2700. Introduced a new c

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

On Wed, 12 Feb 2025, Bernhard Beschow wrote: Am 7. Februar 2025 01:12:38 UTC schrieb BALATON Zoltan : On Thu, 6 Feb 2025, Bernhard Beschow wrote: Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan : I had to apply

[PATCH 1/9] target/microblaze: Split out mb_unaligned_access_internal

Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h| 3 +++ target/microblaze/helper.c | 25 - 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/target/microblaze/cpu.h b/target/micro

Re: [PATCH v3 0/7] physmem: teach cpu_memory_rw_debug() to write to more memory regions

Sorry for the delayed engagement, I failed to apply the patch set from the mailing list and had to remember that David had published this change set on GitHub. Tested-by: Stefan Zabka This addresses my initial use case of being able to write to a single MMIO device. I have not set up a scena

[PATCH v3 13/19] hw/virtio/virtio-pci: Assert before registering QOM types

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 15383570c91..ad1d164421d 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2496,6 +24

Re: [PATCH v3 19/19] qom: Require TypeInfo::class_data points to const data

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: All TypeInfo::class_data point to const data. Enforce that in the structure, so future class_data stays in .rodata. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum

On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 17:23, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 14:53, Philippe Mathieu-Daudé wrote: On 12/2/25 13:56, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25

Re: [PATCH] qapi: merge common parts of NbdServerOptions and nbd-server-start data

On Wed, Feb 12, 2025 at 05:33:51PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Instead of comment > "Keep this type consistent with the nbd-server-start arguments", we > can simply merge these things. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > > No problem for me to rebase on top o

[PATCH 4/9] target/microblaze: Use uint64_t for CPUMBState.ear

Use an explicit 64-bit type for EAR. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- target/microblaze/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 45f7f49809..01571d4f86 1006

[PATCH 7/9] target/microblaze: Use TARGET_LONG_BITS == 32 for system mode

Now that the extended address instructions are handled separately from virtual addresses, we can narrow the emulation to 32-bit. Signed-off-by: Richard Henderson --- configs/targets/microblaze-softmmu.mak | 4 +--- configs/targets/microblazeel-softmmu.mak | 4 +--- 2 files changed, 2 insertion

[PATCH 0/9] target/microblaze: Always use TARGET_LONG_BITS == 32

Use out-of-line helpers to implement extended address memory ops. With this, we can reduce TARGET_LONG_BITS to the more natural 32 for this 32-bit cpu. r~ Richard Henderson (9): target/microblaze: Split out mb_unaligned_access_internal target/microblaze: Split out mb_transaction_failed_inte

[PATCH 8/9] target/microblaze: Drop DisasContext.r0

Return a constant 0 from reg_for_read, and a new temporary from reg_for_write. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 24 ++-- 1 file changed, 2 insertions(+), 22 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/transl

Re: [PATCH v3 18/19] hw: Constify various TypeInfo and associated structures

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: Constify various TypeInfo structures. When they are generated from an array, also constify the array. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 12 ++-- hw/rtc/m48t59-isa.c

Re: [PATCH v3 12/19] hw/virtio/virtio-pci: Always allocate QOM type base_name

On 2/12/25 13:32, Philippe Mathieu-Daudé wrote: Introduce 'single_generic_device' boolean for clarity. Allocate base_name on entry. Replace the g_free() call by g_autofree qualifier. Use g_strconcat() instead of g_strdup_printf(). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci

[PATCH 3/9] target/microblaze: Implement extended address load/store out of line

Use helpers and address_space_ld/st instead of inline loads and stores. This allows us to perform operations on physical addresses wider than virtual addresses. Signed-off-by: Richard Henderson --- target/microblaze/helper.h| 16 -- target/microblaze/op_helper.c | 99 +++

[PATCH 9/9] target/microblaze: Simplify compute_ldst_addr_type{a,b}

Require TCGv_i32 and TCGv be identical, so drop the extensions. Return constants when possible instead of a mov into a temporary. Return register inputs unchanged when possible. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 26 +- 1 file changed,

[PATCH 6/9] target/microblaze: Fix printf format in mmu_translate

Use TARGET_FMT_lx to match the target_ulong type of vaddr. Signed-off-by: Richard Henderson --- target/microblaze/mmu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index 2423ac6172..6152fdafd5 100644 --- a/target/microbl

[PATCH 5/9] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea

Use an explicit 64-bit type for extended addresses. Signed-off-by: Richard Henderson --- target/microblaze/translate.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 549013d25e..a1

[PATCH 2/9] target/microblaze: Split out mb_transaction_failed_internal

Use an explicit 64-bit type for the address to store in EAR. Signed-off-by: Richard Henderson --- target/microblaze/op_helper.c | 70 +-- 1 file changed, 42 insertions(+), 28 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c

[PATCH v3 00/19] qom: Constify class_data

Since v2: - Rework virtio_pci_types_register() - Force TypeInfo::class_data to be in .rodata Since v1: - Make XtensaConfigList::config not const (Max) - Update / test rust (Paolo) - Constify InterfaceInfo[] Following Richard's suggestion [*], make QOM class data *const*. [*] https://lore.kernel

[PATCH v3 07/19] target/riscv: Convert misa_mxl_max using GLib macros

Use GLib conversion macros to pass misa_mxl_max as riscv_cpu_class_init() class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cp

[PATCH v3 14/19] hw/virtio/virtio-pci: Do not access base_type_info.name directly

base_type_info.name is initialized to t->base_name, check that directly. Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index ad1d164421d..9512590c936

[PATCH v3 19/19] qom: Require TypeInfo::class_data points to const data

All TypeInfo::class_data point to const data. Enforce that in the structure, so future class_data stays in .rodata. Signed-off-by: Philippe Mathieu-Daudé --- include/qom/object.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/qom/object.h b/include/qom/object.h index

[PATCH v3 04/19] target/sparc: Constify SPARCCPUClass::cpu_def

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/sparc/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index dda811503b5..462bcb6c0e6 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -574,

[PATCH v3 05/19] target/xtensa: Finalize config in xtensa_register_core()

Make XtensaConfigList::config not const. Only modify XtensaConfig within xtensa_register_core(), when the class is registered, not when it is initialized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Acked-by: Max Filippov --- target/xtensa/cpu.h| 2 +- target/xtens

[PATCH v3 18/19] hw: Constify various TypeInfo and associated structures

Constify various TypeInfo structures. When they are generated from an array, also constify the array. Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/net/e1000.c | 12 ++-- hw/rtc/m48t59-isa.c| 22 +++--- hw/rtc/m48t59.c

[PATCH v3 06/19] target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 97713681cbe..fbe5548cf5a 100644 --- a/target/riscv/cpu.h +++

[PATCH v3 15/19] hw/virtio/virtio-pci: Constify base_type_info

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 9512590c936..a33d1b2cbcf 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -24

[PATCH v3 10/19] qom: Constify TypeInfo::class_data

All callers now correctly expect a const class data. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qom/object.h| 2 +- hw/arm/armsse.c | 2 +- hw/block/m25p80.c

[PATCH v3 02/19] hw: Make class data 'const'

When the %data argument is not modified, we can declare it const. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/sd/sdhci-internal.h | 2 +- hw/sd/sdhci.c| 2 +- hw/sensor/emc141x.c | 2 +- hw/sensor/isl_pmbus_vr.c | 2 +- 4 files changed, 4 inser

[PATCH v3 17/19] hw/virtio/virtio-pci: Reduce generic_type_info scope

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 6f0e1772669..99724deb3d9 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virti

[PATCH v3 01/19] hw: Declare various const data as 'const'

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/isa/vt82c686.c | 2 +- hw/rtc/m48t59-isa.c | 2 +- hw/rtc/m48t59.c | 2 +- hw/sensor/tmp421.c| 2 +- hw/usb/hcd-ehci-pci.c | 2 +- hw/usb/hcd-uhci.c | 2 +- 6 files changed, 6 insertions(+), 6 deletio

[PATCH v3 12/19] hw/virtio/virtio-pci: Always allocate QOM type base_name

Introduce 'single_generic_device' boolean for clarity. Allocate base_name on entry. Replace the g_free() call by g_autofree qualifier. Use g_strconcat() instead of g_strdup_printf(). Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 11 ++- 1 file changed, 6 insertions(+

Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 06:03:30PM +, Daniel P. Berrangé wrote: > On Wed, Feb 12, 2025 at 12:56:46PM -0500, Peter Xu wrote: > > On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote: > > > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > > > > From: Daniil Tatianin > >

[PATCH v3 16/19] hw/virtio/virtio-pci: Constify generic_type_info

Signed-off-by: Philippe Mathieu-Daudé --- hw/virtio/virtio-pci.c | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index a33d1b2cbcf..6f0e1772669 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@

[PATCH v3 03/19] target/i386: Constify X86CPUModel uses

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.h | 2 +- target/i386/cpu.c | 8 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c67b42d34fc..f9ce6970ee1 100644 --- a/target/i386/cpu.h ++

[PATCH v3 11/19] qom: Constify InterfaceInfo[] interfaces

Mechanical change using gsed. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/virtio/virtio-pci.h | 2 +- include/qom/object.h| 4 ++-- authz/list.c| 2 +- authz/l

[PATCH v3 08/19] qom: Have class_base_init() take a const data argument

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/qom/object.h | 2 +- hw/core/machine.c| 2 +- hw/core/qdev.c | 2 +- hw/pci/pci.c | 2 +- qom/object.c | 2 +- rust/qemu-api/src/qom.rs | 2 +- 6 files changed, 6 insert

Re: [PATCH v3 09/23] hw/uefi: add var-service-core.c

On 12.02.25 16:18, Gerd Hoffmann wrote: Hi, Yes. Knowing both physical and virtual address works only for memory you allocated yourself before ExitBootServices. So you can't pass on pointers from the OS, you have to copy the data to a buffer where you know the physical address instead.

Re: [PATCH 09/11] rust/block: Add read support for block drivers

Am 12.02.2025 um 16:05 hat Paolo Bonzini geschrieben: > On 2/11/25 22:43, Kevin Wolf wrote: > > +/// A request to a block driver > > +pub enum Request { > > +Read { offset: u64, len: u64 }, > > +} > > + > > Maybe add flags already? > > +#[allow(dead_code)] > > +pub enum MappingTarget { > > +

Re: [PATCH] hw/ppc/e500: Partial implementation of local access window registers

Am 7. Februar 2025 01:12:38 UTC schrieb BALATON Zoltan : >On Thu, 6 Feb 2025, Bernhard Beschow wrote: >> Am 2. Februar 2025 01:25:22 UTC schrieb BALATON Zoltan : >>> On Sat, 1 Feb 2025, Bernhard Beschow wrote: Am 1. Februar 2025 14:55:15 UTC schrieb Bernhard Beschow : > Am 30. Jan

Adding new block device filter for Zerto based replication

Hello members of QEMU dev, My name is Gil, I'm an architect at Zerto (now part of HPE). Currently Zerto support block device replication, with 5 seconds RPO and RTO of minutes, for the VmWare and HyperV platforms. We would like to support also QEMU based hypervisors. For that, we need to creat

Re: [PATCH] vdpa: Allow vDPA to work on big-endian machine

On 2/12/2025 12:07, Philippe Mathieu-Daudé wrote: On 12/2/25 18:24, Konstantin Shkolnyy wrote: On 2/12/2025 08:52, Philippe Mathieu-Daudé wrote: On 11/2/25 17:19, Konstantin Shkolnyy wrote: Add .set_vnet_le() function that always returns success, assuming that vDPA h/w always implements LE dat

Re: [PATCH 03/11] rust: Add some block layer bindings

Am 12.02.2025 um 18:16 hat Paolo Bonzini geschrieben: > On 2/12/25 16:13, Kevin Wolf wrote: > > Or if you have to define the constants anyway - you currently do this > > only for Windows, but for into_negative_errno() you might need it on > > Linux, too - and it wouldn't be a problem for the consta

Re: [PULL 00/32] Misc HW patches for 2025-02-10

On 12/02/2025 05.45, Eldon Stegall wrote: On Wed, Feb 12, 2025 at 02:39:16AM +0100, Thomas Huth wrote: On 12/02/2025 01.41, Thomas Huth wrote: On 11/02/2025 20.03, Philippe Mathieu-Daudé wrote: On 11/2/25 19:53, Philippe Mathieu-Daudé wrote: On 11/2/25 19:48, Philippe Mathieu-Daudé wrote: [.

Re: [PULL 05/12] vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()

11.02.2025 17:33, Cédric Le Goater wrote: From: Zhenzhong Duan When iommufd_cdev_ram_block_discard_disable() fails for whatever reason, errp should be set or else SIGSEV is triggered in vfio_realize() when error_prepend() is called. By this chance, use the same error message for both legacy an

Re: [PATCH v2 8/8] hw/cpu/arm_mpcore: Remove default values for GIC external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: Implicit default values are often hard to figure out, better be explicit. Now that all boards explicitly set the number of GIC external IRQs, remove the default values (displaying an error message if it is out of range). Signed-off-by: Philippe Mat

Re: [PATCH v2 4/8] hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: We already have a definition to distinct GIC internal IRQs versus external ones, use it. No logical changes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 34 -- 1 fil

Re: [PATCH v2 7/8] hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num

Re: [PATCH 09/11] accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page

On 2/11/25 23:22, Philippe Mathieu-Daudé wrote: On 5/2/25 05:03, Richard Henderson wrote: The declarations use vaddr for size. Which seems dubious, since TARGET_PAGE_SIZE is int IIUC. This parameter must handle guest huge pages. Most often this is 2MiB or 1GiB, which do fit in "int", but l

Re: [PATCH 08/11] rust/block: Add driver module

Il mer 12 feb 2025, 18:32 Kevin Wolf ha scritto: > > > +mut buf: MaybeUninit, > > > > I think Rust doesn't guarantee no copies here, so maybe this could be > > Do you think that in practice the compiler won't optimise the copy away? > It's possiblr that it does not, because it has to bui

Re: [PATCH v6 01/11] hw/qdev-properties-system: Introduce EndianMode QAPI enum

On 12/2/25 17:23, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 14:53, Philippe Mathieu-Daudé wrote: On 12/2/25 13:56, BALATON Zoltan wrote: On Wed, 12 Feb 2025, Philippe Mathieu-Daudé wrote: On 12/2/25 12:37, Thomas Huth wrote: On 12/02/2025 12.24, Phil

Re: [PATCH v2 6/8] hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: When not specified, Cortex-A9MP configures its GIC with 64 external IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"), and Cortex-15MP to 128 (see commit 528622421eb "hw/cpu/a15mpcore: Correct default value for num

Re: [PATCH v2] vdpa: Fix endian bugs in shadow virtqueue

On 12/2/25 17:49, Konstantin Shkolnyy wrote: VDPA didn't work on a big-endian machine due to missing/incorrect CPU<->LE data format conversions. Signed-off-by: Konstantin Shkolnyy --- Changes in v2: Change desc_next[] from LE format to "CPU". hw/virtio/vhost-shadow-virtqueue.c | 18 +

Re: [PATCH v2 5/8] hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14) on Appendix A: Register Details, the mpcore Interrupt Controller Type Register (ICDICTR) has the IT_Lines_Number field read-only with value 0x2, described as: IT_Lines_Number

Re: [PATCH] vdpa: Allow vDPA to work on big-endian machine

On 12/2/25 18:24, Konstantin Shkolnyy wrote: On 2/12/2025 08:52, Philippe Mathieu-Daudé wrote: On 11/2/25 17:19, Konstantin Shkolnyy wrote: Add .set_vnet_le() function that always returns success, assuming that vDPA h/w always implements LE data format. Otherwise, QEMU disables vDPA and outpu

Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 12:56:46PM -0500, Peter Xu wrote: > On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote: > > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > > > From: Daniil Tatianin > > > > > > This will be used in the following commits to make it possible to o

Re: [PATCH v2 3/8] hw/arm/realview: Specify explicitly the GIC has 64 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly settin

Re: [PATCH v2 2/8] hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: When not specified, Cortex-A9MP configures its GIC with 64 external IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts configurable"). Add the GIC_EXT_IRQS definition (with a comment) to make that explicit. Except explicitly settin

Re: [PATCH v2 1/8] hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition

On 2/12/25 07:43, Philippe Mathieu-Daudé wrote: The 32 IRQ lines skipped are the GIC internal ones. Use the GIC_INTERNAL definition for clarity. No logical change. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) Revie

Re: [PULL v2 11/14] os: add an ability to lock memory on_fault

On Wed, Feb 12, 2025 at 05:48:46PM +, Daniel P. Berrangé wrote: > On Wed, Feb 12, 2025 at 12:38:23PM -0500, Peter Xu wrote: > > From: Daniil Tatianin > > > > This will be used in the following commits to make it possible to only > > lock memory on fault instead of right away. > > > > Signed-

Re: [PATCH] linux-user: Move TARGET_SA_RESTORER out of generic/signal.h

Hi Andreas, On 2025-02-10 13:59:34+0100, Andreas Schwab wrote: > SA_RESTORER and the associated sa_restorer field of struct sigaction are > an obsolete feature, not expected to be used by future architectures. > They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but > defined due to

Re: [PATCH 5/5] target/i386: Mark WHPX APIC region as little-endian

On 2/12/25 03:39, Philippe Mathieu-Daudé wrote: This device is only used by the x86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTL

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