On 29/01/2025 08.18, Cédric Le Goater wrote:
The OpenBMC images currently used by QEMU to test the Aspeed machines
are rather old. To prepare an update to the latest builds, we need to
adjust the console patterns. Introduce a new routine to preserve the
current tests.
Signed-off-by: Cédric Le Go
Hi,
On 1/28/25 10:28 PM, Matt Ochs wrote:
>> On Jan 28, 2025, at 11:52 AM, Eric Auger wrote:
>>
>> Hi Matthew, Shameer,
>>
>> On 1/28/25 6:36 PM, Shameerali Kolothum Thodi wrote:
-Original Message-
From: Matthew R. Ochs
Sent: Tuesday, January 28, 2025 4:03 PM
To: qem
On 28/1/25 11:45, Peter Maydell wrote:
The SDCardClass has an 'enable' method, but nothing actually invokes it.
The underlying implementation is sd_enable(), which is documented
in sdcard_legacy.h as something that should not be used and was only
present for the benefit of the now-removed nseries
Use do_test_arm_aspeed_openbmc() routine to run the latest OpenBMC
firmware build of the witherspoon BMC.
Signed-off-by: Cédric Le Goater
---
tests/functional/meson.build | 2 ++
.../functional/test_arm_aspeed_witherspoon.py | 24 +++
2 files changed, 26 inserti
On 1/29/25 00:29, Andrew Jeffery wrote:
Hi Cédric,
On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote:
Hello,
This series updates the OpenBMC firmware images to the latest version
for existing tests and also adds 2 new tests for Aspeed machines
which
were not tested before : witherspoon
Hello,
This series updates the OpenBMC firmware images to the latest version
for existing tests and also adds 2 new tests for Aspeed machines which
were not tested before : witherspoon and bletchley.
Thanks,
C.
Cédric Le Goater (5):
tests/functional: Introduce a new test routine for OpenBMC i
Use do_test_arm_aspeed_openbmc() to run the latest OpenBMC firmware
build of the bletchley BMC.
Signed-off-by: Cédric Le Goater
---
tests/functional/meson.build | 2 ++
tests/functional/test_arm_aspeed_bletchley.py | 24 +++
2 files changed, 26 insertions(+)
cr
The OpenBMC images currently used by QEMU to test the Aspeed machines
are rather old. To prepare an update to the latest builds, we need to
adjust the console patterns. Introduce a new routine to preserve the
current tests.
Signed-off-by: Cédric Le Goater
---
tests/functional/aspeed.py | 18
Use the new do_test_arm_aspeed_openbmc() routine to run the latest
OpenBMC firmware build of the palmetto BMC.
Signed-off-by: Cédric Le Goater
---
tests/functional/test_arm_aspeed_palmetto.py | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/test_a
Use the new do_test_arm_aspeed_openbmc() routine to run the latest
OpenBMC firmware build of the romulus BMC. Remove the older routine
which is now unused.
Signed-off-by: Cédric Le Goater
---
tests/functional/aspeed.py | 16
tests/functional/test_arm_aspeed_romu
Hi Thomas,
On 17/1/25 20:21, Thomas Huth wrote:
QEMU currently crashes when you try to inspect the machines based on
TYPE_PC_MACHINE for their properties:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "
On 17/01/2025 20.21, Thomas Huth wrote:
QEMU currently crashes when you try to inspect the machines based on
TYPE_PC_MACHINE for their properties:
$ echo '{ "execute": "qmp_capabilities" }
{ "execute": "qom-list-properties","arguments":
{ "typename": "pc-q35-10
On 28/01/2025 11.02, Philippe Mathieu-Daudé wrote:
On 28/1/25 11:01, Philippe Mathieu-Daudé wrote:
On 28/1/25 10:27, Daniel P. Berrangé wrote:
On Tue, Jan 28, 2025 at 10:17:33AM +0100, Philippe Mathieu-Daudé wrote:
On 28/1/25 10:02, Alex Bennée wrote:
Thomas Huth writes:
On 28/01/2025 01.4
VM firmware update is a mechanism where the virtual machines can use their
preferred and trusted firmware image in their execution environment without
having to depend on a untrusted party to provide the firmware bundle. This is
particularly useful for confidential virtual machines that are deploye
On 28/01/2025 19.57, David Hildenbrand wrote:
Let's do it similar as virtio-balloon-pci. With this change, we can
use virtio-mem-pci on s390x, although plugging will still fail until
properly wired up in the machine.
No need to worry about transitional/non_transitional devices, because they
don'
Em Tue, 28 Jan 2025 12:29:51 +0100
Mauro Carvalho Chehab escreveu:
> Em Fri, 24 Jan 2025 11:23:46 +0100
> Igor Mammedov escreveu:
>
> > On Wed, 22 Jan 2025 16:46:22 +0100
> > Mauro Carvalho Chehab wrote:
> >
> > > Create a new property (x-has-hest-addr) and use it to detect if
> > > the GHE
On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
In order to move TCG specific code dependent on powerpc_excp()
in the next commit, expose its prototype in "internal.h".
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Harsh Prateek Bora
---
target/ppc/internal.h| 1 +
target/pp
On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
Move helper_attn(), helper_scv() and helper_pminsn() to
tcg-excp_helper.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 45
target/ppc/tcg-
On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
Fix style in do_rfi() before moving the code around.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/ppc/exc
On 1/27/25 15:56, Philippe Mathieu-Daudé wrote:
Move helpers common to system/user emulation to tcg-excp_helper.c.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/excp_helper.c | 141 --
target/ppc/tcg-excp_helper.c | 143 ++
On 2025/01/28 22:54, Philippe Mathieu-Daudé wrote:
GICv3 isn't supported on aarch64/HVF, but GICv2 is.
Commit bdb0ade663c7 ("tests/migration-test: Stick with gicv3 in aarch64
test"), which set gic-version=3, says:
> Switch to a static gic version "3" rather than using version "max",
> so that
On 1/28/25 20:07, Helge Deller wrote:
What I'm not sure about is gva_offset_mask in those hunks and where you
said I can't read from env:
...
@@ -4635,6 +4641,7 @@ static void hppa_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->tb_flags = ctx->base.tb->flags;
ct
On 2025/01/28 23:48, Peter Maydell wrote:
On Sat, 4 Jan 2025 at 07:10, Akihiko Odaki wrote:
kvm-steal-time and sve properties are added for KVM even if the
corresponding features are not available. Always add pmu property for
Armv7+. Note that the property is added only for Armv7-A/R+ as QEMU
On 2025/01/28 20:18, Philippe Mathieu-Daudé wrote:
Since commit b14a0b7469f ("accel: Use QOM classes for accel types")
accelerators are registered as QOM objects. Use QOM as a generic
API to query for available accelerators. This is in particular
useful to query hardware accelerators such HFV, Xe
* Richard Henderson :
> On 1/28/25 17:52, Richard Henderson wrote:
> > On 1/28/25 14:45, del...@kernel.org wrote:
> > > + if (ctx->is_pa20 && (a->dr == 2)) {
> > > + /* Exit TB to recalculate gva_offset_mask on %dr2 */
> > > + ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
> > > + }
On Wed, Jan 15, 2025 at 5:04 AM Daniel Henrique Barboza
wrote:
>
> From the time we added RVA22U64 until now the spec didn't declare 'RVB'
> as a dependency, using zba/zbb/zbs instead. Since then the RVA22 spec
> [1] added the following in the 'RVA22U64 Mandatory Extensions' section:
>
> "B Bit-ma
On 1/28/25 17:52, Richard Henderson wrote:
On 1/28/25 14:45, del...@kernel.org wrote:
+ if (ctx->is_pa20 && (a->dr == 2)) {
+ /* Exit TB to recalculate gva_offset_mask on %dr2 */
+ ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
+ }
Where does this update happen? I think you've
Replace with fp_status[FPST_AH_F16].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 2 +-
target/arm/vfp_helper.c | 10 +-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 18afff850
On 1/28/25 14:45, del...@kernel.org wrote:
+if (ctx->is_pa20 && (a->dr == 2)) {
+/* Exit TB to recalculate gva_offset_mask on %dr2 */
+ctx->base.is_jmp = DISAS_IAQ_N_STALE_EXIT;
+}
Where does this update happen? I think you've missed that step.
r~
On Wed, Jan 15, 2025 at 1:52 PM Huang Borong wrote:
>
> Remove the redundant masking of "hart_idx", as the same operation is
> performed later during address calculation.
>
> This change impacts the "hart_idx" value in the final qemu_log_mask()
> call. The original "hart_idx" parameter should be u
On 1/28/25 14:45, del...@kernel.org wrote:
@@ -4635,6 +4640,7 @@ static void hppa_tr_init_disas_context(DisasContextBase
*dcbase, CPUState *cs)
ctx->tb_flags = ctx->base.tb->flags;
ctx->is_pa20 = hppa_is_pa20(cpu_env(cs));
ctx->psw_xb = ctx->tb_flags & (PSW_X | PSW_B);
+ctx
Replace with fp_status[FPST_AH].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 3 +--
target/arm/cpu.c| 6 +++---
target/arm/vfp_helper.c | 6 +++---
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 0f7d5d5430..5e3d
On Wed, Jan 22, 2025 at 3:07 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this new version, in patch 2, we're using the address 'size' val from
> riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN.
>
> No other changes made. Patches based on master.
>
> Changes from v2:
> - patch 2
On Wed, Jan 22, 2025 at 3:08 AM Daniel Henrique Barboza
wrote:
>
> In the RISC-V privileged ISA section 3.1.15 table 15, it is determined
> that a debug exception that is triggered from a load/store has a higher
> priority than a possible fault that this access might trigger.
>
> This is not the c
On 1/28/25 14:45, del...@kernel.org wrote:
From: Helge Deller
Turn on space register hashing for 64-bit CPUs when reset.
Signed-off-by: Helge Deller
---
target/hppa/cpu.c | 5 +
1 file changed, 5 insertions(+)
Reviewed-by: Richard Henderson
r~
On 1/28/25 14:45, del...@kernel.org wrote:
From: Helge Deller
Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag
instructions which modify the diagnose registers.
diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in
commit 3bdf20819e68 based on some analysis of ODE
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 8 +--
target/arm/tcg/translate-a64.c | 78 +--
target/arm/tcg/translate-sme.c | 4 +-
target/arm/tcg/translate-sve.c | 98 +-
4 files changed, 94 insertions(+), 94 dele
Add versions of float*_ah_chs which takes fpcr_ah.
These will help simplify some usages.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h
index a67
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 14 +++---
target/arm/tcg/translate-a64.c | 8
target/arm/tcg/translate-sve.c | 8
3 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/transla
Pass ARMFPStatusFlavour index instead of fp_status[FOO].
Signed-off-by: Richard Henderson
---
target/arm/vfp_helper.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
index a2775a2e8d..4e242275e7 100644
--- a/target/
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 6 +++---
target/arm/tcg/translate-vfp.c | 24
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 2edb707b85..adf6eb8b91 1006
Replace with fp_status[FPST_STD].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 -
target/arm/cpu.c| 8
target/arm/tcg/mve_helper.c | 28 ++--
target/arm/tcg/vec_helper.c | 4 ++--
target/arm/vfp_helper.c | 4 ++--
5 fil
Signed-off-by: Richard Henderson
---
target/arm/tcg/sve_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index 3f38e07829..a2ff3b7f11 100644
--- a/target/arm/tcg/sve_helper.c
+++ b/target/arm/tcg/sv
Split negation cases out of gvec_fmla, creating 6 new helpers.
We no longer pass 'neg' as a bit in simd_data.
Handle FPCR.AH=0 via xor and FPCR.AH=1 via muladd flags.
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 14 ++
target/arm/tcg/translate-a64.c | 17 +++
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/vec_helper.c| 66 --
2 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 715760a17b..3
Replace with fp_status[FPST_STD_F16].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 -
target/arm/cpu.c| 4 ++--
target/arm/tcg/mve_helper.c | 24
target/arm/vfp_helper.c | 8
4 files changed, 18 insertions(+), 19 deleti
Replace with fp_status[FPST_A32_F16].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 -
target/arm/cpu.c| 2 +-
target/arm/tcg/vec_helper.c | 4 ++--
target/arm/vfp_helper.c | 14 +++---
4 files changed, 10 insertions(+), 11 deletions(-)
diff --g
On 1/28/25 14:45, del...@kernel.org wrote:
From: Helge Deller
Add the diagnose registers (%dr) to the CPUArchState. Those are mostly
undocumented and control cache behaviour, memory behaviour, reset button
management and many other related internal CPU things.
Signed-off-by: Helge Deller
---
Replace with fp_status[FPST_A64_F16].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 -
target/arm/cpu.c| 2 +-
target/arm/tcg/sme_helper.c | 2 +-
target/arm/tcg/vec_helper.c | 8
target/arm/vfp_helper.c | 16
5 files changed,
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 2 +-
target/arm/tcg/vec_helper.c| 44 --
2 files changed, 27 insertions(+), 19 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 3748f7d145..9
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 8 ++---
target/arm/tcg/translate-a64.c | 44 +++
target/arm/tcg/translate-sve.c | 66 +-
3 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/target/arm/tcg/tran
Replace with fp_status[FPST_A32]. As this was the last of the
old structures, we can remove the anonymous union and struct.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 7 +--
target/arm/cpu.c| 2 +-
target/arm/vfp_helper.c | 18 +-
3 files change
The float*_muladd functions have a flags argument that can
perform optional negation of various operand. We don't use
that for "normal" arm fmla, because the muladd flags are not
applied when an input is a NaN. But since FEAT_AFP does not
negate NaNs, this behaviour is exactly what we need.
Sinc
Select on index instead of pointer.
No functional change.
Signed-off-by: Richard Henderson
---
target/arm/tcg/mve_helper.c | 40 +
1 file changed, 14 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c
index 3
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 71 -
1 file changed, 46 insertions(+), 25 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index b3ed6533bb..9b14885ef2 100644
--- a/target/arm/tcg/vec_helpe
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index c716bd774a..bae98a34b8 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tc
On Wed, Jan 22, 2025 at 3:07 AM Daniel Henrique Barboza
wrote:
>
> The mcontrol select bit (19) is always zero, meaning our triggers will
> always match virtual addresses. In this condition, if the user does not
> specify a size for the trigger, the access size defaults to XLEN.
>
> At this moment
Hi Peter,
I know you've sent a PR with some of this, but I don't have a
complete tree against which to rebase. So this is still
Based-on: 20250124162836.2332150-1-peter.mayd...@linaro.org
("[PATCH 00/76] target/arm: Implement FEAT_AFP and FEAT_RPRES")
Up to patch 22 is unchanged; after patch 22
Because the operand is known to be negative, negating the operand
is the same as taking the absolute value. Defer this to the muladd
operation via flags, so that it happens after NaN detection, which
is correct for FPCR.AH.
Signed-off-by: Richard Henderson
---
target/arm/tcg/sve_helper.c | 27 +
The float_muladd_negate_product flag produces the same result
as negating either of the multiplication operands, assuming
neither of the operands are NaNs. But since FEAT_AFP does not
negate NaNs, this behaviour is exactly what we need.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_he
Signed-off-by: Richard Henderson
---
target/arm/tcg/sve_helper.c| 69 +-
target/arm/tcg/translate-sve.c | 2 +-
2 files changed, 43 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c
index c12b2600bd..c206ca6
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
index 9b14885ef2..c716bd774a 100644
--- a/target/arm/tcg/vec_helper.c
+++ b/target/arm/tc
Replace with fp_status[FPST_A64].
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 -
target/arm/cpu.c| 2 +-
target/arm/tcg/sme_helper.c | 2 +-
target/arm/tcg/vec_helper.c | 10 +-
target/arm/vfp_helper.c | 16
5 files changed, 15
Read the bit from the source, rather than from the proxy via
get_flush_inputs_to_zero. This makes it clear that it does
not matter which of the float_status structures is used.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_internal.h | 20
target/arm/tcg/helper-a64.c | 15 +--
2 files changed, 21 insertions(+), 14 deletions(-)
diff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h
index 094f5c169c..a67393
Sink common code from the callers into do_fmlal
and do_fmlal_idx. Reorder the arguments to minimize
the re-sorting from the caller's arguments.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 28
1 file changed, 16 insertions(+), 12 deletions(-)
Move ARMFPStatusFlavour to cpu.h with which to index
this array. For now, place the array in an anonymous
union with the existing structures. Adjust the order
of the existing structures to match the enum.
Simplify fpstatus_ptr() using the new array.
Signed-off-by: Richard Henderson
---
target
The construction of neg_imag and neg_real were done to make it easy
to apply both in parallel with two simple logical operations. This
changed with FPCR.AH, which is more complex than that.
Note that there was a naming issue with neg_imag and neg_real.
They were named backward, with neg_imag bein
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 6 ++--
target/arm/tcg/translate-vfp.c | 54 +-
2 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index 59e780df2e..6ce2471
This reverts commit c5eb0b62e603c1d391ee2199108f0eb34aadc8f5.
---
target/arm/tcg/translate-a64.c | 4 ++--
target/arm/tcg/vec_helper.c| 28
2 files changed, 6 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a6
The construction of neg_imag and neg_real were done to make it easy
to apply both in parallel with two simple logical operations. This
changed with FPCR.AH, which is more complex than that.
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 51 +++
On Fri, Jan 24, 2025 at 7:06 PM Max Chou wrote:
>
> In prop_vlen_set function, there is an incorrect comparison between
> vlen(bit) and vlenb(byte).
> This will cause unexpected error when user applies the `vlen=1024` cpu
> option with a vendor predefined cpu type that the default vlen is
> 1024(v
On Fri, Jan 24, 2025 at 8:16 PM Max Chou wrote:
>
> According to the Vector Reduction Operations section in the RISC-V "V"
> Vector Extension spec,
> "If vl=0, no operation is performed and the destination register is not
> updated."
>
> The vd should be updated when vl is larger than 0.
>
> Signe
On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev
wrote:
>
> A behavior of misa.v must be similar as misa.f.
> So when this bit's field is turned off, mstatus.vs must be turned off
> too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
> "Machine ISA (misa) Register".
>
> Signed-
On Tue, Jan 14, 2025 at 7:33 PM Evgenii Prokopiev
wrote:
>
> A behavior of misa.v must be similar as misa.f.
> So when this bit's field is turned off, mstatus.vs must be turned off
> too. It follows from the privileged manual of RISC-V, paragraph 3.1.1.
> "Machine ISA (misa) Register".
>
> Signed-
On Wed, Jan 15, 2025 at 5:02 AM Daniel Henrique Barboza
wrote:
>
> Add RVA23U64 as described in [1]. Add it as a child of RVA22U64 since
> all RVA22U64 mandatory extensions are also present in RVA23U64. What's
> left then is to list the mandatory extensions that are RVA23 only.
>
> A new "rva23u64
On Sun, Jan 26, 2025 at 12:14 PM Dmitry Osipenko <
dmitry.osipe...@collabora.com> wrote:
> From: Alex Bennée
>
> This attempts to tidy up the VirtIO GPU documentation to make the list
> of requirements clearer. There are still a lot of moving parts and the
> distros have some catching up to do be
> On Jan 22, 2025, at 23:07, Jonathan Cameron
> wrote:
>
> On Fri, 17 Jan 2025 09:43:11 +
> Jonathan Cameron via wrote:
>
>> On Fri, 17 Jan 2025 10:13:41 +0900
>> Itaru Kitayama wrote:
>>
On Jan 16, 2025, at 19:58, Jonathan Cameron
wrote:
On Thu, 16 Jan 2025 15:
On Wed, Jan 22, 2025 at 4:50 AM Daniel Henrique Barboza
wrote:
>
> Coverity found a second DEADCODE issue in rmw_xireg() claiming that we can't
> reach 'RISCV_EXCP_NONE' at the 'done' label:
>
> > 2706 done:
> > 2707 if (ret) {
> > 2708 return (env->virt_enabled && virt)
On Wed, Jan 15, 2025 at 5:04 AM Daniel Henrique Barboza
wrote:
>
> ssu64xl is defined in RVA22 as:
>
> "sstatus.UXL must be capable of holding the value 2 (i.e., UXLEN=64 must
> be supported)."
>
> This is always true in TCG and it's mandatory for RVA23, so claim
> support for it.
>
> Signed-off-b
On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This series contains Coverity fixes for issues found in the latest
> RISC-V pull made yesterday.
>
> Coverity CIDs being resolved: 1590355, 1590356, 1590357, 1590358 and
> 1590359.
>
> Patches based on master.
>
>
> Daniel
On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza
wrote:
>
> Coverity reported a BAD_SHIFT issue in the following code:
>
> > 2097
> CID 1590355: Integer handling issues (BAD_SHIFT)
> In expression "hdeleg >> cause", right shifting by more than 63
>bits has u
On Wed, Jan 22, 2025 at 4:53 AM Daniel Henrique Barboza
wrote:
>
> Coverity reported a DEADCODE ticket in this function, as follows:
>
> CID 1590358: Control flow issues (DEADCODE)
> Execution cannot reach this statement: "return ret;".
> > 380 return ret;
> >
On Wed, Jan 22, 2025 at 4:49 AM Daniel Henrique Barboza
wrote:
>
> Coverity found a DEADCODE issue in rmw_xiregi() claiming that we can't
> reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
>
> > 2652 done:
> CID 1590357: Control flow issues (DEADCODE)
> E
On Wed, Jan 22, 2025 at 4:52 AM Daniel Henrique Barboza
wrote:
>
> Coverity found a DEADCODE issue in rmw_xireg() claiming that we can't
> reach 'RISCV_EXCP_VIRT_INSTRUCTION_FAULT' at the 'done' label:
>
> done:
> if (ret) {
> return (env->virt_enabled && virt) ?
>RISCV
On Thu, Jan 16, 2025 at 10:51 AM Atish Patra wrote:
>
> As per the ISA definition, the upper 8 bits in hpmevent are defined
> by Sscofpmf for privilege mode filtering and overflow bits while the
> lower 56 bits are desginated for platform specific hpmevent values.
> For the reset case, mhpmevent v
On Thu, Jan 16, 2025 at 10:51 AM Atish Patra wrote:
>
> As per the latest privilege specification v1.13[1], the sscofpmf
> only reserves first 8 bits of hpmeventX. Update the corresponding
> masks accordingly.
>
> [1]https://github.com/riscv/riscv-isa-manual/issues/1578
>
> Signed-off-by: Atish Pa
Hi Cédric,
On Tue, 2025-01-28 at 22:41 +0100, Cédric Le Goater wrote:
> Hello,
>
> This series updates the OpenBMC firmware images to the latest version
> for existing tests and also adds 2 new tests for Aspeed machines
> which
> were not tested before : witherspoon and bletchley.
>
> Thanks,
>
This series of 4 patches incorporates the changes as suggested by
Richard regarding PATCH #3 from my previous series.
Please review.
Helge
From: Helge Deller
Add the diagnose registers (%dr) to the CPUArchState. Those are mostly
undocumented and control cache behaviour, memory behaviour, reset button
management and many other related internal CPU things.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 1 +
target/hppa/mac
From: Helge Deller
Turn on space register hashing for 64-bit CPUs when reset.
Signed-off-by: Helge Deller
---
target/hppa/cpu.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index b0bc9d35e4..c86f9190d2 100644
--- a/target/hppa/cpu.c
+++ b/targe
From: Helge Deller
The Linux kernel turns space-register hashing off unconditionally at
bootup. That code was provided by HP at the beginning of the PA-RISC
Linux porting effort, and I don't know why it was decided then why Linux
should not use space register hashing.
32-bit HP-UX versions seem
From: Helge Deller
Add 32- and 64-bit instruction decoding of the mfdiag and mtdiag
instructions which modify the diagnose registers.
diag_getshadowregs_pa2() and diag_putshadowregs_pa2() were added in
commit 3bdf20819e68 based on some analysis of ODE code, but now they
conflict with the generic
Am 28. Januar 2025 10:34:23 UTC schrieb Peter Maydell
:
>On Mon, 27 Jan 2025 at 23:11, Bernhard Beschow wrote:
>>
>>
>>
>> Am 27. Januar 2025 13:24:46 UTC schrieb Peter Maydell
>> :
>> >On Sat, 11 Jan 2025 at 18:37, Bernhard Beschow wrote:
>> >>
>> >> Commit ce5dd27534b0 "hw/sd: Remove omap2
Am 21. Januar 2025 03:07:39 UTC schrieb BALATON Zoltan :
>On Mon, 20 Jan 2025, Bernhard Beschow wrote:
>> Xilinx QEMU implements a TCA6416 device model which may be useful for the
>> broader QEMU community, so upstream it. In the Xilinx fork, the device model
>> gets compiled whenever CONFIG_CAD
Am 28. Januar 2025 14:29:53 UTC schrieb Peter Maydell
:
>On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
>>
>> As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
>> serial. All other devices of the A53 memory map are represented as
>> TYPE_UNIMPLEMENTED_DEVICE,
Am 28. Januar 2025 14:33:14 UTC schrieb Peter Maydell
:
>On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
>>
>> Linux checks for the PLLs in the PHY to be locked, so implement a model
>> emulating that.
>>
>> Signed-off-by: Bernhard Beschow
>
>> diff --git a/docs/system/arm/imx8mp-evk.rs
Am 28. Januar 2025 14:35:14 UTC schrieb Peter Maydell
:
>On Mon, 20 Jan 2025 at 20:38, Bernhard Beschow wrote:
>>
>> Fixes quite a few stack traces during the Linux boot process. Also provides
>> the
>> clocks for devices added later, e.g. enet1.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
Thomas Huth writes:
> There were recently some crashes that occurred when trying to
> retrieve the properties of machines. Let's add a test to avoid
> regression here.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Fabiano Rosas
Am 28. Januar 2025 15:10:18 UTC schrieb "Philippe Mathieu-Daudé"
:
>On 28/1/25 13:57, BALATON Zoltan wrote:
>> On Tue, 28 Jan 2025, Peter Maydell wrote:
>>> On Tue, 28 Jan 2025 at 10:42, Gerd Hoffmann wrote:
On Sat, Jan 25, 2025 at 07:13:34PM +0100, Philippe Mathieu-Daudé wrote:
>>>
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