> > > -const INSTANCE_INIT: Option
> > > = Some(pl011_init);
> > > +const INSTANCE_INIT: Option = Some(Self::init);
> >
> > No need to keep `unsafe` here?
>
> Right now instance_init is called with only the parent initialized, and the
> remaining memory zeroed; its purpose is to prepare
On 10/12/2024 21.43, Alex Bennée wrote:
Now we have virtio-gpu Vulkan support lets add a test for it.
Currently this is using images build by buildroot:
https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html
Signed-off-by: Alex Bennée
---
tests/functional/test_aarch64_v
From: Jamin Lin
Add test_ast2700_evb function and reused testcases which are from
aspeed_smc-test.c for AST2700 testing. The base address, flash base address
and ce index of fmc_cs0 are 0x1400, 0x1 and 0, respectively.
The default flash model of fmc_cs0 is "w25q01jvq" whose size is 12
The following changes since commit ae35f033b874c627d81d51070187fbf55f0bf1a7:
Update version for v9.2.0 release (2024-12-10 16:20:54 +)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspeed-20241211
for you to fetch changes up to 124f4dc0d832c1bf3a451
Removal was scheduled for 10.0. Use the rainier-bmc machine or the
ast2600-evb as a replacement.
Reviewed-by: Philippe Mathieu-Daudé
Link: https://lore.kernel.org/r/20241119071352.515790-1-...@redhat.com
Signed-off-by: Cédric Le Goater
---
docs/about/deprecated.rst | 8
docs/abo
From: Jamin Lin
The testcases for ASPEED SMC model were placed in aspeed_smc-test.c.
However, this test file only supports for ARM32. To support all ASPEED SOCs
such as AST2700 whose CPU architecture is aarch64, introduces a new
aspeed-smc-utils source file and move all common APIs and testcases
From: Jamin Lin
Currently, these test cases used the hardcode offset 0x140 (0x14000 * 256)
which was beyond the 16MB flash size for flash page read/write command testing.
However, the default fmc flash model of ast1030-a1 EVB is "w25q80bl" whose size
is 1MB. To test SoC flash models, introduc
On 10/12/2024 21.43, Alex Bennée wrote:
In the qtest environment time will not step forward if the system is
paused (timers disabled) or we have no timer events to fire. As a
result VirtIO events are responded to directly and we don't need to
step time forward.
Potentially the clock_step calls c
On 10/12/2024 21.43, Alex Bennée wrote:
We have proper detection of prompts now so we don't need to guess with
sleep() sprinkled through the test. The extra step of calling halt is
just to flush the final bits of the log (although the last line is
still missed).
Signed-off-by: Alex Bennée
---
From: Jamin Lin
Add SDHCI model for AST2700 SDHCI support. The SDHCI controller only support 1
slot and registers base address is start at 0x1408_ and its interrupt is
connected to GICINT133_INTC at bit 1.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link: https://lore.kernel.org
From: Jamin Lin
So far, the test cases are used for testing SMC model with AST2400 BMC.
However, AST2400 is end off live and ASPEED is no longer support this SOC.
To test SMC model for AST2500, AST2600 and AST1030, move the test cases
from main to test_palmetto_bmc function.
Signed-off-by: Jamin
This simply moves the debian boot test from the avocado testsuite to
the new functional testsuite. No changes in the test.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-8-...@redhat.com
Signed-off-by: Cédric Le Goater
---
tests/avocado/boot_linux_console.py
On 10/12/2024 21.43, Alex Bennée wrote:
Time will not advance if the system is paused or there are no timer
events set for the future. In absence of pending timer events
advancing time would make no difference the system state. Attempting
to do so would be a bug and the test or device under test
From: Jamin Lin
Add test_ast2500_evb function and reused testcases for AST2500 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E62, 0x2000 and 0, respectively.
The default flash model of fmc_cs0 is "mx25l25635e" whose size is 32MB,
so set jedec_id 0xc22019
From: Jamin Lin
Add test_ast1030_evb function and reused testcases for AST1030 testing.
The base address, flash base address and ce index of fmc_cs0 are
0x7E62, 0x8000 and 0, respectively.
The default flash model of fmc_cs0 is "w25q80bl" whose size is 1MB,
so set jedec_id 0xef4014.
Signe
This introduces a new aspeed module for sharing code between tests and
moves the palmetto test to a new test file. No changes in the test.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-3-...@redhat.com
Signed-off-by: Cédric Le Goater
---
tests/functional/aspeed.
This simply moves the rainier-bmc test to a new test file. No changes
in the test. The test_arm_aspeed.py is deleted.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-7-...@redhat.com
Signed-off-by: Cédric Le Goater
---
tests/functional/meson.build
From: Jamin Lin
Currently, it set the hardcode value of capability registers to all ASPEED SOCs
However, the value of capability registers should be different for all ASPEED
SOCs. For example: the bit 28 of the Capability Register 1 should be 1 for
64-bits System Bus support for AST2700.
Introdu
From: Jamin Lin
Introduce a new ast2700 class to support AST2700. Add a new ast2700 SDHCI class
init function and set the value of capability register to "0x000719f80080".
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link: https://lore.kernel.org/r/20241204084453.610660-5-jamin_.
This moves the ast2600-evb tests to a new test file. No changes in the
test. The routines used to run the buildroot and sdk tests are removed
from the test_arm_aspeed.py file because now unused.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-6-...@redhat.com
Signed
This simply moves the romulus-bmc test to a new test file. No changes
in the test. The do_test_arm_aspeed routine is removed from the
test_arm_aspeed.py file because it is now unused.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-4-...@redhat.com
Signed-off-by: Cé
This simply moves the ast1030 tests to a new test file. No changes.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-2-...@redhat.com
Signed-off-by: Cédric Le Goater
---
tests/functional/meson.build| 1 +
tests/functional/test_arm_aspeed.py
From: Jamin Lin
Add a new testcase for write page command with QPI mode testing.
Currently, only run this testcase for AST2500, AST2600 and AST1030.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/r/20241127091543.1243114-9-jamin_...@aspeedtech.com
Signed-
From: Jamin Lin
Add test_ast2600_evb function and reused testcases for AST2600 testing.
The spi base address, flash base address and ce index of fmc_cs0 are
0x1E62, 0x2000 and 0, respectively.
The default flash model of fmc_cs0 is "mx66u51235f" whose size is 64MB,
so set jedec_id 0xc2253a
From: Jamin Lin
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link: https://lore.kernel.org/r/20241204084453.610660-3-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed_ast2600.c | 3 ++-
1 file changed, 2 insertion
From: Jamin Lin
Currently, these test cases only support to test CE0. To test all CE pins,
introduces new ce and node members in TestData structure. The ce member is used
for saving the ce index and node member is used for saving the node path,
respectively.
Signed-off-by: Jamin Lin
Reviewed-by
From: Jamin Lin
Currently, these test cases are only used for testing fmc_cs0 for AST2400.
To test others BMC SOCs, introduces a new TestData structure.
Users can set the spi base address, flash base address, jedesc id and so on
for different BMC SOCs and flash model testing.
Introduce new helpe
This moves the ast2500-evb tests to a new test file and extends the
aspeed module with routines used to run the buildroot and sdk
tests. No changes in the test.
Reviewed-by: Thomas Huth
Link: https://lore.kernel.org/r/20241206131132.520911-5-...@redhat.com
Signed-off-by: Cédric Le Goater
---
te
From: Jamin Lin
Add SDHCI model for AST2700 eMMC support. The eMMC controller only support 1
slot and registers base address is start at 0x1209_ and its interrupt is
connected to GICINT 15.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link: https://lore.kernel.org/r/2024120408445
From: Jamin Lin
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link: https://lore.kernel.org/r/20241204084453.610660-2-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goater
---
hw/sd/aspeed_sdhci.c | 6 --
1 file changed, 4 insertion
On 10/12/2024 21.43, Alex Bennée wrote:
Purely cosmetic.
Signed-off-by: Alex Bennée
---
util/qemu-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index ffe9a3c5c1..7b71655416 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-time
On 11/12/2024 04:03, Jason Wang wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On Wed, Dec 11, 2024 at 10:50 AM Duan, Zhenzhong
> wrote:
>> Hi Jason, Clement,
>>
>> Sorry for late r
Does efi-e1000.rom come from 8086100e.mrom?
If yes, how to convert it? Thanks
*8086100e.mrom*: ipxe/src/bin/8086100e.mrom
>
*efi-e1000.rom*: qemu/pc-bios/efi-e1000.rom
Ping
On Fri, Nov 15, 2024 at 9:44 AM Fea.Wang wrote:
> When the ethernet PHY's compatible string is 'ethernet-phy-id0141.0cc2',
> it will be matched with the Marvell driver in Linux instead of the
> generic driver. They differ from reading the PHY register17.11 bit which
> is for 'Speed and Dupl
Hi Jean,
On 11/26/24 5:55 AM, Jean-Philippe Brucker wrote:
This series enables running confidential VMs on Arm CCA. The host KVM
support is progressing but still under discussion [1], so there is no
urgency to upstream this series. I'm sending this new version to give a
status update, and also t
On Wed, Dec 11, 2024 at 10:50 AM Duan, Zhenzhong
wrote:
>
> Hi Jason, Clement,
>
> Sorry for late reply, just back from vacation.
>
> >-Original Message-
> >From: CLEMENT MATHIEU--DRIF
> >Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for
> >scalable modern mode
>
On Thu, Dec 05, 2024 at 09:57:16AM -0500, Xiaoyao Li wrote:
> Date: Thu, 5 Dec 2024 09:57:16 -0500
> From: Xiaoyao Li
> Subject: [RFC PATCH 4/4] cpu: Remove nr_cores from struct CPUState
> X-Mailer: git-send-email 2.34.1
>
> There is no user of it now, remove it.
>
> Signed-off-by: Xiaoyao Li
>
Hi Jason, Clement,
Sorry for late reply, just back from vacation.
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v5 18/20] intel_iommu: Introduce a property x-flts for
>scalable modern mode
>
>
>
>
>On 09/12/2024 07:24, Jason Wang wrote:
>> Caution: External email.
On Thu, Dec 05, 2024 at 09:57:13AM -0500, Xiaoyao Li wrote:
> Date: Thu, 5 Dec 2024 09:57:13 -0500
> From: Xiaoyao Li
> Subject: [RFC PATCH 1/4] i386/topology: Update the comment of
> x86_apicid_from_topo_ids()
> X-Mailer: git-send-email 2.34.1
>
> Update the comment of x86_apicid_from_topo_ids(
On 12/10/24 14:15, Richard Henderson wrote:
On 12/10/24 14:43, Alex Bennée wrote:
From: Pierrick Bouvier
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Signed-off-by: Pierrick Bouvier
-
v2:
- mov
On Tue, Dec 10, 2024 at 05:43:38PM +0100, Igor Mammedov wrote:
> Date: Tue, 10 Dec 2024 17:43:38 +0100
> From: Igor Mammedov
> Subject: Re: [RFC PATCH 3/4] i386: Track cores_per_module in CPUX86State
> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.43; x86_64-redhat-linux-gnu)
>
> On Thu, 5 Dec 2024 09:57
v3 -> v4:
- based on 'cxl/cxl-host: Support creation of a new CXL Host Bridge'[1]
- Align base addresses of CXL relevant Windows
- Remove redundant header files
v2 -> v3:
- create a new host bridge type: TYPE_SBSA_CXL_HOST
- CXL exclusive ECAM, PIO, MMIO32 & MMIO64 space in sbsa-ref
- combine all
This creates a specific cxl host bridge (0001:00) with two cxl
root ports on sbsa-ref. And the memory layout provides separate
space windows for the cxl host bridge in the sbsa-ref memmap:
- 64K CXL Host Bridge Component Registers (CHBCR)
- 64K CXL_PIO
- 128M CXL_MMIO
- 256M CXL_ECAM
- 4G CXL_
On Tue, Dec 10, 2024 at 08:48:21PM -0400, Jason Gunthorpe wrote:
> On Tue, Dec 10, 2024 at 03:01:48PM -0800, Nicolin Chen wrote:
>
> > Yet, here we seem to be missing a pathway between VMM and kernel
> > to agree on the MSI window decided by the kernel, as this patch
> > does the hard coding for a
On Tue, Dec 10, 2024 at 03:01:48PM -0800, Nicolin Chen wrote:
> Yet, here we seem to be missing a pathway between VMM and kernel
> to agree on the MSI window decided by the kernel, as this patch
> does the hard coding for a [0x800, 0x810) range.
I would ideally turn it around and provide
Currently, passing mem-lock=on to QEMU causes memory usage to grow by
huge amounts:
no memlock:
$ ./qemu-system-x86_64 -overcommit mem-lock=off
$ ps -p $(pidof ./qemu-system-x86_64) -o rss=
45652
$ ./qemu-system-x86_64 -overcommit mem-lock=off -enable-kvm
$ ps -p $(pidof ./qem
This will be used in the following commits to make it possible to only
lock memory on fault instead of right away.
Signed-off-by: Daniil Tatianin
---
include/sysemu/os-posix.h | 2 +-
include/sysemu/os-win32.h | 3 ++-
migration/postcopy-ram.c | 2 +-
os-posix.c| 10 -
Locking the memory without MCL_ONFAULT instantly prefaults any mmaped
anonymous memory with a write-fault, which introduces a lot of extra
overhead in terms of memory usage when all you want to do is to prevent
kcompactd from migrating and compacting QEMU pages. Add an option to
only lock pages laz
On 5.12.2024 20:02, Peter Xu wrote:
On Tue, Nov 26, 2024 at 10:22:42PM +0100, Maciej S. Szmigiero wrote:
On 26.11.2024 21:52, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Currently, ram_save_complete() sends a final SYNC multifd packet near this
function e
On 9.12.2024 10:28, Avihai Horon wrote:
On 17/11/2024 21:20, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
Implement the multifd device state transfer via additional per-device
thread inside save_live_complete_precopy_thread
Hi Avihai,
On 9.12.2024 10:13, Avihai Horon wrote:
Hi Maciej,
On 17/11/2024 21:20, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different
On 6.12.2024 23:20, Peter Xu wrote:
On Fri, Dec 06, 2024 at 07:03:36PM +0100, Maciej S. Szmigiero wrote:
On 4.12.2024 20:10, Peter Xu wrote:
On Sun, Nov 17, 2024 at 08:19:55PM +0100, Maciej S. Szmigiero wrote:
Important note:
4 VF benchmarks were done with commit 5504a8126115
("KVM: Dynamic si
Hi Cédric,
On 2.12.2024 18:56, Cédric Le Goater wrote:
Hello Maciej,
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
The multifd received data needs to be reassembled since device state
packets sent via different multifd channels can arrive out-of-order.
Therefore,
On 4.12.2024 23:43, Peter Xu wrote:
On Thu, Nov 28, 2024 at 01:11:53PM +0100, Maciej S. Szmigiero wrote:
+static int qemu_loadvm_load_thread(void *thread_opaque)
+{
+ struct LoadThreadData *data = thread_opaque;
+ int ret;
+
+ ret = data->function(&load_threads_abort, data->opaque);
+
On 5.12.2024 17:15, Peter Xu wrote:
On Wed, Dec 04, 2024 at 05:48:52PM -0500, Peter Xu wrote:
@@ -71,6 +72,10 @@
const unsigned int postcopy_ram_discard_version;
+static ThreadPool *load_threads;
+static int load_threads_ret;
+static bool load_threads_abort;
One thing I forgot to mention in
On 4.12.2024 23:48, Peter Xu wrote:
On Wed, Nov 27, 2024 at 09:16:49PM +0100, Maciej S. Szmigiero wrote:
On 27.11.2024 10:13, Cédric Le Goater wrote:
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
Some drivers might want to make use of auxiliary helper threads duri
On 3.12.2024 16:09, Avihai Horon wrote:
On 29/11/2024 19:15, Maciej S. Szmigiero wrote:
External email: Use caution opening links or attachments
On 29.11.2024 15:08, Cédric Le Goater wrote:
On 11/17/24 20:20, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
It's possible for load_cl
Hi Eric/Don/Shameer,
On Fri, Nov 08, 2024 at 12:52:42PM +, Shameer Kolothum wrote:
> Those IOVAs belong to [0x800, 0x810] matching
> MSI_IOVA_BASE and MSI_IOVA_LENGTH definitions in kernel
> arm-smmu-v3 driver. This is the window used to allocate
> IOVAs matching physical MSI doorbells
On 12/10/24 14:43, Alex Bennée wrote:
Now we have virtio-gpu Vulkan support lets add a test for it.
Currently this is using images build by buildroot:
https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html
Signed-off-by: Alex Bennée
---
tests/functional/test_aarch64_vir
On 12/10/24 14:43, Alex Bennée wrote:
We have proper detection of prompts now so we don't need to guess with
sleep() sprinkled through the test. The extra step of calling halt is
just to flush the final bits of the log (although the last line is
still missed).
Signed-off-by: Alex Bennée
Revie
On 12/10/24 14:43, Alex Bennée wrote:
Purely cosmetic.
Signed-off-by: Alex Bennée
---
util/qemu-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index ffe9a3c5c1..7b71655416 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-timer.
On 12/10/24 14:43, Alex Bennée wrote:
From: Pierrick Bouvier
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Signed-off-by: Pierrick Bouvier
-
v2:
- move test to its own file
- add sbsa test
- chec
On 10.12.24 22:51, Luo, Zhigang wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: David Hildenbrand
Sent: Tuesday, December 10, 2024 2:55 PM
To: Luo, Zhigang ; qemu-devel@nongnu.org
Cc: kra...@redhat.com; Igor Mammedov
Subject: Re: [PATCH] hostme
On 12/8/2024 4:48 PM, Richard Henderson wrote:
This structure, with bitfields, is incorrect for big-endian.
Use extract64 and deposit64 instead.
Signed-off-by: Richard Henderson
---
target/hexagon/fma_emu.c | 46 ++--
1 file changed, 16 insertions(+), 30
On 12/8/2024 4:48 PM, Richard Henderson wrote:
This structure, with bitfields, is incorrect for big-endian.
Use the existing float32_getexp_raw which uses extract32.
Signed-off-by: Richard Henderson
---
target/hexagon/fma_emu.c | 16 +++-
1 file changed, 3 insertions(+), 13 del
On 12/8/2024 4:48 PM, Richard Henderson wrote:
This massive macro is now only used once.
Expand it for use only by float64.
Signed-off-by: Richard Henderson
---
target/hexagon/fma_emu.c | 253 +++
1 file changed, 125 insertions(+), 128 deletions(-)
diff
On 12/8/2024 4:48 PM, Richard Henderson wrote:
The function is now unused.
Signed-off-by: Richard Henderson
---
target/hexagon/fma_emu.h | 2 -
target/hexagon/fma_emu.c | 171 ---
2 files changed, 173 deletions(-)
diff --git a/target/hexagon/fma_emu.
[AMD Official Use Only - AMD Internal Distribution Only]
> -Original Message-
> From: David Hildenbrand
> Sent: Tuesday, December 10, 2024 2:55 PM
> To: Luo, Zhigang ; qemu-devel@nongnu.org
> Cc: kra...@redhat.com; Igor Mammedov
> Subject: Re: [PATCH] hostmem-file: add the 'hmem' option
I tested your patch series, and I can confirm it fixes our bug repro case (not
involving the guest kernel).
Thank you
On Tue, 10 Dec 2024 17:39:42 +0100
Igor Mammedov wrote:
> CPU hotremove event is not delivered to OSPM if the CPU
> has been hotplugged before OS has booted.
> For details see [
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-30-alex.ben...@linaro.org>
---
tests/functional/test_ppc64_tuxrun.py | 16
1
Time will not advance if the system is paused or there are no timer
events set for the future. In absence of pending timer events
advancing time would make no difference the system state. Attempting
to do so would be a bug and the test or device under test would need
fixing.
Tighten up the result
We have proper detection of prompts now so we don't need to guess with
sleep() sprinkled through the test. The extra step of calling halt is
just to flush the final bits of the log (although the last line is
still missed).
Signed-off-by: Alex Bennée
---
tests/functional/test_aarch64_virt.py | 22
We didn't have this before and as it exercises the m68k virt platform
it seems worth adding. We don't wait for the shutdown because QEMU
will auto-exit on the shutdown.
Cc: Laurent Vivier
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-2
In the qtest environment time will not step forward if the system is
paused (timers disabled) or we have no timer events to fire. As a
result VirtIO events are responded to directly and we don't need to
step time forward.
Potentially the clock_step calls could be removed all together but as
we may
On Thu, Nov 21, 2024 at 09:46:16AM +, Shameerali Kolothum Thodi wrote:
> Hi Eric,
>
> > -Original Message-
> > From: Shameerali Kolothum Thodi
> > Sent: Wednesday, November 20, 2024 4:26 PM
> > To: 'eric.au...@redhat.com' ; qemu-
> > a...@nongnu.org; qemu-devel@nongnu.org
> > Cc: peter
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-21-alex.ben...@linaro.org>
---
tests/functional/test_arm_tuxrun.py | 28 ++---
Now there are new up to date images available we should update to them.
Note we re-use the riscv32 kernel and rootfs for test_riscv64_rv32.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-32-alex.ben...@linaro.org>
From: Pierrick Bouvier
This boot an OP-TEE environment, and launch a nested guest VM inside it
using the Realms feature. We do it for virt and sbsa-ref platforms.
Signed-off-by: Pierrick Bouvier
-
v2:
- move test to its own file
- add sbsa test
- check output of `cca-workload-attestation
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-29-alex.ben...@linaro.org>
---
tests/functional/test_ppc_tuxrun.py | 8
1 file chang
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-23-alex.ben...@linaro.org>
---
tests/functional/test_i386_tuxrun.py | 8
1 file chan
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-28-alex.ben...@linaro.org>
---
tests/functional/test_mips64el_tuxrun.py | 8
1 file
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-34-alex.ben...@linaro.org>
---
tests/functional/test_sparc64_tuxrun.py | 8
1 file c
Purely cosmetic.
Signed-off-by: Alex Bennée
---
util/qemu-timer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index ffe9a3c5c1..7b71655416 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-timer.c
@@ -680,7 +680,7 @@ int64_t qemu_clock_a
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-26-alex.ben...@linaro.org>
---
tests/functional/test_mipsel_tuxrun.py | 8
1 file ch
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-35-alex.ben...@linaro.org>
---
tests/functional/test_x86_64_tuxrun.py | 8
1 file ch
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-31-alex.ben...@linaro.org>
---
tests/functional/test_riscv32_tuxrun.py | 8
1 file c
Now we have virtio-gpu Vulkan support lets add a test for it.
Currently this is using images build by buildroot:
https://lists.buildroot.org/pipermail/buildroot/2024-December/768196.html
Signed-off-by: Alex Bennée
---
tests/functional/test_aarch64_virt.py | 83 ++-
1 f
There are two parts to this series. The first is the updated images
for all the guests that didn't make it into 9.2. There are also some
new functional tests for virtio-gpu along with some other clean-ups.
The qtest patches focus on ensuring things calling clock_step and
clock_set actually pay att
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-27-alex.ben...@linaro.org>
---
tests/functional/test_mips64_tuxrun.py | 8
1 file ch
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-33-alex.ben...@linaro.org>
---
tests/functional/test_s390x_tuxrun.py | 8
1 file cha
Now there are new up to date images available we should update to them.
Cc: Anders Roxell
Reviewed-by: Thomas Huth
Tested-by: Thomas Huth
Signed-off-by: Alex Bennée
Message-Id: <20241121165806.476008-25-alex.ben...@linaro.org>
---
tests/functional/test_mips_tuxrun.py | 8
1 file chan
On 10.12.24 20:32, Luo, Zhigang wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Hi David,
Hi,
Thanks for your comments.
Let me give you some background for this patch.
I am currently engaged in a project that requires to pass the EFI_MEMORY_SP
(Special Purpose Memory) type
[AMD Official Use Only - AMD Internal Distribution Only]
Hi David,
Please check my comments inline.
Thanks,
Zhigang
> -Original Message-
> From: David Hildenbrand
> Sent: Monday, December 9, 2024 4:11 PM
> To: Luo, Zhigang ; qemu-devel@nongnu.org
> Cc: kra...@redhat.com; Igor Mammedov
On Thu, Dec 05, 2024 at 10:59:52PM +0100, Philippe Mathieu-Daudé wrote:
> On 25/11/24 20:56, Jean-Philippe Brucker wrote:
> > Add a function to register a notifier, that is invoked after a ROM gets
> > loaded into guest memory.
> >
> > It will be used by Arm confidential guest support, in order to
On Tue, Dec 03, 2024 at 09:15:51PM +, Hongjian Fan wrote:
> Hi Jonathan,
>
> I'm trying to emulate our memory appliance which is similar to a MH-SLD. The
> memory device is connected to the host server while the size of the memory
> could be changed by the out-of-band fabric manager. If ther
On 12/10/24 02:10, Philippe Mathieu-Daudé wrote:
On 10/12/24 08:52, Thomas Huth wrote:
On 09/12/2024 21.33, Philippe Mathieu-Daudé wrote:
On 28/11/24 21:15, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
...
+For this reason, we disallow usage of bitfields in packed structures
and
On Thu, Dec 05, 2024 at 10:47:13PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Jean-Philippe,
>
> On 25/11/24 20:56, Jean-Philippe Brucker wrote:
> > Returning an error to kvm_init() is fatal anyway, no need to continue
> > the initialization.
> >
> > Signed-off-by: Jean-Philippe Brucker
> > ---
>
On Thu, Dec 05, 2024 at 11:23:09PM +0100, Philippe Mathieu-Daudé wrote:
> On 25/11/24 20:56, Jean-Philippe Brucker wrote:
> > Create a measurement log describing operations performed by QEMU to
> > initialize the guest, and load it into guest memory above the DTB.
> >
> > Cc: Stefan Berger
> > Si
On Thu, Dec 05, 2024 at 11:21:19PM +0100, Philippe Mathieu-Daudé wrote:
> On 25/11/24 20:56, Jean-Philippe Brucker wrote:
> > In order to write an event log, the ROM load notification handler needs
> > two more fields.
>
> IMHO it makes more sense to squash that in the "hw/core/loader:
> Add ROM l
On Tue, Dec 10, 2024 at 06:29:49PM +0100, Thomas Huth wrote:
> On 05/09/2024 01.52, Tiago Pasqualini wrote:
> > CPU time accounting in the kernel has been demonstrated to have a
> > sawtooth pattern[1][2]. This can cause the getrusage system call to
> > not be as accurate as we are expecting, which
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