[PATCH v1 18/19] intel_iommu: Return page walk level even when the translation fails

From: Clément Mathieu--Drif We use this information in vtd_do_iommu_translate to populate the IOMMUTLBEntry and indicate the correct page mask. This prevents ATS devices from sending many useless translation requests when a megapage or gigapage iova is not mapped to a physical address. Signed-of

[PATCH v1 07/19] pcie: Helper function to check if ATS is enabled

From: Clément Mathieu--Drif ats_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 1 + 2 files

[PATCH v1 08/19] pci: Cache the bus mastering status in the device

From: Clément Mathieu--Drif The cached is_master value is necessary to know if a device is allowed to issue ATS requests or not. This behavior is implemented in an upcoming patch. Signed-off-by: Clément Mathieu--Drif --- hw/pci/pci.c| 25 +++-- include/hw/pc

[PATCH v1 11/19] memory: Store user data pointer in the IOMMU notifiers

From: Clément Mathieu--Drif This will help developers of svm devices to track a state Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h index 756dd2ea7f..c0d064dbd8 100644 --- a/inclu

[PATCH v1 02/19] intel_iommu: Declare supported PASID size

From: Clément Mathieu--Drif PSS field of the ecap register stores the supported PASID size minus 1. Thus, this commit adds support for 20bits PASIDs. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 2 +- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 2 inserti

[PATCH v1 15/19] memory: Add an API for ATS support

From: Clément Mathieu--Drif IOMMU have to implement iommu_ats_request_translation to support ATS. Devices can use IOMMU_TLB_ENTRY_TRANSLATION_ERROR to check the tlb entries returned by a translation request. We decided not to use the existing translation operation for 2 reasons. First, ATS is d

[PATCH v1 13/19] atc: Generic ATC that can be used by PCIe devices that support SVM

From: Clément Mathieu--Drif As the SVM-capable devices will need to cache translations, we provide an first implementation. This cache uses a two-level design based on hash tables. The first level is indexed by a PASID and the second by a virtual addresse. Signed-off-by: Clément Mathieu--Drif

[PATCH v1 12/19] pci: Add a pci-level initialization function for iommu notifiers

From: Clément Mathieu--Drif We add a convenient way to initialize an device-iotlb notifier. This is meant to be used by ATS-capable devices. pci_device_iommu_memory_region_pasid is introduces in this commit and will be used in several other SVM-related functions exposed in the PCI API. Signed-o

[PATCH v1 14/19] atc: Add unit tests

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- tests/unit/meson.build | 1 + tests/unit/test-atc.c | 527 + 2 files changed, 528 insertions(+) create mode 100644 tests/unit/test-atc.c diff --git a/tests/unit/meson.build b/tests/

[PATCH v1 00/19] Rebase ATS onto lastest Qemu mailing list state

From: Clément Mathieu--Drif This series belongs to a list of series that add SVM support for VT-d. As a starting point, we use the series called 'intel_iommu: Enable stage-1 translation for emulated device' by Zhenzhong Duan and Yi Liu. Ref: https://github.com/yiliu1765/qemu/tree/zhenzhong/iomm

[PATCH v1 04/19] intel_iommu: Fill the PASID field when creating an IOMMUTLBEntry

From: Clément Mathieu--Drif PASID value must be used by devices as a key (or part of a key) when populating their ATC with the IOTLB entries returned by the IOMMU. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 9 + 1 file changed, 9 insertions(+) diff --git a/hw/i38

[PATCH v1 06/19] pcie: Helper functions to check if PASID is enabled

From: Clément Mathieu--Drif pasid_enabled checks whether the capability is present or not. If so, we read the configuration space to get the status of the feature (enabled or not). Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 9 + include/hw/pci/pcie.h | 2 ++ 2 fil

[PATCH v1 16/19] pci: Add a pci-level API for ATS

From: Clément Mathieu--Drif Devices implementing ATS can send translation requests using pci_ats_request_translation_pasid. The invalidation events are sent back to the device using the iommu notifier managed with pci_register_iommu_tlb_event_notifier and pci_unregister_iommu_tlb_event_notifier

[PATCH v1 10/19] intel_iommu: Implement the get_memory_region_pasid iommu operation

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 17 - include/hw/i386/intel_iommu.h | 2 +- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a92ef9fe74..7e867

[PATCH v1 19/19] intel_iommu: Add support for ATS

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 71 -- hw/i386/intel_iommu_internal.h | 1 + 2 files changed, 69 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index

[PATCH v1 03/19] memory: Allow to store the PASID in IOMMUTLBEntry

From: Clément Mathieu--Drif This will be useful for devices that support ATS and need to store entries in an ATC (device IOTLB). Signed-off-by: Clément Mathieu--Drif --- include/exec/memory.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/memory.h b/include/exec/memory.h inde

[PATCH v1 01/19] memory: Add permissions in IOMMUAccessFlags

From: Clément Mathieu--Drif This will be necessary for devices implementing ATS. We also define a new macro IOMMU_ACCESS_FLAG_FULL in addition to IOMMU_ACCESS_FLAG to support more access flags. IOMMU_ACCESS_FLAG is kept for convenience and backward compatibility. Here are the flags added (define

[PATCH v1 17/19] intel_iommu: Set address mask when a translation fails and adjust W permission

From: Clément Mathieu--Drif Implements the behavior defined in section 10.2.3.5 of PCIe spec rev 5. This is needed by devices that support ATS. Signed-off-by: Clément Mathieu--Drif --- hw/i386/intel_iommu.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/i38

[PATCH v1 09/19] pci: Add IOMMU operations to get memory regions with PASID

From: Clément Mathieu--Drif The region returned by this operation will be used as the input region for ATS. Signed-off-by: Clément Mathieu--Drif --- include/hw/pci/pci.h | 16 1 file changed, 16 insertions(+) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 1356

[PATCH v1 05/19] pcie: Add helper to declare PASID capability for a pcie device

From: Clément Mathieu--Drif Signed-off-by: Clément Mathieu--Drif --- hw/pci/pcie.c | 24 include/hw/pci/pcie.h | 6 +- include/hw/pci/pcie_regs.h | 5 + 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/hw/pci/pcie.c b/hw/pci/pci

Re: [PATCH] cpu: Initialize nr_cores and nr_threads in cpu_common_initfn()

On 11/25/2024 5:38 PM, Igor Mammedov wrote: On Fri, 22 Nov 2024 11:03:17 -0500 Xiaoyao Li wrote: Currently cpu->nr_cores and cpu->nr_threads are initialized in qemu_init_vcpu(), which is called a bit late in *cpu_realizefn() for each ARCHes. x86 arch would like to use nr_cores and nr_threads

Re: [PATCH v4 0/6] hw/loongarch/virt: Add cpu hotplug support

Hello everyone, I have a question about cpu hotplug to consult you. When I start qemu with the following parameters: /usr/bin/qemu-system-loongarch64 \ -machine virt  \ -accel tcg \ -bios /usr/share/edk2/loongarch64/QEMU_EFI.fd \ -m size=1048576k \ -smp 1,maxcpus=4,cores=1,threads=1,sockets=4  \

Re: [RFC PATCH 0/5] support unaligned access to xHCI Capability

On 2024/11/28 20:15, Peter Maydell wrote: On Thu, 28 Nov 2024 at 06:19, Tomoyuki HIROSE wrote: Hi, thank you for your comment. On 2024/11/27 20:23, Peter Maydell wrote: On Wed, 27 Nov 2024 at 04:34, Tomoyuki HIROSE wrote: I would be happy to receive your comments. ping. Hi; this one is on

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

On Thu, 2024-11-28 at 14:21 +, Alex Bennée wrote: > Yanfeng Liu writes: > > > This adds `virt` virtual register on debug interface so that users > > can access current virtualization mode for debugging purposes. > > > > Signed-off-by: Yanfeng Liu > > --- > >  gdb-xml/riscv-32bit-virtual.xml

[PATCH v2] plugins: optimize cpu_index code generation

When running with a single vcpu, we can return a constant instead of a load when accessing cpu_index. A side effect is that all tcg operations using it are optimized, most notably scoreboard access. When running a simple loop in user-mode, the speedup is around 20%. Signed-off-by: Pierrick Bouvier

[PATCH v2] tests/functional/aarch64: add tests for FEAT_RME

This boot an OP-TEE environment, and launch a nested guest VM inside it using the Realms feature. We do it for virt and sbsa-ref platforms. Signed-off-by: Pierrick Bouvier - v2: - move test to its own file - add sbsa test - check output of `cca-workload-attestation report` Signed-off-by: P

Re: [PATCH v3 2/3] docs/devel/style: add a section about bitfield, and disallow them for packed structures

On 11/28/24 14:15, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- docs/devel/style.rst | 20 1 file changed, 20 insertions(+) Reviewed-by: Richard Henderson r~ diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 2f68b500798..2d73e6a8f7a 1006

Re: [PATCH v3 1/3] win32: remove usage of attribute gcc_struct

On 11/28/24 14:15, Pierrick Bouvier wrote: This attribute is not recognized by clang. An investigation has been performed to ensure this attribute has no effect on layout of structures we use in QEMU [1], so it's safe to remove now. In the future, we'll forbid introducing new bitfields in packe

Re: [PATCH] plugins: optimize cpu_index code generation

On 11/27/24 09:53, Richard Henderson wrote: On 11/26/24 13:02, Pierrick Bouvier wrote: @@ -266,6 +266,19 @@ static void qemu_plugin_vcpu_init__async(CPUState *cpu, run_on_cpu_data unused) assert(cpu->cpu_index != UNASSIGNED_CPU_INDEX); qemu_rec_mutex_lock(&plugin.lock); + +

Re: [PATCH 08/12] docs/system/arm/orangepi: update links

On 11/22/24 14:50, Pierrick Bouvier wrote: Signed-off-by: Pierrick Bouvier --- docs/system/arm/orangepi.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst index 9afa54213b0..db87e81fec4 100644 --- a/docs/syst

[PATCH v3 0/3] Enable clang build on Windows

For now, it was only possible to build plugins using GCC on Windows. However, windows-aarch64 only supports Clang. This biggest roadblock was to get rid of gcc_struct attribute, which is not supported by Clang. After investigation, we proved it was safe to drop it. Built and tested on Windows (all

[PATCH v3 1/3] win32: remove usage of attribute gcc_struct

This attribute is not recognized by clang. An investigation has been performed to ensure this attribute has no effect on layout of structures we use in QEMU [1], so it's safe to remove now. In the future, we'll forbid introducing new bitfields in packed struct, as they are the one potentially imp

[PATCH v3 3/3] plugins: enable linking with clang/lld

Windows uses a special mechanism to enable plugins to work (DLL delay loading). Option for lld is different than ld. MSYS2 clang based environment use lld by default, so restricting to this config on Windows is safe, and will avoid false bug reports. Signed-off-by: Pierrick Bouvier --- meson.bu

[PATCH v3 2/3] docs/devel/style: add a section about bitfield, and disallow them for packed structures

Signed-off-by: Pierrick Bouvier --- docs/devel/style.rst | 20 1 file changed, 20 insertions(+) diff --git a/docs/devel/style.rst b/docs/devel/style.rst index 2f68b500798..2d73e6a8f7a 100644 --- a/docs/devel/style.rst +++ b/docs/devel/style.rst @@ -416,6 +416,26 @@ definitio

[PULL for-9.2 6/7] 9pfs: fix 'Tgetattr' after unlink

With a valid file ID (FID) of an open file, it should be possible to send a 'Tgettattr' 9p request and successfully receive a 'Rgetattr' response, even if the file has been removed in the meantime. Currently this would fail with ENOENT. I.e. this fixes the following misbehaviour with a 9p Linux cl

[PULL for-9.2 5/7] 9pfs: remove obsolete comment in v9fs_getattr()

The comment claims that we'd only support basic Tgetattr fields. This is no longer true, so remove this comment. Fixes: e06a765efbe3 ("hw/9pfs: Add st_gen support in getattr reply") Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: --- hw/9pfs/9p.c | 4 1 file chang

Re: [PATCH v11 01/15] ui & main loop: Redesign of system-specific main thread event handling

On Thu, 28 Nov 2024 at 12:17, Akihiko Odaki wrote: > On 2024/11/28 0:02, Phil Dennis-Jordan wrote: > > macOS's Cocoa event handling must be done on the initial (main) thread > > of the process. Furthermore, if library or application code uses > > libdispatch, the main dispatch queue must be handl

[PULL for-9.2 2/7] tests/9p: add 'use-after-unlink' test

After removing a file from the file system, we should still be able to work with the file if we already had it open before removal. As a first step we verify that it is possible to write to an unlinked file, as this is what already works. This test is extended later on after having fixed other use

[PULL for-9.2 3/7] tests/9p: fix Rreaddir response name

All 9p response types are prefixed with an "R", therefore fix "READDIR" -> "RREADDIR" in function rmessage_name(). Fixes: 4829469fd9ff ("tests/virtio-9p: added readdir test") Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: --- tests/qtest/libqos/virtio-9p-client.c | 2

[PULL for-9.2 7/7] tests/9p: also check 'Tgetattr' in 'use-after-unlink' test

This verifies expected behaviour of previous bug fix patch. Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: <7017658155c517b9665b75333a97c79aa2d4f3df.1732465720.git.qemu_...@crudebyte.com> --- tests/qtest/virtio-9p-test.c | 5 + 1 file changed, 5 insertions(+) diff

[PULL for-9.2 0/7] 9p queue 2024-11-28

gs/pull-9p-20241128 for you to fetch changes up to eaab44ccc59b83d8dff60fca3361a9b98ec7fee6: tests/9p: also check 'Tgetattr' in 'use-after-unlink' test (2024-11-28 18:54:00 +0100) * Fix open-unlink-fstat idiom o

[PULL for-9.2 4/7] tests/9p: add missing Rgetattr response name

'Tgetattr' 9p request and its 'Rgetattr' response types are already used by test client, however this response type is yet missing in function rmessage_name(), so add it. Fixes: a6821b828404 ("tests/9pfs: compare QIDs in fs_walk_none() test") Signed-off-by: Christian Schoenebeck Reviewed-by: Greg

[PULL for-9.2 1/7] 9pfs: cleanup V9fsFidState

Drop V9fsFidState's 'next' member, which is no longer used since: f5265c8f917e ('9pfs: use GHashTable for fid table') Fixes: f5265c8f917e ('9pfs: use GHashTable for fid table') Signed-off-by: Christian Schoenebeck Reviewed-by: Greg Kurz Message-Id: --- hw/9pfs/9p.h | 1 - 1 file changed, 1

[PULL 1/3] amd_iommu: Fix kvm_enable_x2apic link error with clang in non-KVM builds

From: Sairaj Kodilkar Commit b12cb3819 (amd_iommu: Check APIC ID > 255 for XTSup) throws linking error for the `kvm_enable_x2apic` when kvm is disabled and Clang is used for compilation. This issue comes up because Clang does not remove the function callsite (kvm_enable_x2apic in this case) duri

Re: [PATCH] i386/kvm: Fix kvm_enable_x2apic link error in non-KVM builds

On Thu, 28 Nov 2024 at 17:46, Philippe Mathieu-Daudé wrote: > On 28/11/24 17:38, Phil Dennis-Jordan wrote: > > Paolo, could we please apply either Sairaj and Santosh's fix at > > https://patchew.org/QEMU/20241114114509.15350-1-sarun...@amd.com/ > >

[PULL 3/3] scsi: megasas: Internal cdbs have 16-byte length

From: Guenter Roeck Host drivers do not necessarily set cdb_len in megasas io commands. With commits 6d1511cea0 ("scsi: Reject commands if the CDB length exceeds buf_len") and fe9d8927e2 ("scsi: Add buf_len parameter to scsi_req_new()"), this results in failures to boot Linux from affected SCSI d

[PULL 2/3] hvf: complete 1G page support

From: Alexander Graf Hvf on x86 only supported 2MiB large pages, but never bothered to strip out the 1GiB page size capability from -cpu host. With QEMU 8.0.0 this became a problem because OVMF started to use 1GiB pages by default. Let's just unconditionally add 1GiB page walk support to the wal

[PULL 0/3] Bugfixes for QEMU 9.2 rc3

The following changes since commit 24602b77f5658ae8377958c15fdef2f44affc743: Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-11-28 10:50:20 +) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream f

[PATCH 5/6] preallocate: simplify preallocate_drop_resize

Once permission change process is normalized, there is no need to have permission update inside preallocate_drop_resize() and preallocate_truncate_to_real_size() could be merged into the caller. Signed-off-by: Denis V. Lunev CC: Vladimir Sementsov-Ogievskiy CC: Andrey Drobyshev CC: Kevin Wolf

[PATCH v3 0/6] block/preallocate: fix image truncation logic

Recent QEMU changes around preallocate_set_perm mandates that it is not possible to poll on aio_context inside this function anymore. Thus truncate operation has been moved inside bottom half. This bottom half is scheduled from preallocate_set_perm() and that is all. This approach proven to be pro

[PATCH 1/6] preallocate: truncate the image inside bdrv_inactivate()

Let us assume that we have the following quite usual chain: QCOW2 -> preallocate-filter -> raw-file In this case in the case of the migration over shared storage, f.e. NFS we go through bdrv_inactivate() bdrv_inactivate_recurse() qcow2_inactivate() <- writes a lot of data, f.e.

[PATCH 2/6] preallocate: do not enable filter inside preallocate_co_getlength()

Let us auto-enable it inside handle_write() and truncate(), i.e. on the actual write operation. This just makes things more relaxing. Signed-off-by: Denis V. Lunev CC: Vladimir Sementsov-Ogievskiy CC: Andrey Drobyshev CC: Kevin Wolf CC: Hanna Reitz --- block/preallocate.c | 9 + 1 fi

[PATCH 3/6] preallocate: rework preallocate_truncate_to_real_size()

The filter is not enabled if s->data_end is negative. In this case it would be useless completely to initialize s->file_end inside preallocate_truncate_to_real_size() without setting s->data_end. Here are we are going to reset the state and disable the filter as we are either in the process of swit

[PATCH 6/6] iotests: add preallocate filter checks

From: Andrey Drobyshev This test summaries the cases faced inside Virtuozzo with the preallocation filter worth to be added to unit tests: 1. Launch a VM whose block graph has preallocate filter node and migrate it locally into a file. 2. Same, but make sure preallocate filter is activa

[PATCH 4/6] preallocate: remove bottom half from preallocate filter

IO operations like truncate inside preallocate_set_perm() looks like insane complexity which should not seen in the reality. Preallocate filter lifecycle is very close to the lifecycle of CBT. This is well handled inside QCOW2 driver. The approach should be the same inside preallocation filter. It

Re: [PULL v2 15/31] Hexagon (target/hexagon) use softfloat default NaN and tininess

On 11/28/24 07:29, Peter Maydell wrote: On Sun, 2 May 2021 at 15:44, Richard Henderson wrote: From: Taylor Simpson Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Message-Id: <1617930474-31979-11-git-send-email-tsimp...@quicinc.com> Signed-off-

Re: [PATCH v4 00/15] vfio: VFIO migration support with vIOMMU

On 28/11/2024 03:19, Zhangfei Gao wrote: > Hi, Joao > > On Fri, Jun 23, 2023 at 5:51 AM Joao Martins > wrote: >> >> Hey, >> >> This series introduces support for vIOMMU with VFIO device migration, >> particurlarly related to how we do the dirty page tracking. >> >> Today vIOMMUs serve two purpos

Re: [RFC PATCH 2/5] hw/arm/smmuv3: Add initial support for SMMUv3 Nested device

On Thu, Nov 28, 2024 at 08:54:26AM -0400, Jason Gunthorpe wrote: > On Wed, Nov 27, 2024 at 08:44:47PM -0800, Nicolin Chen wrote: > > On Wed, Nov 27, 2024 at 11:29:06PM -0500, Donald Dutile wrote: > > > On 11/27/24 5:21 AM, Shameerali Kolothum Thodi wrote: > > > > > > W.r.t naming, maybe something r

Re: [RFC PATCH] softfloat: Allow runtime choice of default NaN value

On 11/28/24 08:54, Peter Maydell wrote: Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depend

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

On 11/28/24 08:21, Alex Bennée wrote: Yanfeng Liu writes: This adds `virt` virtual register on debug interface so that users can access current virtualization mode for debugging purposes. Signed-off-by: Yanfeng Liu --- gdb-xml/riscv-32bit-virtual.xml | 1 + gdb-xml/riscv-64bit-virtual.xm

Re: [PATCH for-10.0 25/25] fpu: Remove use_first_nan field from float_status

On 11/28/24 04:43, Peter Maydell wrote: The use_first_nan field in float_status was an xtensa-specific way to select at runtime from two different NaN propagation rules. Now that xtensa is using the target-agnostic NaN propagation rule selection that we've just added, we can remove use_first_nan

Re: [PULL 15/42] tests/functional: enable pre-emptive caching of assets

On Thu, Nov 28, 2024 at 09:25:03AM -0800, Pierrick Bouvier wrote: > On 11/28/24 01:34, Daniel P. Berrangé wrote: > > On Wed, Nov 27, 2024 at 10:31:13AM -0800, Pierrick Bouvier wrote: > > > On 11/27/24 01:06, Daniel P. Berrangé wrote: > > > > On Tue, Nov 26, 2024 at 04:54:18PM -0600, Richard Henders

Re: [PATCH for-10.0 24/25] target/hppa: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for HPPA, and remove the ifdef from pickNaNMulAdd(). HPPA is the only target that was using the default branch of the ifdef ladder (other targets either do not use muladd or set default_nan_mode), so we can remove the i

Re: [PATCH for-10.0 23/25] target/i386: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for i386. We had no i386-specific behaviour in the old ifdef ladder, so we were using the default "prefer a then b then c" fallback. This is very likely wrong for i386, but in this refactoring we don't want to make a b

Re: [PATCH] hw/display/vga: Do not reset 'big_endian_fb' in vga_common_reset()

On 28/11/24 18:52, Philippe Mathieu-Daudé wrote: The 'pci-vga' device allow setting a 'big-endian-framebuffer' property since commit 3c2784fc864 ("vga: Expose framebuffer byteorder as a QOM property"). Similarly, the 'virtio-vga' device since commit 8be61ce2ce3 ("virtio-vga: implement big-endian-

Re: [PATCH for-10.0 22/25] target/xtensa: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for xtensa, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/xtensa/fpu_helper.c | 2 ++ fpu/softfloat-specialize.c.inc | 8 2 files changed, 2 insertions(+), 8 deletio

Re: [PATCH for-10.0 21/25] target/mips: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/mips/fpu_helper.h | 4 target/mips/msa.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +--- 3 f

Re: [PATCH for-10.0 20/25] target/sparc: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for SPARC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/sparc/cpu.c | 2 ++ fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-)

Re: [PATCH for-10.0 19/25] target/s390x: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for s390x, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/s390x/cpu.c | 1 + fpu/softfloat-specialize.c.inc | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) R

Re: [PATCH for-10.0 18/25] target/ppc: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for PPC, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/ppc/cpu_init.c | 8 fpu/softfloat-specialize.c.inc | 6 -- 2 files changed, 8 insertions(+), 6 deleti

[PATCH] hw/display/vga: Do not reset 'big_endian_fb' in vga_common_reset()

The 'pci-vga' device allow setting a 'big-endian-framebuffer' property since commit 3c2784fc864 ("vga: Expose framebuffer byteorder as a QOM property"). Similarly, the 'virtio-vga' device since commit 8be61ce2ce3 ("virtio-vga: implement big-endian-framebuffer property"). Both call vga_common_reset

Re: [PATCH for-10.0 17/25] target/loongarch: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for loongarch, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/loongarch/tcg/fpu_helper.c | 1 + fpu/softfloat-specialize.c.inc| 2 -- 2 files changed, 1 insertion(+), 2 deleti

Re: [PATCH for-10.0 16/25] target/arm: Set Float3NaNPropRule explicitly

On 11/28/24 04:43, Peter Maydell wrote: Set the Float3NaNPropRule explicitly for Arm, and remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/arm/cpu.c | 5 + fpu/softfloat-specialize.c.inc | 8 +--- 2 files changed, 6 insertions(+), 7 deletio

Re: [PATCH for-10.0 15/25] tests/fp: Explicitly set 3-NaN propagation rule

On 11/28/24 04:43, Peter Maydell wrote: Explicitly set a rule in the softfloat tests for propagating NaNs in the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and so we should select here the Arm rule of float_3nan_prop_s_cab. Signed-off-by: Peter Maydell --- tests/fp/fp-bench.

Re: [PATCH for-10.0 14/25] softfloat: Allow runtime choice of NaN propagation for muladd

On 11/28/24 04:42, Peter Maydell wrote: +/* + * 3-input NaN propagation rule, for fused multiply-add. Individual + * architectures have different rules for which input NaN is + * propagated to the output when there is more than one NaN on the + * input. + * + * If default_nan_mode is enabled then

Re: [PULL 15/42] tests/functional: enable pre-emptive caching of assets

On 11/28/24 01:34, Daniel P. Berrangé wrote: On Wed, Nov 27, 2024 at 10:31:13AM -0800, Pierrick Bouvier wrote: On 11/27/24 01:06, Daniel P. Berrangé wrote: On Tue, Nov 26, 2024 at 04:54:18PM -0600, Richard Henderson wrote: On 11/26/24 11:52, Thomas Huth wrote: I think we want to continue to m

Re: [PATCH] hw/i386/amd_iommu: Allow migration

On 21/11/2024 11:42, Joao Martins wrote:> On 20/11/2024 07:31, Suravee Suthikulpanit wrote: >> Add migration support for AMD IOMMU model by saving necessary AMDVIState >> parameters for MMIO registers, device table, command buffer, and event >> buffers. >> >> Signed-off-by: Suravee Suthikulpanit >

Re: [PATCH] i386/kvm: Fix kvm_enable_x2apic link error in non-KVM builds

On 28/11/24 17:38, Phil Dennis-Jordan wrote: Paolo, could we please apply either Sairaj and Santosh's fix at https://patchew.org/QEMU/20241114114509.15350-1-sarun...@amd.com/ or mine to fix this link error? As neither patch has

Re: [PATCH] i386/kvm: Fix kvm_enable_x2apic link error in non-KVM builds

Paolo, could we please apply either Sairaj and Santosh's fix at https://patchew.org/QEMU/20241114114509.15350-1-sarun...@amd.com/ or mine to fix this link error? As neither patch has so far been merged, 9.2.0-rc2 still fails to build on macOS, at least on my local systems. I'm not sure why CI build

Re: [PATCH v11 09/15] gpex: Allow more than 4 legacy IRQs

On Thu, 28 Nov 2024 at 13:45, Akihiko Odaki wrote: > On 2024/11/28 0:02, Phil Dennis-Jordan wrote: > > From: Alexander Graf > > > > Some boards such as vmapple don't do real legacy PCI IRQ swizzling. > > Instead, they just keep allocating more board IRQ lines for each new > > legacy IRQ. Let's s

Re: [PATCH v11 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Thu, 28 Nov 2024 at 12:25, Akihiko Odaki wrote: > On 2024/11/28 0:02, Phil Dennis-Jordan wrote: > > MacOS provides a framework (library) that allows any vmm to implement a > > paravirtualized 3d graphics passthrough to the host metal stack called > > ParavirtualizedGraphics.Framework (PVG). Th

Re: [PATCH] tests/functional/test_acpi_bits: Turn the test into a QemuSystemTest

On 28/11/24 12:50, Thomas Huth wrote: By using QemuSystemTest as a base class, we can use the set_machine() command to check whether the required machine is available in the binary (otherwise this test is failing when QEMU has been compiled without the default 'pc' machine type). Signed-off-by:

[RFC PATCH] softfloat: Allow runtime choice of default NaN value

Currently we hardcode the default NaN value in parts64_default_nan() using a compile-time ifdef ladder. This is awkward for two cases: * for single-QEMU-binary we can't hard-code target-specifics like this * for Arm FEAT_AFP the default NaN value depends on FPCR.AH (specifically the sign bit i

[PATCH v6 3/9] target/riscv: Implement Ssdbltrp sret, mret and mnret behavior

When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning to VU from HS. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- targ

[PATCH v6 8/9] target/riscv: Implement Smdbltrp behavior

When the Smsdbltrp ISA extension is enabled, if a trap happens while MSTATUS.MDT is already set, it will trigger an abort or an NMI is the Smrnmi extension is available. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 56 ---

Re: [PATCH v2] riscv/gdb: add virt mode debug interface

Yanfeng Liu writes: > This adds `virt` virtual register on debug interface so that users > can access current virtualization mode for debugging purposes. > > Signed-off-by: Yanfeng Liu > --- > gdb-xml/riscv-32bit-virtual.xml | 1 + > gdb-xml/riscv-64bit-virtual.xml | 1 + > target/riscv/gdbst

[PATCH v6 9/9] target/riscv: Add Smdbltrp ISA extension enable switch

Add the switch to enable the Smdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index be7c0475bf..9e2166a810 100644 --- a/target/riscv/cpu.c +++ b

Re: [RFC PATCH 06/14] s390x/cpumodel: add Concurrent-functions facility support

On 12/11/2024 16.54, Hendrik Brueckner wrote: The Concurrent-functions facility introduces the new instruction Perform Functions with Concurrent Results (PFCR) with few subfunctions. Signed-off-by: Hendrik Brueckner --- linux-headers/asm-s390/kvm.h| 3 ++- target/s390x/cpu_features.

[PATCH v6 7/9] target/riscv: Implement Smdbltrp sret, mret and mnret behavior

When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared when executing sret if executed in M-mode. When executing mret/mnret, SSTATUS.MDT is cleared. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/op_helper.c | 12 1 file changed, 12 insert

[PATCH v6 5/9] target/riscv: Add Ssdbltrp ISA extension enable switch

Add the switch to enable the Ssdbltrp ISA extension. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1fac03ca99..f30630e947 100644 --- a/target/riscv/cpu.c +++ b

[PATCH v6 1/9] target/riscv: fix henvcfg potentially containing stale bits

With the current implementation, if we had the following scenario: - Set bit x in menvcfg - Set bit x in henvcfg - Clear bit x in menvcfg then, the internal variable env->henvcfg would still contain bit x due to both a wrong menvcfg mask used in write_henvcfg() as well as a missing update of henvcf

[PATCH v6 0/9] target/riscv: Add support for Smdbltrp and Ssdbltrp extensions

A double trap typically arises during a sensitive phase in trap handling operations — when an exception or interrupt occurs while the trap handler (the component responsible for managing these events) is in a non-reentrant state. This non-reentrancy usually occurs in the early phase of trap handlin

[PATCH v6 6/9] target/riscv: Add Smdbltrp CSRs handling

Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior. Also set MDT to 1 at reset according to the specification. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 +++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_cfg.h | 1 + tar

[PATCH v6 2/9] target/riscv: Add Ssdbltrp CSRs handling

Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT, {H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the presence of the Ssdbltrp ISA extension. Signed-off-by: Clément Léger --- target/riscv/cpu.h| 1 + target/riscv/cpu_bits.h | 6 target/riscv/cpu_cfg.h

[PATCH v6 4/9] target/riscv: Implement Ssdbltrp exception handling

When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode while SSTATUS.SDT isn't cleared, generate a double trap exception to M-mode. Signed-off-by: Clément Léger Reviewed-by: Alistair Francis --- target/riscv/cpu.c| 2 +- target/riscv/cpu_bits.h | 1 + target/riscv/c

Re: [PATCH for-10.0 13/25] target/hppa: Set FloatInfZeroNaNRule explicitly

On 11/28/24 04:42, Peter Maydell wrote: Set the FloatInfZeroNaNRule explicitly for the HPPA target, so we can remove the ifdef from pickNaNMulAdd(). As this is the last target to be converted to explicitly setting the rule, we can remove the fallback code in pickNaNMulAdd() entirely. Signed-off

Re: [PATCH for-10.0 12/25] target/loongarch: Set FloatInfZeroNaNRule explicitly

On 11/28/24 04:42, Peter Maydell wrote: Set the FloatInfZeroNaNRule explicitly for the loongarch target. Signed-off-by: Peter Maydell --- target/loongarch/tcg/fpu_helper.c | 5 + fpu/softfloat-specialize.c.inc| 7 +-- 2 files changed, 6 insertions(+), 6 deletions(-) Reviewed-b

Re: [PATCH for-10.0 11/25] target/x86: Set FloatInfZeroNaNRule explicitly

On 11/28/24 04:42, Peter Maydell wrote: Set the FloatInfZeroNaNRule explicitly for the x86 target. Signed-off-by: Peter Maydell --- target/i386/tcg/fpu_helper.c | 7 +++ fpu/softfloat-specialize.c.inc | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/i386/tc

Re: [PULL 00/13] virtio,pc,pci: bug fixes, new test

On Wed, 27 Nov 2024 at 13:57, Michael S. Tsirkin wrote: > > The following changes since commit 34754a3a627e1937be7f3daaa0c5e73d91c7d9b5: > > Update version for v9.2.0-rc1 release (2024-11-20 18:27:48 +) > > are available in the Git repository at: > > https://git.kernel.org/pub/scm/virt/kvm

Re: [PATCH for-10.0 05/25] target/arm: Set FloatInfZeroNaNRule explicitly

On 11/28/24 04:42, Peter Maydell wrote: Set the FloatInfZeroNaNRule explicitly for the Arm target, so we can remove the ifdef from pickNaNMulAdd(). Signed-off-by: Peter Maydell --- target/arm/cpu.c | 3 +++ fpu/softfloat-specialize.c.inc | 8 +--- 2 files changed, 4 inserti

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