On 19/11/2024 16.05, Daniel P. Berrangé wrote:
When functional tests go wrong, it will often be related to the console
interaction wait state. By logging the messages that we're looking for,
and data we're about to be sending, it'll be easier to diagnose where
tests are getting stuck.
Signed-off
On 19/11/2024 16.05, Daniel P. Berrangé wrote:
Set the 'qemu.machine' logger to 'DEBUG' level, to ensure we see log
messages related to the QEMUMachine class. Most importantly this
ensures we capture the full QEMU command line args for instances we
spawn.
Signed-off-by: Daniel P. Berrangé
---
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 74d7076f5a..11e3a6d647 100644
--- a/targe
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 19 +++
target/riscv/insn_trans/trans_rvh.c.inc | 11 +++
target/riscv/translate.c| 4
4 files changed, 3
On 19/11/2024 17.13, Philippe Mathieu-Daudé wrote:
This document tries to document the steps required to:
- Have a single binary to run system emulations
- Emulate different architectures in the same process
- Have QEMU assemble dynamic machines at runtime
Signed-off-by: Philippe Mathieu-
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.c | 74 +++
2 files changed, 79 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 417ff45544..74d7076f5a 100644
--- a/targ
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 4
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 31 ++-
target/riscv/pmp.c | 14 +++---
target/riscv/pmp.h |
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e80dcd2e6..fd3ea9ce76 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -186,11 +186,14 @@ const RISCVIsaExt
From: Alexey Baturo
Zjpm extension is finally ratified. And it's much simplier compared to the
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
t
Hi everyone,
The QEMU v9.0.4 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-9.0.4.tar.xz
https://download.qemu.org/qemu-9.0.4.tar.xz.sig (signature)
v9.0.4 is now tagged in the o
Hi Jean, Mathieu,
I’ve been using you guys’ ccs/v3 QEMU for some time to bring up an Realm
instance without a major issue, and as a one who is making changes libvirt to
support CCA, I wonder if you could merge the v3 local changes under qap dir
first so I can query the feature from libvirt?
Th
If pointer arguments to HVX helper functions are not marked restrict *,
then LLVM will assume that input vectors may alias and emit runtime
checks.
Signed-off-by: Anton Johansson
---
target/hexagon/mmvec/macros.h | 36 +--
1 file changed, 18 insertions(+), 18 dele
Daniel P. Berrangé writes:
> Historical bugs in avocado related to zstd support are not relevant to
> the code now that it uses QEMU's native test harness.
>
> Signed-off-by: Daniel P. Berrangé
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Sets up a barebones meson.build that handles:
1. Exposing command for converting .c files to LLVM IR by looking at
compile_commads.json;
2. Finding LLVM and verifying the LLVM version manually by running
llvm-config, needed for dealing with multiple LLVM versions in a
sane way;
Wrap __attribute__((annotate(str))) in a macro for convenient
function annotations. Will be used in future commits to tag functions
for translation by helper-to-tcg, and to specify which helper function
arguments correspond to immediate or vector values.
Signed-off-by: Anton Johansson
---
inclu
Functions with cycles are removed for two primary reasons:
* as a simplifying assumption for register allocation which occurs down
the line, and;
* if a function contains cycles post-optimization neither unrolling or
loop vectorization were beneficial, and the function _might_ be
For HVX instructions that were successfully translated by helper-to-tcg,
emit calls to emit_*() "manually" from generate_*(). Recall that scalar
instructions translated by helper-to-tcg are automatically called by a
hook in tcg_gen_callN.
Signed-off-by: Anton Johansson
---
target/hexagon/gen_tc
Introduces a new python helper script to convert a set of QEMU .c files to
LLVM IR .ll using clang. Compile flags are found by looking at
compile_commands.json, and llvm-link is used to link together all LLVM
modules into a single module.
Signed-off-by: Anton Johansson
---
subprojects/helper-to
Adds a custom pipeline, similar to LLVM opt, with the goal of taking an
input LLVM IR module to an equivalent output .c file implementing
functions in TCG.
Initial LLVM boilerplate is added until the creation of a
ModulePassManager. A custom target derived from x64 is added, to ensure
consistent
The input LLVM module may define an array of cpu_mapping structs,
describing the mapping between fields in a specified struct (usually
CPUArchState) and TCG globals.
Create a map between offsets into the specified struct and TCG globals
(name, size, number of elements, stride) by iterating over th
Only generate input functions to idef-parser for instructions which
failed to be translated by helper-to-tcg.
Signed-off-by: Anton Johansson
---
target/hexagon/gen_idef_parser_funcs.py | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/hexagon/gen_idef_parser_funcs.py
b/target/hex
Make an early pass over all functions in the input module and filter out
functions with:
1. Invalid return type;
2. No helper-to-tcg annotation.
Signed-off-by: Anton Johansson
---
.../helper-to-tcg/include/PrepareForOptPass.h | 7 +-
.../PrepareForOptPass/PrepareForOptPass.cpp | 93 ++
This commit adds a gvec function for copying data from constant array
given in C to a gvec intptr_t. For each element, a host store of
each constant is performed, this is not ideal and will inflate TBs for
large vectors.
Moreover, data will be copied during each run of the generated code
impactin
Adds the following LLVM_ANNOTATE attributes to helper functions generated
by Hexagon:
1. "helper-to-tcg", to specify that a given helper functions should be
translated, and;
2. "immediate: ..." to make sure immediate arguments to helper
functions remain immediates in the emitted TCG
Simple function for creating Expected<> with nice error messages.
Signed-off-by: Anton Johansson
---
subprojects/helper-to-tcg/include/Error.h | 40 +++
1 file changed, 40 insertions(+)
create mode 100644 subprojects/helper-to-tcg/include/Error.h
diff --git a/subprojects/he
Convert llvm.returnaddress arguments to cpu_[ld|st]*() to undef, causing
the LLVM optmizer to discard the intrinsics. Needed as
llvm.returnadress is not representable in TCG, and usually results from
usage of GETPC() in helper functions.
Signed-off-by: Anton Johansson
---
.../PrepareForOptPass/
Adds a backend pass, taking previously optimized and canonicalized LLVM
IR and for each function:
1. Runs the TcgV register allocator;
2. Iterates over instructions and calls appropriate functions in
TcgEmit.h to emit TCG code.
Signed-off-by: Anton Johansson
---
.../helper-to-tcg/incl
Adds a new LLVM pass that runs early in the pipeline with the goal
of preparing the input module for optimization by doing some early
culling of functions and information gathering.
This commits sets up a new LLVM pass over the IR module and runs it from
the pipeline.
Signed-off-by: Anton Johanss
Adds a translation unit with the sole purpose of handling inter-LLVM
code changes. Instead of littering the code with #ifdefs, most of them
will be limited to llvm-compat.[cpp|h] and a saner compat::*() function
is exposed in its place.
Signed-off-by: Anton Johansson
---
subprojects/helper-to-t
In the LLVM IR module function annotations are stored in one big global
array of strings. Traverse this array and parse the data into a format
more useful for future passes. A map between Functions * and a list of
annotations is exposed.
Signed-off-by: Anton Johansson
---
.../include/FunctionA
Introduces simple end-to-end tests of helper-to-tcg of functions the
translator is expected to handle, any translation failure will result in
a test failure. More test cases to come.
Signed-off-by: Anton Johansson
---
subprojects/helper-to-tcg/meson.build | 2 +
subprojects/helper-to-
Adds a functions to return the current mmu index given tb_flags of the
current translation block. Required by helper-to-tcg in order to
retrieve the mmu index for memory operations without changing the
signature of helper functions.
Signed-off-by: Anton Johansson
---
target/hexagon/cpu.h | 12 +
PHI nodes have no clear analogue in TCG, this commits converts them to
stack accesses using a built-in LLVM transformation.
Signed-off-by: Anton Johansson
---
.../PrepareForTcgPass/PrepareForTcgPass.cpp | 24 +++
1 file changed, 24 insertions(+)
diff --git
a/subprojects/helpe
Iterates over the IR with the goal of converting it to a form closer to
TCG, taking care of IR disparencies between LLVM and TCG. This also
simplifies the backend by containing the bulk of custom IR
transformations, meaning the backend can be as dumb as possible.
Signed-off-by: Anton Johansson
-
Adds a meson option for enabling/disabling helper-to-tcg along with a
CONFIG_* definition.
CONFIG_* will in future commits be used to conditionally include the
helper-to-tcg subproject, and to remove unneeded code/memory when
helper-to-tcg is not in use.
Current meson option is limited to Hexagon
A new translation unit is added with the purpose of containing all code
which emits strings of TCG code. The idea is that maintainence of the
backend will be simpler if all "tcg_*(*)" strings are contained and
wrapped in functions.
Signed-off-by: Anton Johansson
---
.../helper-to-tcg/include/Cm
Modifies meson.build to use helper-to-tcg for automatic translation of
helper functions. Any helper functions with the "helper-to-tcg"
attribute will be automatically translated to TCG.
Order of code generation is changed, and helper functions are always
generated first, for all instructions. He
Adds a cpu_mapping struct to describe, in a declarative fashion, the
mapping between fields in a struct, and a corresponding TCG global. As
such, tcg_global_mem_new() can be automatically called given an array of
cpu_mappings.
This change is not limited to helper-to-tcg, but will be required in
f
Adds new functions to the gvec API for truncating, sign- or zero
extending vector elements. Currently implemented as helper functions,
these may be mapped onto host vector instructions in the future.
For the time being, allows translation of more complicated vector
instructions by helper-to-tcg.
Adds a struct representing everything a LLVM value might map to in TCG,
this includes:
* TCGv (IrValue);
* TCGv_ptr (IrPtr);
* TCGv_env (IrEnv);
* TCGLabel (IrLabel);
* tcg_constant_*() (IrConst);
* 123123ull (IrImmediate);
* intptr_t gvec_vector (IrPtrToOffset).
NOTE: Patch is subj
getelementpointer (GEP) instructions in LLVM IR represent general pointer
arithmetic (struct field access, array indexing, ...). From the
perspective of TCG, three distinct cases are important and are
transformed into pseudo instructions respectively:
* struct accesses whose offset into the str
Signed-off-by: Anton Johansson
---
subprojects/helper-to-tcg/README.md | 265
1 file changed, 265 insertions(+)
create mode 100644 subprojects/helper-to-tcg/README.md
diff --git a/subprojects/helper-to-tcg/README.md
b/subprojects/helper-to-tcg/README.md
new file mo
Temporary vectors in helper-to-tcg generated code are allocated from an
array of bytes in CPUArchState, specified with --temp-vector-block.
This commits adds such a block of memory to CPUArchState, if
CONFIG_HELPER_TO_TCG is set.
Signed-off-by: Anton Johansson
---
target/hexagon/cpu.h | 4
Hi all, this patchset introduces helper-to-tcg, a LLVM based build-time
C to TCG translator, as a QEMU subproject. The purpose of this tool is
to simplify implementation of instructions in TCG by automatically
translating helper functions for a given target to TCG. It may also be
used as a standa
Adds necessary helper functions for mapping LLVM IR onto TCG.
Specifically, helpers corresponding to the bitreverse and funnel-shift
intrinsics in LLVM.
Note: these may be converted to more efficient implementations in the
future, but for the time being it allows helper-to-tcg to support a
wider s
"pseudo" instructions makes it easy to add custom instructions to
LLVM IR in the form of calls to undefined functions. These will be used
in future commits to express functionality present in TCG that is missing
from LLVM IR (certain vector ops.), or to simplify the backend by
collecting similar i
QOL commit, all the various gen_* python scripts take a large set
arguments where order is implicit. Using argparse we also get decent
error messages if a field is missing or too many are added.
Signed-off-by: Anton Johansson
---
target/hexagon/gen_analyze_funcs.py | 6 +++--
target/hexago
Replaces previous calls to tcg_global_mem_new*() with a declarative
global array of cpu_mapping structs. This array can be used to
initialize all TCG globals with one function call from the target, and
may additionally be used from LLVM based tools to map between offsets
into a struct and a mapped
Makes sure gen_slotval() and check_noshuf() remains defined when
helper-to-tcg and idef-parser are both used. gen_slotval() is needed
for creating a TCGv of the slot value fed to helpers (generated
helper-to-tcg code), and check_noshuf() is needed for helper definitions
used as input to helper-to-
Based on the assumption of a cycle free IR, this commit adds a simple
register allocator for emitted values in TCG. The goal of this pass is
to reduce the number of temporaries required in the output code, which
is especially important when dealing with gvec vectors as to not require
very large am
Adds a function pointer to the TCGContext which may be set by targets via
the TARGET_HELPER_DISPATCHER macro. The dispatcher is function
(void *func, TCGTemp *ret, int nargs, TCGTemp **args) -> bool
which allows targets to hook the generation of helper calls in TCG and
take over translation.
Adds a new pass over the LLVM module which runs post-optimization with
the end-goal of:
* culling functions which aren't worth translating;
* canonicalizing the IR to something closer to TCG, and;
* extracting information which may be useful in the backend pass.
This commits sets up a new LL
Transformation of the IR, identity mapping trivial expressions which
would amount to nothing more than a move when emitted as TCG, but is
required in LLVM IR to not break the IR.
Trivial expressions are mapped to a @IdentityMap pseudo instruction
allowing them to be dealt with in a uniform manner
Run a standard LLVM -Os optimization pass, which makes up the bulk of
optimizations in helper-to-tcg.
Signed-off-by: Anton Johansson
---
subprojects/helper-to-tcg/pipeline/Pipeline.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/subprojects/helper-to-tcg/pipeline/Pipeline.c
When producing LLVM IR using clang -O0, a noinline attribute is added.
Remove this attribute to not inhibit future optimization.
Signed-off-by: Anton Johansson
---
.../passes/PrepareForOptPass/PrepareForOptPass.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git
a/subprojects/h
Doubles amount of space allocated for translation blocks. This is
needed, particularly for Hexagon, where a single instruction packet may
consist of up to four vector instructions. If each vector instruction
then gets expanded into gvec operations that utilize a small host vector
size the TB blow
QEMU will start to not rely on implicit creations of containers soon. Make
PPC drc devices follow by explicitly create the container whenever a drc
device is realized, dropping container_get() calls.
No functional change intended.
Cc: Nicholas Piggin
Cc: Daniel Henrique Barboza
Cc: Harsh Prate
On 11/19/24 09:14, Peter Maydell wrote:
On Tue, 19 Nov 2024 at 16:52, Pierrick Bouvier
wrote:
On 11/19/24 02:09, Peter Maydell wrote:
On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier
wrote:
I'm currently reviewing the QEMU Arm documentation, and I have a
question about the status of following
On Fri, Nov 01, 2024 at 06:35:23PM +, Shameerali Kolothum Thodi wrote:
> I have a bare minimum prototype code that works with a pluggable smmuv3.
>
> ...
> -device pxb-pcie,id=pcie.1,bus_nr=2,bus=pcie.0 \
> -device pcie-root-port,id=pcie.port1,bus=pcie.1 \
> -device arm-smmuv3-nested,id=smmuv1,
On 11/19/24 02:54, Peter Maydell wrote:
On Tue, 19 Nov 2024 at 10:09, Peter Maydell wrote:
On Mon, 18 Nov 2024 at 23:33, Pierrick Bouvier wrote:
8.4:
- FEAT_CNTSC, Generic Counter Scaling (hw/timer/sse-counter.c)
This is optional, and we don't implement it yet. (There's an
open ticket for i
Add a helper to fetch a root container (under object_get_root()). Sanity
check on the type of the object.
Signed-off-by: Peter Xu
---
include/qom/object.h | 10 ++
qom/object.c | 10 ++
2 files changed, 20 insertions(+)
diff --git a/include/qom/object.h b/include/qom/ob
The following changes since commit e6459afb1ff4d86b361b14f4a2fc43f0d2b4d679:
Merge tag 'pull-target-arm-20241119' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-11-19
14:23:34 +)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-
On 11/19/2024 3:16 PM, Peter Xu wrote:
On Tue, Nov 19, 2024 at 02:50:40PM -0500, Steven Sistare wrote:
On 11/14/2024 2:04 PM, Peter Xu wrote:
On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote:
On 11/13/2024 4:58 PM, Peter Xu wrote:
On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve
Always explicitly create QEMU system containers upfront.
Root containers will be created when trying to fetch the root object the
1st time. Machine sub-containers will be created only until machine is
being initialized.
Signed-off-by: Peter Xu
---
hw/core/machine.c | 19 ---
qo
On 11/19/24 01:24, Daniel P. Berrangé wrote:
On Mon, Nov 18, 2024 at 09:23:54AM -0800, Pierrick Bouvier wrote:
MacOS and Linux are straightforward, but Windows needs a bit more
details.
Signed-off-by: Pierrick Bouvier
---
docs/about/build-platforms.rst | 4 +-
docs/devel/build-environme
Drop one use of container_get(), instead switch to the explicit function to
create a container.
Signed-off-by: Peter Xu
---
tests/unit/check-qom-proplist.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/unit/check-qom-proplist.c b/tests/unit/check-qom-proplist.c
index
To move towards explicit creations of containers, starting that by
providing a helper for creating container objects.
Signed-off-by: Peter Xu
---
include/qom/object.h | 12
qom/container.c | 18 +++---
2 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/
On 11/19/24 01:29, Daniel P. Berrangé wrote:
On Mon, Nov 18, 2024 at 09:23:57AM -0800, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/devel/build-system.rst | 2 +
docs/how-to/index.rst | 146
docs/index.rst | 1 +
Add a helper to fetch machine containers. Add some sanity check around.
Signed-off-by: Peter Xu
---
include/hw/qdev-core.h | 10 ++
hw/core/qdev.c | 17 +
2 files changed, 27 insertions(+)
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
index 5be984
This series is not for 9.2, but for 10.0. It is intended to replace this
previous patchset:
[PATCH 0/5] QOM: Enforce container_get() to operate on containers only
https://lore.kernel.org/r/20241118221330.3480246-1-pet...@redhat.com
Since it's a different patchset, the versioning starts from
container_get() is going to become strict on not allowing to return a
non-container.
Switch the e500 user to use object_resolve_path_component() explicitly.
Cc: Bharat Bhushan
Cc: qemu-...@nongnu.org
Signed-off-by: Peter Xu
---
hw/pci-host/ppce500.c | 4 ++--
1 file changed, 2 insertions(+), 2
test-qdev-global-props creates a few subprocesses and test things based on
qdev realize(). One thing was overlooked since the start, that anonymous
creations of qdev (then realize() the device) requires the machine object's
presence, as all these devices need to be attached to QOM tree, by default
Now we should be ready to always create containers upfront, meanwhile we
have explicit helpers to fetch either:
- Root containers (object_get_container()), or
- Machine containers (machine_get_container()).
Change all rest container_get() users to use the explicit & fast version of
container
Follow the trend to explicitly create containers, do that for console.c on
"/backend" container.
Cc: Marc-André Lureau
Signed-off-by: Peter Xu
---
ui/console.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/ui/console.c b/ui/console.c
index 5165f17125..36f8c6debb 100644
Provide a macro for the container type across QEMU source tree, rather than
hard code it every time.
Signed-off-by: Peter Xu
---
include/qom/object.h | 1 +
hw/arm/stellaris.c | 2 +-
qom/container.c | 4 ++--
qom/object.c | 4 ++--
4 files changed, 6 insertions(+), 5 deletions(-)
Currently, qdev_get_machine() has a slight misuse on container_get(), as
the helper says "get a container" but in reality the goal is to get the
machine object. It is still a "container" but not strictly.
Note that it _may_ get a container (at "/machine") in our current unit test
of test-qdev-glo
print_mmap() assumes that mmap() receives arguments via memory if
mmap2() is present. s390x (as opposed to s390) does not fit this
pattern: it does not have mmap2(), but mmap() still receives arguments
via memory.
Fix by sharing the detection logic between syscall.c and strace.c.
Cc: qemu-sta...@
On 11/19/24 01:04, Daniel P. Berrangé wrote:
On Mon, Nov 18, 2024 at 09:23:52AM -0800, Pierrick Bouvier wrote:
Signed-off-by: Pierrick Bouvier
---
docs/devel/submitting-a-patch.rst | 14 ++
1 file changed, 14 insertions(+)
diff --git a/docs/devel/submitting-a-patch.rst
b/docs/d
On Mon, Nov 18, 2024 at 06:59:53PM +0100, Eric Auger wrote:
> Looking at your branch I see the following series (marked with cover-letter)
..
> cover-letter: Add RMR WAR for MSI mappings (based on former RMR flat
> mapping and not related to *[PATCH RFCv1 0/7] vfio: Allow userspace
> to
On 11/11/24 09:02, Richard Henderson wrote:
On 11/11/24 06:59, Richard Henderson wrote:
On 10/23/24 16:47, J. Neuschäfer wrote:
This aligns with strace, and is very useful when tracing multi-threaded
programs. The result is the same in single-threaded programs.
See also "-D log.%d -d tid -str
On 11/19/24 15:11, Ilya Leoshkevich wrote:
print_mmap() assumes that mmap() receives arguments via memory if
mmap2() is present. s390x (as opposed to s390) does not fit this
pattern: it does not have mmap2(), but mmap() still receives arguments
via memory.
Fix by special-casing s390x.
Cc: qemu-
On Wed, 13 Nov 2024 09:37:02 +0100
Mauro Carvalho Chehab wrote:
> The GHES migration logic at GED should now support HEST table
> location too.
>
> Increase migration version and change needed to check for both
> ghes_addr_le and hest_addr_le.
Where is the migration version increased? Maybe I'
On 11/19/24 09:34, Paolo Bonzini wrote:
Queued, thanks.
Paolo
Thanks for pulling it Paolo.
Hi Eric,
> -Original Message-
> From: Eric Auger
> Sent: Wednesday, November 20, 2024 4:11 PM
> To: Shameerali Kolothum Thodi
> ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nicol...@nvidia.com;
> ddut...@redhat.com; Linuxarm ; Wangzhou (B
The actual page size (region size for MPU) of armv7m may
smaller than TARGET_PAGE_SIZE (2^5 vs 2^10). So we should
use the actual virtual address to get the phys page address.
Since address_space_rw do not check the region protection, so
if we have some region like [0x0020 ~ 0x003F rw], [0x0040
Libvirt may still use pipes for old file migrations in fd: URI form,
especially when loading old images dumped from Libvirt's compression
algorithms.
In that case, Libvirt needs to compress / uncompress the images on its own
over the migration binary stream, and pipes are passed over to QEMU for
o
On 11/19/24 16:05, Daniel P. Berrangé wrote:
The console interaction that waits for predicted strings uses
readline(), and thus is only capable of waiting for strings
that are followed by a newline.
This is inconvenient when needing to match on some things,
particularly login prompts, or shell p
In some adhoc profiling, it's observed that ahci_irq_lower() can be a hot
path and the type cast might be slow and prone to optimizations.
Considering it's in ODD FIXES stage, we may not expect major time consumed
yet on this on either developing efforts, or reviewing efforts from
maintainers. Ho
On Wed, Nov 20, 2024 at 11:12:51AM -0500, Steven Sistare wrote:
> On 11/20/2024 4:38 AM, Daniel P. Berrangé wrote:
> > On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote:
> > >
> > > This begs the question, should we allow channels to be specified in hmp
> > > migrate
> > > commands a
On Wed, Nov 20, 2024 at 12:45:19PM +0100, Paolo Bonzini wrote:
> Il mar 19 nov 2024, 22:43 Peter Xu ha scritto:
>
> > > The easiest way to check is probably to print the type of every
> > successful
> > > object_dynamic_cast and object_class_dynamic_cast. I suspect the result
> > > will be virtio
The actual page size (region size for MPU) of armv7m may
smaller than TARGET_PAGE_SIZE (2^5 vs 2^10). So we should
use the actual virtual address to get the phys page address.
Signed-off-by: Xiong Nandi
---
system/physmem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/sy
On 11/20/2024 4:38 AM, Daniel P. Berrangé wrote:
On Tue, Nov 19, 2024 at 03:32:55PM -0500, Steven Sistare wrote:
On 11/19/2024 3:16 PM, Peter Xu wrote:
On Tue, Nov 19, 2024 at 02:50:40PM -0500, Steven Sistare wrote:
On 11/14/2024 2:04 PM, Peter Xu wrote:
On Thu, Nov 14, 2024 at 01:36:00PM -05
Hi Shameer,
On 11/20/24 15:16, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Eric Auger
>> Sent: Monday, November 18, 2024 6:10 PM
>> To: Shameerali Kolothum Thodi
>> ; qemu-...@nongnu.org;
>> qemu-devel@nongnu.org
>> Cc: peter.mayd...@linaro.org; j...@nvidia.com; nico
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 65 ++
hw/riscv/microchip_pfsoc.c | 11 ---
hw/riscv/opentitan.c | 4 ++-
hw/riscv/sifive_e.c|
> On 22 Oct 2024, at 15:58, Atish Kumar Patra wrote:
>
> On Mon, Oct 21, 2024 at 6:45 AM Aleksei Filippov
> wrote:
>>
>>
>>
>>> On 11 Oct 2024, at 23:45, Atish Kumar Patra wrote:
>>>
>>> On Thu, Oct 10, 2024 at 5:44 AM Alexei Filippov
>>> wrote:
On 10.10.2024 02:0
On Wed, 13 Nov 2024 09:37:03 +0100
Mauro Carvalho Chehab wrote:
> Create a new property (x-has-hest-addr) and use it to detect if
> the GHES table offsets can be calculated from the HEST address
> (qemu 9.2 and upper) or via the legacy way via an offset obtained
> from the hardware_errors firmwar
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 25 -
include/hw/riscv/boot.h | 3 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff -
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 14 +-
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifi
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. DTB loading now will check if overlapping
to kernel/initrd and report this error.
Verify the patch via running 4GB initramfs on the virt machine.
Changes for v4:
- Update the comments of loading
On Tue, Nov 12, 2024 at 6:05 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/8/24 4:04 AM, Jim Shu wrote:
> > Add a new struct RISCVBootInfo to sync boot information between multiple
> > boot functions.
> >
> > Signed-off-by: Jim Shu
> > ---
> > hw/riscv/boot.c| 65 +
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