Daniel P. Berrangé writes:
> On Thu, Nov 14, 2024 at 01:48:28PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > This replaces use of the constants from the QapiSpecialFeatures
>> > enum, with constants from the auto-generate QapiFeatures enum
>> > in qapi-features.h
>> >
>
Hi Cédric,
>-Original Message-
>From: Cédric Le Goater
>Sent: Friday, November 15, 2024 2:53 PM
>Subject: [PATCH for-9.2] vfio/container: Fix container object destruction
>
>When commit 96b7af4388b3 intoduced a .instance_finalize() handler,
>it did not take into account that the container
When commit 96b7af4388b3 intoduced a .instance_finalize() handler,
it did not take into account that the container was not necessarily
inserted into the container list of the address space. Hence, if
the container object is destroyed, by calling object_unref() for
example, before vfio_address_space
On 15/11/2024 00.30, Jared Rossi wrote:
On 11/14/24 12:47 PM, Thomas Huth wrote:
On 14/11/2024 16.55, Jared Rossi wrote:
On 11/14/24 7:29 AM, Thomas Huth wrote:
While adding the new flexible boot order feature on s390x recently,
we missed to add the "loadparm" property to the scsi-hd and s
On 15/11/2024 01.27, jro...@linux.ibm.com wrote:
From: Jared Rossi
Update documentation to include per-device loadparm support.
Signed-off-by: Jared Rossi
---
docs/system/s390x/bootdevices.rst | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/docs
On 14/11/2024 17.19, jro...@linux.ibm.com wrote:
From: Jared Rossi
Commit bb185de423 ("s390x: Add individual loadparm assignment to
CCW device") allowed boot devices to be assigned a loadparm value independent
of the machine value, however, when no boot devices are defined, the machine
loadparm
With documentation of per-device loadparm behavior during device probing
similar to suggestion here:
https://lore.kernel.org/qemu-devel/20241115002742.3576842-1-jro...@linux.ibm.com/
Reviewed-by: Jared Rossi
On 11/14/24 7:29 AM, Thomas Huth wrote:
While adding the new flexible boot order fea
On 12/11/2024 16:40, Zhang Chen wrote:
> Signed-off-by: Zhang Chen
Reviewed-by: Li Zhijian
> ---
> MAINTAINERS | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 095420f8b0..3f10529d9c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
When the ethernet PHY's compatible string is 'ethernet-phy-id0141.0cc2',
it will be matched with the Marvell driver in Linux instead of the
generic driver. They differ from reading the PHY register17.11 bit which
is for 'Speed and Duplex Resolved' and the value 0 will clear
phydev->link and stop th
On 11/14/24 08:00, Richard Henderson wrote:
Remove force_mmio and place the expression into the IF
expression, behind the short-circuit logic expressions
that might eliminate its computation.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 12
1 file changed, 8 inserti
From: Jared Rossi
Update documentation to include per-device loadparm support.
Signed-off-by: Jared Rossi
---
docs/system/s390x/bootdevices.rst | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/docs/system/s390x/bootdevices.rst
b/docs/system/s390x/bo
On 11/15/24 00:10, Rob Landley wrote:
Seems a _bit_ awkward to do that (and potentially fail on a random new
dependency) just to delete it all again?
That's just how Make works. If it finds that Makefile is old, it first
regenerates Makefile and only then looks at the target. See "How
Makef
On 11/14/24 12:47 PM, Thomas Huth wrote:
On 14/11/2024 16.55, Jared Rossi wrote:
On 11/14/24 7:29 AM, Thomas Huth wrote:
While adding the new flexible boot order feature on s390x recently,
we missed to add the "loadparm" property to the scsi-hd and scsi-cd
devices. This property is require
Apparently because:
../meson.build:1:0: ERROR: Meson version is 0.59.3 but project requires
>=1.5.0
A full log can be found at
/home/landley/qemu/qemu/build/meson-logs/meson-log.txt
/home/landley/qemu/qemu/build/pyvenv/bin/meson setup --reconfigure
/home/landley/qemu/qemu
WARNING: Regeneratin
Rather than handling the MDIO registers as RAM, map them
as unimplemented I/O within the device MR.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-
+Michal for Linux driver
On 5/11/24 23:08, Edgar E. Iglesias wrote:
On Tue, Nov 05, 2024 at 02:04:21PM +0100, Philippe Mathieu-Daudé wrote:
Per the datasheet (reference added in file header, p.9)
'Programming Model' -> 'Register Data Types and Organization':
"The XPS INTC registers are re
On Thu, Nov 14, 2024 at 10:16:41PM +0100, David Hildenbrand wrote:
> On 14.11.24 20:28, Peter Xu wrote:
> > On Thu, Nov 14, 2024 at 10:02:37AM +0100, David Hildenbrand wrote:
> > > On 13.11.24 21:12, Peter Xu wrote:
> > > > On Wed, Nov 13, 2024 at 07:49:44PM +0100, David Hildenbrand wrote:
> > > >
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
In order to keep "exec/ram_addr.h" focused on (target
agnostic) methods related to the ram_addr_t type, move
all (target specific) CPU physical memory API to a new
"sysemu/physmem-target.h" header.
Signed-off-by: Philippe Mathieu-Daudé
Some of
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 5 +++--
hw/net/trace-events | 4
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index e84b4cdd35..bb330a233f 100644
--- a
From: Hao Xiang
* Add test case to start and complete multifd live migration with DSA
offloading enabled.
* Add test case to start and cancel multifd live migration with DSA
offloading enabled.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/qtest/mig
From: Hao Xiang
Create DSA task with operation code DSA_OPCODE_COMPVAL.
Here we create two types of DSA tasks, a single DSA task and
a batch DSA task. Batch DSA task reduces task submission overhead
and hence should be the default option. However, due to the way DSA
hardware works, a DSA batch ta
From: Hao Xiang
* Add a DSA task completion callback.
* DSA completion thread will call the tasks's completion callback
on every task/batch task completion.
* DSA submission path to wait for completion.
* Implement CPU fallback if DSA is not able to complete the task.
Signed-off-by: Hao Xiang
S
Signed-off-by: Yichen Wang
---
scripts/update-linux-headers.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh
index 99a8d9fa4c..9128c7499b 100755
--- a/scripts/update-linux-headers.sh
+++ b/scripts/update-linux
From: Yuan Liu
Signed-off-by: Yuan Liu
Signed-off-by: Yichen Wang
---
.../migration/dsa-zero-page-detection.rst | 290 ++
docs/devel/migration/features.rst | 1 +
2 files changed, 291 insertions(+)
create mode 100644 docs/devel/migration/dsa-zero-page-detecti
From: Hao Xiang
* DSA device open and close.
* DSA group contains multiple DSA devices.
* DSA group configure/start/stop/clean.
Signed-off-by: Hao Xiang
Signed-off-by: Bryan Zhang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 103 +
util/dsa.c | 280
v7
* Rebase on top of f0a5a31c33a8109061c2493e475c8a2f4d022432;
* Fix a bug that will crash QEMU when DSA initialization failed;
* Use a more generalized accel-path to support other accelerators;
* Remove multifd-packet-size in the parameter list;
v6
* Rebase on top of 838fc0a8769d7cc6edfe50451ba4
From: Hao Xiang
Multifd sender path gets an array of pages queued by the migration
thread. It performs zero page checking on every page in the array.
The pages are classfied as either a zero page or a normal page. This
change uses Intel DSA to offload the zero page checking from CPU to
the DSA ac
From: Hao Xiang
Intel DSA offloading is an optional feature that turns on if
proper hardware and software stack is available. To turn on
DSA offloading in multifd live migration by setting:
zero-page-detection=dsa-accel
dsa-accel-path="dsa: dsa:[dsa_dev_path2] ..."
This feature is turned off by
From: Hao Xiang
* Use a safe thread queue for DSA task enqueue/dequeue.
* Implement DSA task submission.
* Implement DSA batch task submission.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
include/qemu/dsa.h | 29 +++
util/dsa.c | 202 ++
From: Hao Xiang
* Test DSA start and stop path.
* Test DSA configure and cleanup path.
* Test DSA task submission and completion path.
Signed-off-by: Bryan Zhang
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
tests/unit/meson.build | 6 +
tests/unit/test-dsa.c | 503 +
From: Hao Xiang
Enable instruction set enqcmd in build.
Signed-off-by: Hao Xiang
Signed-off-by: Yichen Wang
---
meson.build | 14 ++
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
3 files changed, 19 insertions(+)
diff --git a/mes
From: Hao Xiang
* Create a dedicated thread for DSA task completion.
* DSA completion thread runs a loop and poll for completed tasks.
* Start and stop DSA completion thread during DSA device start stop.
User space application can directly submit task to Intel DSA
accelerator by writing to DSA's
All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
---
hw/char/xilinx_uartlite.c | 4
hw/intc/xilinx_intc.c | 4
This series addresses the following issues with EPYC CPU models.
1. Update the L1, L2, L3 cache properties to match the actual hardware (PPR).
This needs to be updated on all the EPYC models.
2. RAS feature bits (SUCCOR, McaOverflowRecov).
3. Add SVM feature bits which are required in nested
On 14.11.24 20:28, Peter Xu wrote:
On Thu, Nov 14, 2024 at 10:02:37AM +0100, David Hildenbrand wrote:
On 13.11.24 21:12, Peter Xu wrote:
On Wed, Nov 13, 2024 at 07:49:44PM +0100, David Hildenbrand wrote:
I think I had precisely that, and I recall you suggested to have it only
after the initial
Paolo Bonzini writes:
> On 11/14/24 18:27, Alex Bennée wrote:
>> Paolo Bonzini writes:
>>
>>> On 11/14/24 16:22, Alex Bennée wrote:
ERROR: Build data file './meson-private/build.dat' references
functions or classes that don't exist. This probably means that it
was generated with
On 14/11/24 19:21, Richard Henderson wrote:
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 28 +++-
include/exec/exec-all.h | 17 -
On 11/14/24 11:56, Pierrick Bouvier wrote:
I tested this change by booting a debian x86_64 image, it works as expected.
I noticed that this change does not come for free (64s before, 82s after - 1.3x). Is that
acceptable?
Well, no. But I didn't notice any change during boot tests. I used hype
On 14/11/24 19:19, Richard Henderson wrote:
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 7 +++
include/exec/exec-all.h | 3 ---
include/exec/ram_addr.h | 1 +
syst
On 11/14/24 12:58, Richard Henderson wrote:
On 11/14/24 11:56, Pierrick Bouvier wrote:
I tested this change by booting a debian x86_64 image, it works as expected.
I noticed that this change does not come for free (64s before, 82s after -
1.3x). Is that
acceptable?
Well, no. But I didn't not
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_LEN. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_LEN0] and s->regs[R_TX_LEN1] are now
unused. Not a concern, this array will soon di
'rxbuf' is the index of the dual port RAM used.
Rename it as 'port_index'.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/xilinx_ethlite.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_eth
rxbuf_ptr() points to the beginning of a (RAM) RX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 40 ++--
1 file changed, 30 insertions(+), 10 deletions(-)
diff --git a/hw/ne
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 5 +++--
hw/net/trace-events | 4
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index e84b4cdd35..bb330a233f 100644
--- a
Add TX_GIE to the TX registers MMIO region.
Before TX_GIE1 was accessed as RAM, with no effect.
Now it is accessed as MMIO, also without any effect.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_CTRL. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_CTRL0] and s->regs[R_TX_CTRL1] are now
unused. Not a concern, this array will soon
Declare TX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3
In order to track access to reserved I/O space, use yet
another UnimplementedDevice covering the whole device
memory range. Mapped with lower priority (-1).
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio
Add TX_CTRL to the TX registers MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3 (prio 0, i/o): ethlite.mdio
81
Rather than using I/O registers for RAM buffer, having to
swap endianness back and forth (because the core memory layer
automatically swaps endiannes for us), declare the buffers
as RAM regions. The "xlnx.xps-ethernetlite" MR doesn't have
any more I/O regions. Remove the now unused s->regs[] array.
Rather than accessing the registers within the mixed RAM/MMIO
region as indexed register, declare a per-port TX_GIE. This
will help to map the RAM as RAM (keeping MMIO as MMIO) in few
commits.
Previous s->regs[R_TX_GIE0] and s->regs[R_TX_GIE1] are now
unused. Not a concern, this array will soon di
Declare RX registers as MMIO region, split it out
of the current mixed RAM/MMIO region.
The memory flat view becomes:
(qemu) info mtree -f
FlatView #0
Root memory region: system
8100-810007e3 (prio 0, i/o): xlnx.xps-ethernetlite
810007e4-810007f3
Having all its address range mapped by subregions,
s->mmio MemoryRegion effectively became a container.
Rename it as 'container' for clarity.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/xilinx_ethlite.c | 16
1 file changed, 8 insertions(+),
For a particular physical address within the EthLite MMIO range,
addr_to_port_index() returns which port is accessed.
txbuf_ptr() points to the beginning of a (RAM) TX buffer
within the device state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite
The current max RX bufsize is set to 0x800. This is
invalid, since it contains the MMIO registers region.
Add the correct definition (valid for both TX & RX,
see datasheet p. 20, Table 11 "XPS Ethernet Lite MAC
Memory Map") and use it.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Philippe Mathie
On Mon, Nov 11, 2024 at 03:55:54PM +, Daniel P. Berrangé wrote:
> In cases where qdev_new() is not being passed a static, const
> string, the caller cannot be sure what type they are instantiating.
> There is a risk that instantiation could fail, if it is an abstract
> type.
>
> Convert such c
Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro;
convert type_init() to DEFINE_TYPES().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 48 +++--
1 file changed, 22 insertions(+), 26 deletions(-)
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index bb330a233f..2b52597f03 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethl
Missing review: patch #19 (new)
Since v1:
- Addressed Edgar review comments
- New patch to map RSVD I/O region (Paolo)
- Added Edgar R-b tags
This is the result of a long discussion with Edgar (started few
years ago!) and Paolo:
https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f681
All these MemoryRegionOps read() and write() handlers are
implemented expecting 32-bit accesses. Clarify that setting
.impl.min/max_access_size fields.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Anton Johansson
---
hw/char/xilinx_uartlite.c | 4
hw/intc/xilinx_intc.c | 4
On Mon, Nov 11, 2024 at 03:55:51PM +, Daniel P. Berrangé wrote:
> In cases where object_new() is not being passed a static, const
> string, the caller cannot be sure what type they are instantiating.
> There is a risk that instantiation could fail, if it is an abstract
> type.
>
> Convert such
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
"ram_addr.h" contains declarations specific to system emulation,
move it under the sysemu/ directory to clarify the API namespace.
Signed-off-by: Philippe Mathieu-Daudé
---
MAINTAINERS | 2 +-
include/exec/cpu-common.h
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/memory.h | 2 +-
include/exec/ram_addr.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
diff --git a/include/exec/memory.h b/include/exe
On Mon, Nov 11, 2024 at 03:55:53PM +, Daniel P. Berrangé wrote:
> qdev_new() has a failure scenario where it will assert() if given
> an abstract type. Callers which are creating qdevs based on user
> input, or unknown/untrusted type names, must manually check the
> result of qdev_class_is_abst
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Move methods related to the ram_addr_t type to
the specific "exec/ram_addr.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-common.h| 56 +---
include/exec/ram_addr.h | 56 ++
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
On Thu, Nov 14, 2024 at 01:36:00PM -0500, Steven Sistare wrote:
> On 11/13/2024 4:58 PM, Peter Xu wrote:
> > On Fri, Nov 01, 2024 at 06:47:50AM -0700, Steve Sistare wrote:
> > > Add the cpr-transfer migration mode. Usage:
> > >qemu-system-$arch -machine anon-alloc=memfd ...
> > >
> > >sta
Use XlnxXpsEthLite typedef, OBJECT_DECLARE_SIMPLE_TYPE macro;
convert type_init() to DEFINE_TYPES().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 48 +++--
1 file changed, 22 insertions(+), 26 deletions(-)
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Move the #endif guard where it belongs to restrict
the cpu_untagged_addr() implementation to user
emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/ta
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Extract all declarations related to 'guest from/to host'
address translation to a new "user/guest-host.h" header.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-all.h| 34 +--
include/exec/cpu_ldst.h | 47 +
Missing review: patch #19 (new)
Since v1:
- Addressed Edgar review comments
- New patch to map RSVD I/O region (Paolo)
- Added Edgar R-b tags
This is the result of a long discussion with Edgar (started few
years ago!) and Paolo:
https://lore.kernel.org/qemu-devel/34f6fe2f-06e0-4e2a-a361-2d662f681
On 13/11/24 15:23, Edgar E. Iglesias wrote:
On Tue, Nov 12, 2024 at 07:10:32PM +0100, Philippe Mathieu-Daudé wrote:
For a particular physical address within the EthLite MMIO range,
addr_to_port_index() returns which port is accessed.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/net/xilinx_et
Found that some of the cache properties are not set correctly for EPYC models.
l1d_cache.no_invd_sharing should not be true.
l1i_cache.no_invd_sharing should not be true.
L2.self_init should be true.
L2.inclusive should be true.
L3.inclusive should not be true.
L3.no_invd_sharing should be true.
Add the CPUID bit indicates that a WRMSR to MSR_FS_BASE, MSR_GS_BASE, or
MSR_KERNEL_GS_BASE is non-serializing.
CPUID_Fn8021_EAX
BitFeature description
1 FsGsKernelGsBaseNonSerializing.
WRMSR to FS_BASE, GS_BASE and KernelGSbase are non-serializing.
Link:
https://www.amd.com/
On Mon, Nov 11, 2024 at 03:55:52PM +, Daniel P. Berrangé wrote:
> Since object_new() will assert(), it should only be used in scenarios
> where the caller knows exactly what type it is asking to be created,
> and can thus be confident in avoiding abstract types.
>
> Enforce this by using a mac
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
---
hw/net/xilinx_ethlite.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c
index bb330a233f..2b52597f03 100644
--- a/hw/net/xilinx_ethlite.c
+++ b/hw/net/xilinx_ethl
On Mon, Nov 11, 2024 at 03:55:50PM +, Daniel P. Berrangé wrote:
> object_new() has a failure scenario where it will assert() if given
> an abstract type. Callers which are creating objects based on user
> input, or unknown/untrusted type names, must manually check the
> result of object_class_i
The addition to ppc/Kconfig is for building this into the
qemu-system-ppc64 binary. The enablement requires the
following command line argument:
-device tpm-tis-spi,tpmdev=tpm0,bus=pnv-spi-bus.4
Signed-off-by: dan tan
---
hw/ppc/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/pp
On Thu, 14 Nov 2024 at 05:51, Daniel P. Berrangé wrote:
>
> Looking at
>
> https://wiki.qemu.org/ChangeLog/9.2
>
> I'm thinking that I'm sure there used to be a table of contents present
> at the top of pages, but none is to be seen. until I eventually
> discover that there's a bare noticabl
On 11/14/24 08:00, Richard Henderson wrote:
v1: 20241009150855.804605-1-richard.hender...@linaro.org
The initial idea was: how much can we do with an intelligent data
structure for the same cost as a linear search through an array?
r~
Richard Henderson (54):
util/interval-tree: Introduce
On Mon, Nov 11, 2024 at 03:55:49PM +, Daniel P. Berrangé wrote:
> Since object_new_with_class() accepts a non-const parameter for
> the class, callers should be prepared for failures from unexpected
> input. Add an Error parameter for this and make callers check.
> If the caller does not alread
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu_ldst.h | 25 -
include/exec/cputlb.h | 26 ++
target/arm/tcg/helper-a64.c |
On Mon, Nov 11, 2024 at 03:55:48PM +, Daniel P. Berrangé wrote:
> @@ -753,7 +761,7 @@ typedef union {
> } qemu_max_align_t;
> #endif
>
> -static Object *object_new_with_type(Type type)
> +static Object *object_new_with_type(Type type, Error **errp)
> {
> Object *obj;
> size_t siz
On Thu, Nov 14, 2024 at 10:02:37AM +0100, David Hildenbrand wrote:
> On 13.11.24 21:12, Peter Xu wrote:
> > On Wed, Nov 13, 2024 at 07:49:44PM +0100, David Hildenbrand wrote:
> > > I think I had precisely that, and I recall you suggested to have it only
> > > after the initial sync. Would work for
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h| 187 +++
include/exec/exec-all.h | 183 --
accel/tc
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-all.h | 23 ---
accel/tcg/cputlb.c | 23 +++
2 files changed, 23 insertions(+), 23 deletio
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
"exec/ram_addr.h" contains system specific declarations.
Restrict its inclusion to sysemu to avoid build errors
when refactoring.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/tcg/mte_helper.c | 2 ++
1 file changed, 2 insertions(+)
Re
On 11/13/24 17:13, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 23 +++
include/exec/exec-all.h | 22 --
target/sparc/mmu_helper.c | 2 +-
3 fi
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 28 +++-
include/exec/exec-all.h | 17 -
accel/tcg/cpu-exec.c| 1 +
3 files cha
On 11/14/24 08:00, Richard Henderson wrote:
We will have a need to flush only the "fast" portion
of the tlb, allowing re-fill from the "full" portion.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/accel
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
Move CPU TLB related methods to "exec/cputlb.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cputlb.h | 7 +++
include/exec/exec-all.h | 3 ---
include/exec/ram_addr.h | 1 +
system/physmem.c| 1 +
4 files changed,
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
abi_ptr is expected to be used in user emulation.
tlb_vaddr_to_host() uses it, but can be used in
system emulation. Replace the type by 'vaddr' which
is equivalent on user emulation but also works on
system.
Signed-off-by: Philippe Mathieu-Daudé
On 11/14/24 08:01, Richard Henderson wrote:
Avoid a lookup to find the node that we have just inserted.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 20a
On 11/14/24 08:01, Richard Henderson wrote:
Link from the fast tlb entry to the interval tree node.
Signed-off-by: Richard Henderson
---
include/exec/tlb-common.h | 2 ++
accel/tcg/cputlb.c| 26 +-
2 files changed, 15 insertions(+), 13 deletions(-)
diff --g
On 11/14/24 08:01, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/rx/cpu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 65a74ce720..c83a582141 100644
--- a/target/rx/cpu.c
+++ b/target/rx
On 11/14/24 08:01, Richard Henderson wrote:
Reuse most of TLBLookupInput between calls to tlb_lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 65 ++
1 file changed, 25 insertions(+), 40 deletions(-)
diff --git a/accel/tcg/cputlb.
On 11/13/24 17:12, Philippe Mathieu-Daudé wrote:
abi_long type is defined in "user/abitypes.h".
Include it in order to avoid when refactoring:
linux-user/aarch64/mte_user_helper.h:30:42: error: unknown type name
‘abi_long’; did you mean ‘u_long’?
30 | void arm_set_mte_tcf0(CPUArchState
On 11/14/24 08:01, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/rx/cpu.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 65a74ce720..c83a582141 100644
--- a/target/rx/cpu.c
+++ b/target/rx
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