Actually it comes in 9.2, not 9.1.
Fixes: 3f98408e2e ("qapi: introduce device-sync-config")
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
qapi/qdev.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/qdev.json b/qapi/qdev.json
index 2a581129c9..25cbcf977b 100644
--- a
Now cs->nr_threads is initialized in qemu_early_init_vcpu() which is
called at the begining of realizef(). Drop the comment of the order
dependcy on qemu_init_vcpu() and hoist code to put it together with
other feature checking.
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 33 ++
Currently cpu->nr_cores and cpu->nr_threads are initialized in
qemu_init_vcpu(), which is called a bit late in *cpu_realizefn() for
each ARCHes.
x86 arch would like to use nr_cores and nr_threads earlier in its
realizefn(). Introduce qemu_early_init_vcpu() and move the
initialization of nr_cores a
Track CPUID_HT in env->features[FEAT_1_EDX] instead of evaluating it
each time in cpu_x86_cpuid(). env->features[] should be set up in cpu's
realizefn() and cpu_x86_cpuid() should be the consumer of it.
Beside, TDX support also depends on it because TDX is going to validate
the feature configurati
... instead of manually set it in cpu_x86_cpuid().
Signed-off-by: Xiaoyao Li
---
target/i386/cpu.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0c5a61ff615..015e085fa66c 100644
--- a/target/i386/cpu.c
+++ b
This series is extracted from TDX QEMU v6[1] series per Paolo's request.
It is originally motivated by x86 TDX to track CPUID_HT in env->features[]
which requires nr_cores and nr_cores being initialized earlier than in
qemu_init_vcpu().
Initialize of nr_cores and nr_threads earlier in x86's cpu_r
On 06.11.24 21:17, Michael S. Tsirkin wrote:
On Wed, Nov 06, 2024 at 02:18:34PM +0300, Vladimir Sementsov-Ogievskiy wrote:
v7: update QAPI version 9.1 -> 9.2
Not like this. ypur patches are merged, pls post a fix patch on top.
Thanks!
Ah, missed this. Ok.
Vladimir Sementsov-Ogievskiy (
Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
system doesn't have 32-bit addressable issue, we just load DTB to the end
of dram in 64-bit system.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 8 ++--
hw/riscv/microchip_pfsoc.c | 4 ++--
hw/riscv/sifive_u.c
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 65 +-
hw/riscv/microchip_pfsoc.c | 12 +++---
hw/riscv/opentitan.c | 5 ++-
hw/riscv/sifive
DTB is placed to the end of memory, so we will check if the start
address of DTB overlaps to the address of kernel/initrd.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c | 25 -
include/hw/riscv/boot.h | 3 +++
2 files changed, 27 insertions(+), 1 deletion(-)
diff -
Support to load DTB after 3GB on RV64 system, so that larger initrd
doesn't be overlapped to DTB. DTB loading now will check if overlapping
to kernel/initrd and report this error.
Verify the patch via running 4GB initramfs on the virt machine.
Changes for v3:
- Change struct RISCVBootInfo from
Hi,
On 11/6/24 8:30 PM, Eugenio Perez Martin wrote:
On Wed, Nov 6, 2024 at 3:33 PM Stefano Garzarella wrote:
On Tue, Nov 05, 2024 at 08:24:17PM +0530, Sahil Siddiq wrote:
Hi,
Thank you for the review.
On 11/5/24 3:06 PM, Stefano Garzarella wrote:
On Mon, Nov 04, 2024 at 09:51:24PM +0530,
On Fri, Nov 8, 2024 at 12:28 AM Peter Xu wrote:
> On Thu, Nov 07, 2024 at 05:56:50PM +0800, yong.hu...@smartx.com wrote:
> > From: Hyman Huang
> >
> > The first iteration's RAMBlock dirty sync can be omitted because QEMU
> > always initializes the RAMBlock's bmap to all 1s by default.
> >
> > Si
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_helper.c | 19 +++
target/riscv/insn_trans/trans_rvh.c.inc | 11 +++
target/riscv/translate.c| 4
4 files changed, 3
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 22 --
target/riscv/vector_helper.c | 16
2 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index bb92f36ba1
From: Alexey Baturo
Hi,
As Pointer Masking is finally ratified, these patches intend to update the
existing code to the final version.
These patches have been submitted previously and I tried to address all the
suggestions, but I'd suggest to review them from the clean slate and then
finally
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h | 8
target/riscv/cpu_bits.h | 4
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 30 ++
target/riscv/pmp.c | 14 +++---
target/riscv/pmp.h | 1
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e80dcd2e6..13b2c56a72 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -200,6 +200,9 @@ const RISCVIsaExtDa
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 5 +++
target/riscv/cpu_helper.c | 74 +++
2 files changed, 79 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 417ff45544..74d7076f5a 100644
--- a/targ
From: Alexey Baturo
Zjpm extension is finally ratified. And it's much simplier compared to the
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo
---
t
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 74d7076f5a..11e3a6d647 100644
--- a/targe
>-Original Message-
>From: Jason Wang
>Sent: Friday, November 8, 2024 12:42 PM
>Subject: Re: [PATCH v4 14/17] intel_iommu: Set default aw_bits to 48 in
>scalable
>modern mode
>
>On Mon, Sep 30, 2024 at 5:30 PM Zhenzhong Duan
>wrote:
>>
>> According to VTD spec, stage-1 page table could
On Mon, Nov 4, 2024 at 2:56 PM Yi Liu wrote:
>
> On 2024/9/30 17:26, Zhenzhong Duan wrote:
> > This gives user flexibility to turn off FS1GP for debug purpose.
> >
> > It is also useful for future nesting feature. When host IOMMU doesn't
> > support FS1GP but vIOMMU does, nested page table on host
On Mon, Sep 30, 2024 at 5:30 PM Zhenzhong Duan wrote:
>
> According to VTD spec, stage-1 page table could support 4-level and
> 5-level paging.
>
> However, 5-level paging translation emulation is unsupported yet.
> That means the only supported value for aw_bits is 48.
>
> So default aw_bits to 4
On Mon, Sep 30, 2024 at 5:30 PM Zhenzhong Duan wrote:
>
> This is used by some emulated devices which caches address
> translation result. When piotlb invalidation issued in guest,
> those caches should be refreshed.
>
> For device that does not implement ATS capability or disable
> it but still c
On Fri, Nov 8, 2024 at 5:33 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 11/7/24 3:31 AM, Jim Shu wrote:
> > Add a new struct RISCVBootInfo to sync boot information between multiple
> > boot functions.
> >
> > Signed-off-by: Jim Shu
> > ---
> > hw/riscv/boot.c| 66 ++
This commit adds a test device for checking memory access. The test
device generates memory regions that covers all the parameter
patterns. With this device, we can check the handling of
reading/writing the MemoryRegion is correct.
Signed-off-by: Tomoyuki HIROSE
---
hw/misc/Kconfig
The previous code ignored 'impl.unaligned' and handled unaligned
accesses as is. But this implementation could not emulate specific
registers of some devices that allow unaligned access such as xHCI
Host Controller Capability Registers.
This commit emulates an unaligned access with multiple aligne
This commit adds a qtest for accessing various memory regions. The
qtest checks the correctness of handling the access to memory regions
by using 'memaccess-testdev'.
Signed-off-by: Tomoyuki HIROSE
---
tests/qtest/memaccess-test.c | 598 +++
tests/qtest/meson.bui
'valid' field in MemoryRegionOps struct indicates how the MemoryRegion
can be accessed by the guest. In the previous code, the 'valid' field
was not specified explicitly. As a result, the CMB area could only be
accessed in units of 4 bytes.
This commit specifies the 'valid' field in MemoryRegionOp
This patch set aims to support unaligned access to xHCI Capability
Registers.
To achieve this, we introduce the emulation of an unaligned access
through multiple aligned accesses. This patch set also adds a test
device and several tests using this device to verify that the
emulation functions corr
According to xHCI spec rev 1.2, unaligned access to xHCI Host
Controller Capability Registers is not prohibited. In addition, the
limit of access size is also unspecified. Actually, some real devices
allow unaligned access and 8-byte access to these registers.
This commit makes it possible to unal
On Mon, Sep 30, 2024 at 5:30 PM Zhenzhong Duan wrote:
>
> From: Clément Mathieu--Drif
>
> Signed-off-by: Clément Mathieu--Drif
> Signed-off-by: Zhenzhong Duan
> ---
Acked-by: Jason Wang
Thanks
Paolo Bonzini writes:
> Avoid looking for Rust dependencies via cmake.
>
> Signed-off-by: Paolo Bonzini
Reviewed-by: Junjie Mao
> ---
> rust/qemu-api-macros/meson.build | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/rust/qemu-api-macros/meson.build
> b/rust/qemu-api-macros/m
On Fri Nov 8, 2024 at 12:18 AM AEST, Peter Maydell wrote:
> On Tue, 5 Nov 2024 at 17:35, Peter Maydell wrote:
> >
> > On Mon, 29 Jul 2024 at 11:11, Cédric Le Goater wrote:
> > >
> > > On 7/26/24 01:52, Nicholas Piggin wrote:
> > > > The POWER8 LPC ISA device irqs all get combined and reported to
On Wed Nov 6, 2024 at 1:50 AM AEST, Michael Tokarev wrote:
> 04.11.2024 03:17, Nicholas Piggin wrote:
> > The HFSCR defines were being encoded as bit masks, but the users
> > expect (and analogous FSCR defines are) bit numbers.
> >
> > Cc: qemu-sta...@nongnu.org
> > Reviewed-by: Richard Henderson
On Wed Nov 6, 2024 at 2:09 AM AEST, Thomas Huth wrote:
> Since commit 786bc2255256, cached asset files are read-only, so now we've
> got to use "read-only=true" in tests that try to use these files directly.
>
> Fixes: 786bc22552 ("tests/functional: make cached asset files read-only")
> Signed-off-
> I will wait for a day or maybe the weekend. I am going to switch to the
> previous
> solution in v2 if there isn't any further objection with a more valid reason.
>
> Thank you very much for the feedback!
>
Welcome. It's now v9.2 soft frozen. I'm also continuing to review your
remaining patch
On Tue, Nov 05, 2024 at 03:36:07PM -0300, Daniel Henrique Barboza wrote:
> [EXTERNAL MAIL]
>
> Hi Ethan,
>
>
> Do you plan to send a new version of this work? It seems to me that we're
> a couple of reviews away from getting it merged.
>
Hi Daniel,
Thanks for checking in! I do plan to send an
Hi Maksim,
On 11/7/24 1:00 PM, Maksim Davydov wrote:
>
>
> On 11/4/24 12:40, Dongli Zhang wrote:
>> QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
>> and kvm_put_msrs() to restore them to KVM. However, there is no support for
>> AMD PMU registers. Currently, has_pmu_v
On Thu, Nov 7, 2024 at 4:32 PM Jim Shu wrote:
>
> Larger initrd image will overlap the DTB at 3GB address. Since 64-bit
> system doesn't have 32-bit addressable issue, we just load DTB to the end
> of dram in 64-bit system.
>
> Signed-off-by: Jim Shu
> ---
> hw/riscv/boot.c| 8 ++
Hi Zhao,
On 11/6/24 11:52 PM, Zhao Liu wrote:
> (+Dapang & Zide)
>
> Hi Dongli,
>
> On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote:
>> Date: Mon, 4 Nov 2024 01:40:17 -0800
>> From: Dongli Zhang
>> Subject: [PATCH 2/7] target/i386/kvm: introduce 'pmu-cap-disabled' to set
>> KVM_
On 11/7/24 3:31 PM, Nicolin Chen wrote:
Hi Eric,
On Thu, Nov 07, 2024 at 12:11:05PM +0100, Eric Auger wrote:
On 11/1/24 05:09, Nicolin Chen wrote:
Hi,
This is a continued discussion following previous month's:
https://lore.kernel.org/qemu-devel/Zvr%2Fbf7KgLN1cjOl@Asurada-Nvidia/
Kernel ch
On 11/7/24 3:31 AM, Jim Shu wrote:
Add a new struct RISCVBootInfo to sync boot information between multiple
boot functions.
Signed-off-by: Jim Shu
---
hw/riscv/boot.c| 66 ++
hw/riscv/microchip_pfsoc.c | 11 ++---
hw/riscv/opentitan
On 11/4/24 12:40, Dongli Zhang wrote:
QEMU uses the kvm_get_msrs() function to save Intel PMU registers from KVM
and kvm_put_msrs() to restore them to KVM. However, there is no support for
AMD PMU registers. Currently, has_pmu_version and num_pmu_gp_counters are
initialized based on cpuid(0xa)
On Thu, 7 Nov 2024 at 16:32, Peter Maydell wrote:
>
> In virtio-net.c we assume that the IP length field in the packet is
> aligned, and we copy its address into a uint16_t* in the
> VirtioNetRscUnit struct which we then dereference later. This isn't
> a safe assumption; it will also result in co
ilable in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20241107
>
> for you to fetch changes up to 27652f9ca9d831c67dd447346c6ee953669255f0:
>
> tests/functional: Convert the RV32
On 11/6/24 6:10 AM, Thomas Huth wrote:
On 05/11/2024 17.42, Jared Rossi wrote:
Hi Thomas, Sebastian,
It looks like this is simply caused by the "is_cdrom" value only ever
being set
to true. I think it is a one-line fix that just makes sure to
initialize the
value to false each time we tr
Hi Eric,
On Thu, Nov 07, 2024 at 12:11:05PM +0100, Eric Auger wrote:
> On 11/1/24 05:09, Nicolin Chen wrote:
> > Hi,
> >
> > This is a continued discussion following previous month's:
> > https://lore.kernel.org/qemu-devel/Zvr%2Fbf7KgLN1cjOl@Asurada-Nvidia/
> >
> > Kernel changes are getting close
Signed-off-by: Titus Rwantare
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 1b25e73578..30480dad7b 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -465,6 +465,7 @@ config NPCM7XX
bool
default y
depends on TCG && ARM
This device has the same register layout as the pca9538, but 4 fewer
gpio pins. This commit lowers the number of pins initialised, and reuses
the pca9538 logic.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/pca_i2c_gpio.c | 18 +++
This patch adds the quanta-gsz-bmc target, a current Google machine of
the day. This machine will be used as a platform to enable features such
as the PECI bmc interface, and Intel eSPI virtual wire interface in
QEMU.
Signed-off-by: Titus Rwantare
---
hw/arm/npcm7xx_boards.c | 160 ++
Makes it more explicit that 16 bit values are being used
Signed-off-by: Titus Rwantare
---
include/qemu/bitops.h | 26 ++
1 file changed, 26 insertions(+)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 2c0a2fe751..05179e3ded 100644
--- a/include/qemu/bi
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Titus Rwantare
---
hw/i2c/core.c | 8 +---
hw/i2c/trace-events | 2 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 4cf30b2c86..d238311776 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/co
This patch series bundles the GPIO sensors previously sent for review:
https://lore.kernel.org/all/20230206194936.168843-1-tit...@google.com
and the GSZ board commit sent here:
https://lore.kernel.org/all/20241007171700.1594342-1-tit...@google.com/
The Quanta GSZ a current Google machine of the d
The PCA6416 is an i2c device with 16 GPIO pins, the PCA9538 has 8 pins.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Hao Wu
Signed-off-by: Titus Rwantare
---
hw/gpio/Kconfig | 5 +
hw/gpio/meson.build | 1 +
hw/gpio/pca_i2c_gpio.c | 391
Am 7. November 2024 09:19:05 UTC schrieb Bernhard Beschow :
>
>
>Am 7. November 2024 07:04:10 UTC schrieb Dmitry Frolov :
>>If pcmc->pci_enabled is false, pcms->pcibus is NULL and is passed
>>to pc_nic_init() where it is being dereferenced.
>>
>>Found making check with enabled sanitizers.
>>
>>S
Am 7. November 2024 09:04:16 UTC schrieb Zhao Liu :
>+Philippe for ISAPC
>
>On Thu, Nov 07, 2024 at 10:04:10AM +0300, Dmitry Frolov wrote:
>> Date: Thu, 7 Nov 2024 10:04:10 +0300
>> From: Dmitry Frolov
>> Subject: [PATCH] hw/i386: fix NULL-dereference
>>
>> If pcmc->pci_enabled is false, pcms
Am 5. November 2024 17:18:13 UTC schrieb Peter Maydell
:
>The 'isapc' machine type has no PCI bus, but pc_nic_init() still
>calls pci_init_nic_devices() passing it a NULL bus pointer. This
>causes the clang sanitizer to complain:
>
>$ ./build/clang/qemu-system-i386 -M isapc
>../../hw/pci/pci.c
On Thu, 31 Oct 2024 at 06:55, Bibo Mao wrote:
>
> With generic cpu reset interface, pc register is entry of FLASH for
> UEFI BIOS. However with direct kernel booting requirement, there is
> little different, pc register of primary cpu is entry address of ELF
> file.
>
> At the same time with requi
Hello!
This PR fixes the path used by swtpm to store its state and now uses a
path under /var/tmp rather than a path local to the test. We ran into
issues on Ubuntu when that path was under /mnt and therefore not
supported by the AppArmor profile of swtpm.
Stefan
The following changes since
Hi Igor,
Many thanks for taking time to reply.
> From: qemu-arm-bounces+salil.mehta=huawei@nongnu.org arm-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Igor
> Mammedov
> Sent: Thursday, November 7, 2024 4:57 PM
> To: Salil Mehta
>
> On Wed, 6 Nov 2024 19:05:15 +
> Sal
On 11/7/2024 11:19 AM, David Hildenbrand wrote:
On 07.11.24 15:04, Steven Sistare wrote:
On 11/7/2024 8:05 AM, David Hildenbrand wrote:
[...]
Do you plan to submit the part of your "tmp" patch that refactors
shm_backend_memory_alloc and defines qemu_shm_alloc? If you want,
I could include it
In `virtio_add_resource` function, the UUID used as a key for
`g_hash_table_insert` was temporary, which could lead to
invalid lookups when accessed later. This patch ensures that
the UUID remains valid by duplicating it into a newly allocated
memory space. The value is then inserted into the hash
On Wed, 6 Nov 2024 at 18:41, Fabiano Rosas wrote:
> What we're thinking is having an initial exchange of information between
> src & dst as soon as migration starts and that would sync the
> capabilities and parameters between both sides. Which would then be
> followed by a channel establishment p
On 11/6/24 18:46, Philippe Mathieu-Daudé wrote:
These devices are only used by the SPARC targets, which are
only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN
definition expand to DEVICE_BIG_ENDIAN (besides, the
DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly
using DEVICE_BIG
On Thu, Nov 07, 2024 at 05:38:26PM +0100, David Hildenbrand wrote:
> > David: why do we need to drop PRIVATE in ramblock flags? I thought it was
> > pretty harmless. I suppose things like qemu_ram_is_shared() will even keep
> > working as before?
> >
> > It looks ok to remove it too, but it adds
The size should always be 8 so hard code that. By coincidience the
incorrect use of sizeof(char *) is 8 on 64 bit hosts, but was caught
by CI testing with i686 as the host.
Reported-by: Michael S. Tsirkin
Closes:
https://lore.kernel.org/qemu-devel/20241104110025-mutt-send-email-...@kernel.org/
S
Hi,
Since now we allocate memory for the key, we should provide the
> `key_destroy_func` when calling g_hash_table_new_full(), otherwise
> this new memory will not be de-allocated.
>
Ack
IIUC it can be null, only if `uuid` was null since glib memory
> API usually terminates the application if me
On Thu, Nov 07, 2024 at 05:35:06PM +0530, Prasad Pandit wrote:
> On Wed, 6 Nov 2024 at 18:41, Fabiano Rosas wrote:
> > What we're thinking is having an initial exchange of information between
> > src & dst as soon as migration starts and that would sync the
> > capabilities and parameters between
On Thu, Nov 07, 2024 at 04:57:46PM +, Daniel P. Berrangé wrote:
> On Thu, Nov 07, 2024 at 11:17:30AM -0500, Peter Xu wrote:
> > On Thu, Nov 07, 2024 at 12:33:17PM +, Daniel P. Berrangé wrote:
> > I'll comment on a few examples above, which I think some of them, even if
> > handshake is read
On 08/10/2024 12.54, David Hildenbrand wrote:
With memory devices, we will have storage attributes for memory that
exceeds the initial ram size. Further, we can easily have memory holes,
for which there (currently) are no storage attributes.
In particular, with memory holes, KVM_S390_SET_CMMA_BI
On Thu, Nov 07, 2024 at 05:02:47PM +0530, Prasad Pandit wrote:
From: Prasad Pandit
While starting a vhost device, updating iotlb entries
via 'vhost_device_iotlb_miss' may return an error.
qemu-kvm: vhost_device_iotlb_miss:
700871,700871: Fail to update device iotlb
Fail device start when
On Tue, 7 Jun 2022 at 00:31, Richard Henderson
wrote:
>
> From: Xiaojuan Yang
>
> This includes:
> - TLBSRCH
> - TLBRD
> - TLBWR
> - TLBFILL
> - TLBCLR
> - TLBFLUSH
> - INVTLB
Hi; running the loongarch functional tests on a build with
the clang undefined-behaviour sanitizer enabled reveals an
at
On Thu, Nov 07, 2024 at 05:09:28PM +0400, Marc-André Lureau wrote:
> Hi Michael, Alex,
>
> Any of you could take this in the next virtio-related PR?
>
> thanks
Sorry, we are past soft freeze. So not unless this is a bugfix.
On 11/4/24 9:48 AM, Richard Henderson wrote:
On 10/30/24 15:25, Paolo Savini wrote:
Thanks for the review Richard.
On 10/30/24 11:40, Richard Henderson wrote:
On 10/29/24 19:43, Paolo Savini wrote:
This patch optimizes the emulation of unit-stride load/store RVV instructions
when the data
On Wed, Nov 6, 2024 at 4:57 AM Kevin Wolf wrote:
> Am 01.11.2024 um 18:36 hat John Snow geschrieben:
> > Various python tests in the "check-python-tox" test case on GitLab have
> > begun failing due to newer package versions. This patch set corrects
> > those issues and also improves the reliabil
On Thu, Nov 07, 2024 at 11:17:30AM -0500, Peter Xu wrote:
> On Thu, Nov 07, 2024 at 12:33:17PM +, Daniel P. Berrangé wrote:
> I'll comment on a few examples above, which I think some of them, even if
> handshake is ready, may still need mgmt layers to involve..
>
> Multifd and postcopy are the
On Wed, 6 Nov 2024 19:05:15 +
Salil Mehta wrote:
> Hi Igor,
>
> Thanks for replying back and the reviews. Please find my replies
> inline.
>
> > From: Igor Mammedov
> > Sent: Wednesday, November 6, 2024 4:08 PM
> > To: Salil Mehta
> >
> > On Wed, 6 Nov 2024 14:45:42 +
> > Salil
On Wed, 6 Nov 2024 12:27:07 +
Jonathan Cameron wrote:
> On Mon, 4 Nov 2024 11:00:59 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Sep 16, 2024 at 06:44:49PM +0100, Jonathan Cameron wrote:
> > > Add a test with 6 nodes to exercise most interesting corner cases of SRAT
> > > and HMAT ge
> Compilation fails for me, on macos / rustc 1.80.1
>
> error[E0369]: binary operation `==` cannot be applied to type
> `&Attribute`
> --> ../rust/qemu-api-macros/src/lib.rs:25:43
> |
> 25 | if input.attrs.iter().any(|attr| attr == &expected) {
> |
On Wed, 6 Nov 2024 at 18:08, Paolo Bonzini wrote:
>
> The following changes since commit 11b8920ed2093848f79f93d106afe8a69a61a523:
>
> Merge tag 'pull-request-2024-11-04' of https://gitlab.com/thuth/qemu into
> staging (2024-11-04 17:37:59 +)
>
> are available in the Git repository at:
>
>
On Thu, Nov 07, 2024 at 01:52:01PM +0100, Dorinda Bassey wrote:
In `virtio_add_resource` function, the UUID used as a key for
`g_hash_table_insert` was temporary, which could lead to
invalid lookups when accessed later. This patch ensures that
the UUID remains valid by duplicating it into a newly
On Thu, Nov 07, 2024 at 09:04:02AM -0500, Steven Sistare wrote:
> On 11/7/2024 8:05 AM, David Hildenbrand wrote:
> > On 06.11.24 21:59, Steven Sistare wrote:
> > > On 11/6/2024 3:41 PM, Peter Xu wrote:
> > > > On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote:
> > > > > On 11/4/2024 4:
On Thu, Nov 07, 2024 at 05:56:50PM +0800, yong.hu...@smartx.com wrote:
> From: Hyman Huang
>
> The first iteration's RAMBlock dirty sync can be omitted because QEMU
> always initializes the RAMBlock's bmap to all 1s by default.
>
> Signed-off-by: Hyman Huang
> ---
> migration/cpu-throttle.c |
The ip_header is not actually guaranteed to be aligned. We attempt to
deal with this in some places such as net_checksum_calculate() by
using stw_be_p and so on to access the fields, but this is not
sufficient to be correct, because even accessing a byte member
within an unaligned struct is undefin
In virtio-net.c we assume that the IP length field in the packet is
aligned, and we copy its address into a uint16_t* in the
VirtioNetRscUnit struct which we then dereference later. This isn't
a safe assumption; it will also result in compilation failures if we
mark the ip_header struct as QEMU_PA
On 07.11.24 15:04, Steven Sistare wrote:
On 11/7/2024 8:05 AM, David Hildenbrand wrote:
On 06.11.24 21:59, Steven Sistare wrote:
On 11/6/2024 3:41 PM, Peter Xu wrote:
On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote:
On 11/4/2024 4:36 PM, David Hildenbrand wrote:
On 04.11.24 21
Daniel P. Berrangé writes:
> On Thu, Nov 07, 2024 at 01:36:49PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
[...]
>> > TL;DR: I think you can re-add the documentation comments to
>> > the Golang code generator, declare the resulting code as being
>> > "MIT-0 AND GPL-2.0-or-la
On 06.11.24 21:59, Steven Sistare wrote:
On 11/6/2024 3:41 PM, Peter Xu wrote:
On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote:
On 11/4/2024 4:36 PM, David Hildenbrand wrote:
On 04.11.24 21:56, Steven Sistare wrote:
On 11/4/2024 3:15 PM, David Hildenbrand wrote:
On 04.11.24 20
This patchset aims to fix some clang undefined-behavior
sanitizer warnings that you see if you run the arm
functional-tests:
Stopping network: ../../net/checksum.c:106:9: runtime error: member
access within misaligned address 0x556aad9b502e for type 'struct ip_header',
which requires 4
On 11/7/2024 11:26 AM, David Hildenbrand wrote:
On 07.11.24 17:02, Steven Sistare wrote:
On 11/7/2024 8:23 AM, David Hildenbrand wrote:
On 06.11.24 21:12, Steven Sistare wrote:
On 11/4/2024 4:36 PM, David Hildenbrand wrote:
On 04.11.24 21:56, Steven Sistare wrote:
On 11/4/2024 3:15 PM, David
On 07.11.24 17:32, Peter Xu wrote:
On Thu, Nov 07, 2024 at 09:04:02AM -0500, Steven Sistare wrote:
On 11/7/2024 8:05 AM, David Hildenbrand wrote:
On 06.11.24 21:59, Steven Sistare wrote:
On 11/6/2024 3:41 PM, Peter Xu wrote:
On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote:
On
On 07.11.24 17:02, Steven Sistare wrote:
On 11/7/2024 8:23 AM, David Hildenbrand wrote:
On 06.11.24 21:12, Steven Sistare wrote:
On 11/4/2024 4:36 PM, David Hildenbrand wrote:
On 04.11.24 21:56, Steven Sistare wrote:
On 11/4/2024 3:15 PM, David Hildenbrand wrote:
On 04.11.24 20:51, David Hil
Hello!
This PR fixes the path used by swtpm to store its state and now uses a
path under /var/tmp rather than a path local to the test. We ran into
issues on Ubuntu when that path was under /mnt and therefore not
supported by the AppArmor profile of swtpm.
Stefan
The following changes since
To avoid AppArmor-related test failures when functional test are run from
somewhere under /mnt, adjust the path to swtpm's state to use an AppArmor-
supported path, such as /var/tmp, which is provided by the python function
tempfile.TemporaryDirectory().
An update to swtpm's AppArmor profile is al
On Thu, 07 Nov 2024 11:31, Paolo Bonzini wrote:
Compilation fails for me, on macos / rustc 1.80.1
error[E0369]: binary operation `==` cannot be applied to type
`&Attribute`
--> ../rust/qemu-api-macros/src/lib.rs:25:43
|
25 | if input.attrs.iter().any(|attr| attr == &expecte
在 2024/10/28 下午8:57, Bibo Mao 写道:
If cpu hotplug is enabled, all possible_cpus is initialized with
arch_id set. For ipi interrupt controller, cpu is searched from
possible_cpus with specified arch_id. However it is possible that
cpu object is not created for offlined cpu.
Here safer check is add
On Thu, 7 Nov 2024 at 16:09, Peter Maydell wrote:
>
> I was trying to track down why one of the functional tests was
> hanging, so I tried running it directly:
>
> UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1
> QEMU_TEST_QEMU_BINARY=build/clang/qemu-system-loongarch64
> PYTHONPATH=./build/clang/
On Thu, Nov 07, 2024 at 12:33:17PM +, Daniel P. Berrangé wrote:
> On Thu, Nov 07, 2024 at 05:35:06PM +0530, Prasad Pandit wrote:
> > On Wed, 6 Nov 2024 at 18:41, Fabiano Rosas wrote:
> > > What we're thinking is having an initial exchange of information between
> > > src & dst as soon as migra
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