Re: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable

> Thank you very much for the suggestion. > > Yes, this works. The PERFCORE is a prerequisite of PERFMON_V2 (according to > Linux kernel source code). > > 1403 static int __init amd_core_pmu_init(void) > 1404 { > 1405 union cpuid_0x8022_ebx ebx; > 1406 u64 even_ctr_mask = 0ULL

Re: [PATCH v3 6/7] qapi/block-core: deprecate block-job-change

Vladimir Sementsov-Ogievskiy writes: > That's a first step to move on newer job-* APIs. > > The difference between block-job-change and job-change is in > find_block_job_locked() vs find_job_locked() functions. What's > different? > > 1. find_block_job_locked() finds only block jobs, whereas >

Re: [PATCH 2/7] target/i386/kvm: introduce 'pmu-cap-disabled' to set KVM_PMU_CAP_DISABLE

(+Dapang & Zide) Hi Dongli, On Mon, Nov 04, 2024 at 01:40:17AM -0800, Dongli Zhang wrote: > Date: Mon, 4 Nov 2024 01:40:17 -0800 > From: Dongli Zhang > Subject: [PATCH 2/7] target/i386/kvm: introduce 'pmu-cap-disabled' to set > KVM_PMU_CAP_DISABLE > X-Mailer: git-send-email 2.43.5 > > The AMD

Re: [PATCH] tests: Adjust path for swtpm state to use path under /var/tmp/

On 11/6/24 19:07, Stefan Berger wrote: From: Stefan Berger To avoid AppArmor-related test failures when functional test are run from somewhere under /mnt, adjust the path to swtpm's state to use an AppArmor- supported path, such as /var/tmp, which is provided by the python function tempfile.Tem

[PATCH] hw/i386: fix NULL-dereference

If pcmc->pci_enabled is false, pcms->pcibus is NULL and is passed to pc_nic_init() where it is being dereferenced. Found making check with enabled sanitizers. Signed-off-by: Dmitry Frolov --- hw/i386/pc_piix.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_

Re: [PATCH] tests/functional: Bump timeouts of functional tests

On 06/11/2024 19.04, Daniel P. Berrangé wrote: On Wed, Nov 06, 2024 at 06:09:46PM +0100, Thomas Huth wrote: When building QEMU with "--enable-debug" and running the tests in parallel with "make -j$(nproc) check-functional", many tests are still timing out due to our conservative timeout settings

[PATCH v2 3/3] hw/riscv: Add the checking if DTB overlaps to kernel or initrd

DTB is placed to the end of memory, so we will check if the start address of DTB overlaps to the address of kernel/initrd. Signed-off-by: Jim Shu --- hw/riscv/boot.c | 24 +++- include/hw/riscv/boot.h | 3 +++ 2 files changed, 26 insertions(+), 1 deletion(-) diff --

[PATCH v2 2/3] hw/riscv: Add a new struct RISCVBootInfo

Add a new struct RISCVBootInfo to sync boot information between multiple boot functions. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 66 ++ hw/riscv/microchip_pfsoc.c | 11 ++--- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_e

[PATCH v2 0/3] Support 64-bit address of initrd

Support to load DTB after 3GB on RV64 system, so that larger initrd doesn't be overlapped to DTB. DTB loading now will check if overlapping to kernel/initrd and report this error. Verify the patch via running 4GB initramfs on the virt machine. Changes for v2: - Add DTB overlapping checking and

[PATCH v2 1/3] hw/riscv: Support to load DTB after 3GB memory on 64-bit system.

Larger initrd image will overlap the DTB at 3GB address. Since 64-bit system doesn't have 32-bit addressable issue, we just load DTB to the end of dram in 64-bit system. Signed-off-by: Jim Shu --- hw/riscv/boot.c| 8 ++-- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c

[PATCH] rust/pl011: Fix range checks for device ID accesses

The peripheral and PrimeCell identification registers of pl011 are located at offset 0xFE0 - 0xFFC. To check if a read falls to such registers, the C implementation checks if the offset-shifted-by-2 (not the offset itself) is in the range 0x3F8 - 0x3FF. Use the same check in the Rust implementatio

Re: [PATCH v2 RFT] cocoa: Remove deprecated CVDisplayLinkCreateWithCGDisplay() calls

On 2024/11/07 7:59, Philippe Mathieu-Daudé wrote: +Phil & Akihiko On 6/11/24 17:50, Paolo Bonzini wrote: When building on macOS 15 we get: ../../ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated: first deprecated in macOS 15.0 - use NSView.displayLink(targe

[PULL 12/12] tests/functional: Convert the RV32-on-RV64 riscv test

From: Thomas Huth A straggler that has been added to the Avocado framework while the conversion to the functional framework was already in progress... Move it over now, too! Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20241105103519.341304-1-t

[PULL 00/12] riscv-to-apply queue

The following changes since commit 63dc36944383f70f1c7a20f6104966d8560300fa: Merge tag 'hw-misc-20241105' of https://github.com/philmd/qemu into staging (2024-11-06 17:28:45 +) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-202411

[PULL 05/12] target/riscv: rvv: Replace VSTART_CHECK_EARLY_EXIT in vext_ldst_us

From: Max Chou Because the real vl (evl) of vext_ldst_us may be different (e.g. vlm.v/vsm.v/etc.), so the VSTART_CHECK_EARLY_EXIT checking function should be replaced by checking evl in vext_ldst_us. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Message-ID: <20240918171412.15010

[PULL 02/12] hw/riscv/riscv-iommu: change 'depth' to int

From: Daniel Henrique Barboza Coverity reports an unsigned overflow when doing: for (; depth-- > 0; ) { When depth = 0 inside riscv_iommu_ctx_fetch(). Building it with a recent GCC the code doesn't actually break with depth = 0, i.e. the comparison "0-- > 0" will exit the loop instead of p

[PULL 09/12] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

From: Max Chou The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou Re

[PULL 01/12] hw/char/sifive_uart: Fix broken UART on big endian hosts

From: Thomas Huth Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit part of the value does not work on big endian hosts. We've got to take the proper detour through an 8-bit variable. Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart characters async") Signed-off-by: Thomas H

[PULL 08/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions

From: Max Chou The unmasked unit-stride fault-only-first load instructions are similar to the unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Message-ID: <

[PULL 11/12] target/riscv/kvm: Update kvm exts to Linux v6.11

From: Quan Zhou Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs. Signed-off-by: Quan Zhou Reviewed-by: Andrew Jones Reviewed-by: Jim Shu Message-ID: Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/targe

[PULL 04/12] target/riscv: Set vdata.vm field for vector load/store whole register instructions

From: Max Chou The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou Reviewed-by: Daniel Henrique Barboza Message-I

[PULL 10/12] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

From: Max Chou In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou Reviewed-by:

[PULL 06/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

From: Max Chou This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store implementation with following optimizations: * Get the page boundary * Probing pages/resolving host memory address at the beginning if possible *

[PULL 07/12] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

From: Max Chou The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Because the vector whole register load/store instructions do not need to handl

[PULL 03/12] hw/riscv/riscv-iommu: fix riscv_iommu_validate_process_ctx() check

From: Daniel Henrique Barboza 'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the 'switch' right before it if 'mode' isn't 0, 8, 9 or 10. 'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32. Reported by Coverity via a "DEADCODE" ticket. Resolves: Coverity CID 1564

OOO for first half

Hi, I would be out of office first half, will connect online post lunch. Regards, Sai Pavan

Re: [PATCH v2 2/4] hw/loongarch/virt: Implement cpu plug interface

On 2024/11/6 下午6:56, Igor Mammedov wrote: On Wed, 30 Oct 2024 09:50:56 +0800 maobibo wrote: Hi Zhao, On 2024/10/29 下午9:37, Zhao Liu wrote: (CC Igor since I want to refer his comment on hotplug design.) Hi Bibo, I have some comments about your hotplug design. [snip] +static void vi

Re: [PATCH v2 1/4] hw/loongarch/virt: Add CPU topology support

On 2024/11/6 下午6:41, Igor Mammedov wrote: On Tue, 29 Oct 2024 21:19:15 +0800 Zhao Liu wrote: Hi Bibo, [snip] +In the CPU topology relationship, When we know the ``socket_id`` ``core_id`` +and ``thread_id`` of the CPU, we can calculate its ``arch_id``: + +``arch_id = (socket_id * S) + (co

[PATCH v2 02/16] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()

Pass vCPU endianness as argument so we can load kernels with different endianness (different from the qemu-system-binary builtin one). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-Id: <20241105130431.225

[PATCH v2 07/16] hw/char/xilinx_uartlite: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-D

[PATCH v2 15/16] tests/functional: Explicit endianness of microblaze assets

The archive used in test_microblaze_s3adsp1800.py (testing a big-endian target) contains a big-endian kernel. Rename using the _BE suffix. Similarly, the archive in test_microblazeel_s3adsp1800 (testing a little-endian target) contains a little-endian kernel. Rename using _LE suffix. These change

[PATCH v2 12/16] target/microblaze: Introduce mo_endian() helper

mo_endian() returns the target endianness, currently static. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 14 ++ 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/target/microblaze/translate.c b/target/microbla

[PATCH v2 11/16] target/microblaze: Set MO_TE once in do_load() / do_store()

All callers of do_load() / do_store() set MO_TE flag. Set it once in the callees. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/translate.c | 36 +++ 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/targ

[PATCH v2 14/16] hw/microblaze: Support various endianness for s3adsp1800 machines

Introduce an abstract machine parent class which defines the 'little_endian' property. Duplicate the current machine, which endian is tied to the binary endianness, to one big endian and a little endian machine; updating the machine description. Keep the current default machine for each binary. 'p

[PATCH v2 03/16] hw/intc/xilinx_intc: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Signed-off-by: Philippe Mathieu-Daudé

[PATCH v2 16/16] tests/functional: Add microblaze cross-endianness tests

Copy/paste the current tests, but call the opposite endianness machines, testing: - petalogix-s3adsp1800-le machine (little-endian CPU) on the qemu-system-microblaze binary (big-endian) - petalogix-s3adsp1800-be machine (big-endian CPU) on the qemu-system-microblazeel binary (little-endian). S

[PATCH v2 10/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

Extract the implicit MO_TE definition in order to replace it by runtime variable in the next commit. Mechanical change using: $ for n in UW UL UQ UO SW SL SQ; do \ sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ $(git grep -l MO_TE$n target/microblaze); \ done Signed-off-by: Philip

[RFC PATCH v2 04/16] hw/net/xilinx_ethlite: Simplify by having configurable endianness

The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the build-system"). I/O endianness access was then clarified in commit d48751ed4f ("xilinx-ethli

[PATCH v2 06/16] hw/timer/xilinx_timer: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness for each machine using the device. Signed-off-by: Philippe Mathieu-Daudé

[PATCH v2 13/16] target/microblaze: Consider endianness while translating code

Consider the CPU ENDI bit, swap instructions when the CPU endianness doesn't match the binary one. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 7 +++ target/microblaze/translate.c | 5 +++-- 2 files changed, 10 insertions(+), 2 de

[PATCH v2 09/16] hw/ssi/xilinx_spips: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-D

[RFC PATCH v2 05/16] hw/timer/xilinx_timer: Allow down to 8-bit memory access

Allow down to 8-bit access, per the datasheet (reference added in previous commit): "Timer Counter registers are accessed as one of the following types: • Byte (8 bits) • Half word (2 bytes) • Word (4 bytes)" Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Acked-by: Al

[PATCH v2 08/16] hw/ssi/xilinx_spi: Make device endianness configurable

Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "little-endian" property to select the device endianness, defaulting to little endian. Set the proper endianness on the single machine using the device. Signed-off-by: Philippe Mathieu-D

[PATCH v2 01/16] hw/microblaze: Restrict MemoryRegionOps are implemented as 32-bit

All these MemoryRegionOps read() and write() handlers are implemented expecting 32-bit accesses. Clarify that setting .impl.min/max_access_size fields. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Message-Id: <20241105130431.22564-8-phi...@linaro.org> --- hw/char/xilinx_ua

[PATCH v2 00/16] hw/microblaze: Allow running cross-endian vCPUs

Since v1: - Make device endianness configurable (Edgar) - Convert more Xilinx devices - Avoid preprocessor #if (Richard) - Add R-b tags Make machines endianness-agnostic, allowing to run a big-endian vCPU on the little-endian 'qemu-system-microblazeel' binary, and a little endian one on the big-en

Re: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable

Hi Zhao, > > You can define dependency like this: > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 3baa95481fbc..99c69ec9f369 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1803,6 +1803,10 @@ static FeatureDep feature_dependencies[] = { > .from = { FEAT_

Re: [PATCH 5/7] target/i386/kvm: reset AMD PMU registers during VM reset

Hi Sandipan, On 11/6/24 1:58 AM, Sandipan Das wrote: [snip] >> @@ -4830,6 +4966,20 @@ static int kvm_get_msrs(X86CPU *cpu) >> case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: >> env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; >> break

Re: linux-user: Add option to run `execve`d programs through QEMU

On Wed, Nov 6, 2024 at 3:30 PM Noah Goldstein wrote: > > On Wed, Nov 6, 2024 at 3:10 PM Richard Henderson > wrote: > > > > On 11/6/24 18:13, Noah Goldstein wrote: > > > Question about impl regarding handling of `-execfd` with/without a > > > program name. > > > > > > 1) `-execfd` + program name

Re: [PATCH v2 RFT] cocoa: Remove deprecated CVDisplayLinkCreateWithCGDisplay() calls

+Phil & Akihiko On 6/11/24 17:50, Paolo Bonzini wrote: When building on macOS 15 we get: ../../ui/cocoa.m:662:14: error: 'CVDisplayLinkCreateWithCGDisplay' is deprecated: first deprecated in macOS 15.0 - use NSView.displayLink(target:selector:), NSWindow.displayLink(target:selector:

Re: [PATCH 5/5] hw/sparc: Mark devices as big-endian

On 06/11/2024 18:46, Philippe Mathieu-Daudé wrote: These devices are only used by the SPARC targets, which are only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE

Re: [PATCH] rust: pl011: fix device id matching

On 6/11/24 18:51, Paolo Bonzini wrote: The offset that is compared against 0x3f8..0x400 is not shifted right. Adjust the pattern matching. Cc: Pierrick Bouvier Cc: Manos Pitsidianakis Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 2 +- 1 file changed, 1 insertion(+),

Re: [PATCH] target/i386: Fix legacy page table walk

On 06/11/2024 15:43, Alexander Graf wrote: Commit b56617bbcb4 ("target/i386: Walk NPT in guest real mode") added logic to run the page table walker even in real mode if we are in NPT mode. That function then determined whether real mode or paging is active based on whether the pg_mode variable

[PATCH v2 8/8] tests/tcg: Add late gdbstub attach test

Add a small test to prevent regressions. Make sure that host_interrupt_signal is not visible to the guest. Signed-off-by: Ilya Leoshkevich --- tests/guest-debug/run-test.py | 15 ++-- tests/tcg/multiarch/Makefile.target| 9 - tests/tcg/multiarch/gdbstub/late-attach.

[PATCH v2 3/8] user: Introduce user/signal.h

gdbstub needs target_to_host_signal(), so move its declaration to a public header. Reviewed-by: Richard Henderson Reviewed-by: Warner Losh Signed-off-by: Ilya Leoshkevich --- bsd-user/signal-common.h | 1 - bsd-user/signal.c | 1 + include/user/signal.h | 23 +

[PATCH v2 5/8] osdep: Introduce qemu_kill_thread()

Add a function for sending signals to individual threads. It does not make sense on Windows, so do not provide an implementation, so that if someone uses it by accident, they will get a linker error. Reviewed-by: Richard Henderson Reviewed-by: Warner Losh Signed-off-by: Ilya Leoshkevich --- in

[PATCH v2 6/8] gdbstub: Allow late attachment

Allow debugging individual processes in multi-process applications by starting them with export QEMU_GDB=/tmp/qemu-%d.sock,suspend=n. Currently one would have to attach to every process to ensure the app makes progress. In case suspend=n is not specified, the flow remains unchanged. If it is speci

[PATCH v2 7/8] docs/user: Document the %d placeholder and suspend=n QEMU_GDB features

Signed-off-by: Ilya Leoshkevich --- docs/user/main.rst | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/docs/user/main.rst b/docs/user/main.rst index 7a126ee8093..8dcb1d90a8b 100644 --- a/docs/user/main.rst +++ b/docs/user/main.rst @@ -50,7 +50,7 @@ Command li

[PATCH v2 1/8] gdbstub: Allow the %d placeholder in the socket path

Just like for QEMU_LOG_FILENAME, replace %d with PID in the GDB socket path. This allows running multi-process applications with, e.g., export QEMU_GDB=/tmp/qemu-%d.sock. Currently this is not possible, since the first process will cause the subsequent ones to fail due to not being able to bind() t

[PATCH v2 2/8] gdbstub: Try unlinking the unix socket before binding

In case an emulated process execve()s another emulated process, bind() will fail, because the socket already exists. So try deleting it. Note that it is not possible to handle this in do_execv(): deleting gdbserver_user_state.socket_path before safe_execve() is not correct, because the latter may

[PATCH v2 0/8] gdbstub: Allow late attachment

v1: https://lore.kernel.org/qemu-devel/20241024200031.80327-1-...@linux.ibm.com/ v1 -> v2: Rebase, fix conflicts with the QEMU_RTSIG_MAP patch. Use qemu_get_thread_id() for %d (Helge, Richard, Warner). Add R-bs, except for the Richard's one on 4/8, since conflict resol

[PATCH v2 4/8] user: Introduce host_interrupt_signal

Attaching to the gdbstub of a running process requires stopping its threads. For threads that run on a CPU, cpu_exit() is enough, but the only way to grab attention of a thread that is stuck in a long-running syscall is to interrupt it with a signal. Reserve a host realtime signal for this, just l

Re: linux-user: Add option to run `execve`d programs through QEMU

On Wed, Nov 6, 2024 at 3:10 PM Richard Henderson wrote: > > On 11/6/24 18:13, Noah Goldstein wrote: > > Question about impl regarding handling of `-execfd` with/without a program > > name. > > > > 1) `-execfd` + program name ie: `qemu -execfd ls -a`. > > 2) `-execfd` without program name i.e: `q

Re: [PULL v2 00/29] Misc HW patches for 2024-11-05

On Tue, 5 Nov 2024 at 23:35, Philippe Mathieu-Daudé wrote: > > The following changes since commit 44a9394b1d272b53306d097d4bc20ff7ad14b159: > > Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into > staging (2024-11-05 14:23:22 +) > > are available in the Git repository

Re: [PULL 0/4] Crypto fixes patches

On Tue, 5 Nov 2024 at 18:42, Daniel P. Berrangé wrote: > > The following changes since commit 44a9394b1d272b53306d097d4bc20ff7ad14b159: > > Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into > staging (2024-11-05 14:23:22 +) > > are available in the Git repository at:

Re: [PATCH V3 01/16] machine: anon-alloc option

On Wed, Nov 06, 2024 at 03:59:23PM -0500, Steven Sistare wrote: > On 11/6/2024 3:41 PM, Peter Xu wrote: > > On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote: > > > On 11/4/2024 4:36 PM, David Hildenbrand wrote: > > > > On 04.11.24 21:56, Steven Sistare wrote: > > > > > On 11/4/2024 3:

Re: linux-user: Add option to run `execve`d programs through QEMU

On 11/6/24 18:13, Noah Goldstein wrote: Question about impl regarding handling of `-execfd` with/without a program name. 1) `-execfd` + program name ie: `qemu -execfd ls -a`. 2) `-execfd` without program name i.e: `qemu -execfd -a`. Do you want to allow both of these? If you want to allow (1)

Re: [PATCH V3 01/16] machine: anon-alloc option

On 11/6/2024 3:41 PM, Peter Xu wrote: On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote: On 11/4/2024 4:36 PM, David Hildenbrand wrote: On 04.11.24 21:56, Steven Sistare wrote: On 11/4/2024 3:15 PM, David Hildenbrand wrote: On 04.11.24 20:51, David Hildenbrand wrote: On 04.11.24

Re: [PATCH V3 01/16] machine: anon-alloc option

On Wed, Nov 06, 2024 at 03:12:20PM -0500, Steven Sistare wrote: > > > On 11/4/2024 4:36 PM, David Hildenbrand wrote: > > On 04.11.24 21:56, Steven Sistare wrote: > > > On 11/4/2024 3:15 PM, David Hildenbrand wrote: > > > > On 04.11.24 20:51, David Hildenbrand wrote: > > > > > On 04.11.24 18:38, S

Re: [PATCH v4 1/2] next-kbd: convert to use qemu_input_handler_register()

On Wed, 6 Nov 2024, Philippe Mathieu-Daudé wrote: On 6/11/24 13:00, BALATON Zoltan wrote: On Wed, 6 Nov 2024, Mark Cave-Ayland wrote: Convert the next-kbd device from the legacy UI qemu_add_kbd_event_handler() function to use qemu_input_handler_register(). Signed-off-by: Mark Cave-Ayland Rev

Re: [PATCH V3 01/16] machine: anon-alloc option

On 11/4/2024 4:36 PM, David Hildenbrand wrote: On 04.11.24 21:56, Steven Sistare wrote: On 11/4/2024 3:15 PM, David Hildenbrand wrote: On 04.11.24 20:51, David Hildenbrand wrote: On 04.11.24 18:38, Steven Sistare wrote: On 11/4/2024 5:39 AM, David Hildenbrand wrote: On 01.11.24 14:47, Ste

Re: [PATCH 4/5] i386/hvf: Raise exception on error setting APICBASE

On Tue, Nov 05, 2024 at 04:57:59PM +0100, Phil Dennis-Jordan wrote: > When setting the APICBASE MSR to an illegal value, the APIC > implementation will return an error. This change forwards that report > to the guest as an exception rather than ignoring it when using the hvf > accelerator. > Revi

Re: [PATCH v2] vhost-user: fix shared object return values

22.10.2024 15:46, Albert Esteve wrote: VHOST_USER_BACKEND_SHARED_OBJECT_ADD and VHOST_USER_BACKEND_SHARED_OBJECT_REMOVE state in the spec that they return 0 for successful operations, non-zero otherwise. However, implementation relies on the return types of the virtio-dmabuf library, with opposit

Re: [PATCH 0/7] hw/cxl: Round up of fixes.

14.10.2024 15:18, Jonathan Cameron via wrote: A mixed bag of fixes that have all been on the list already with the exception of: "hw/pci-bridge: Make pxb_dev_realize_common() return if it succeeded" (so that's the one that needs more eyes). I've tweaked the others to fix typos and correct Fixes

Re: [PATCH v6 45/60] i386/tdx: Don't get/put guest state for TDX VMs

Il mer 6 nov 2024, 14:57 Xiaoyao Li ha scritto: > 8 > --- a/accel/kvm/kvm-all.c > +++ b/accel/kvm/kvm-all.c > @@ -457,7 +457,9 @@ int kvm_create_vcpu(CPUState *cpu) > > cpu->kvm_fd = kvm_fd; > cpu->kvm_state = s; > -cpu->vcpu_dirty = true; > +if (!s

Re: [PATCH v7 15/15] hw/vmapple/vmapple: Add vmapple machine type

On Wed, 6 Nov 2024 at 10:16, Akihiko Odaki wrote: > On 2024/11/06 18:10, Phil Dennis-Jordan wrote: > > > > > > On Wed, 6 Nov 2024 at 08:42, Akihiko Odaki > > wrote: > > > > On 2024/11/06 0:30, Phil Dennis-Jordan wrote: > > > From: Alexander Graf mailto:g

RE: [PATCH 2/3] Fix: Reverse CPUs presence check logic for x86 backward compatability

Hi Igor, Thanks for replying back and the reviews. Please find my replies inline. > From: Igor Mammedov > Sent: Wednesday, November 6, 2024 4:08 PM > To: Salil Mehta > > On Wed, 6 Nov 2024 14:45:42 + > Salil Mehta wrote: > > > Hi Igor, > > > > > From: qemu-arm-bounces+salil.me

Re: [PATCH] vhost: fail device start if iotlb update fails

On Wed, 6 Nov 2024 at 17:31, Stefano Garzarella wrote: > For vhost_set_iotlb_callback() that is true because for now we go to > that label only if the callback is defined, but this is not the case for > hdev->vhost_ops->vhost_dev_start(). > > Anyway if in the future we add a new step that need to

[PATCH] rust: pl011: fix device id matching

The offset that is compared against 0x3f8..0x400 is not shifted right. Adjust the pattern matching. Cc: Pierrick Bouvier Cc: Manos Pitsidianakis Signed-off-by: Paolo Bonzini --- rust/hw/char/pl011/src/device.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rust/hw/char/pl

[PATCH 5/5] hw/sparc: Mark devices as big-endian

These devices are only used by the SPARC targets, which are only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE_BIG_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé -

[PATCH 0/5] hw: Mark architecture specific devices with specific endianness

When a device is only built for an architecture built for a particular endianness, we can simplify the device to not use the "target native endianness" definition and directly use the proper target endianness. Philippe Mathieu-Daudé (5): hw/i386: Mark devices as little-endian hw/tricore: Mark

[PATCH 3/5] hw/m68k: Mark devices as big-endian

These devices are only used by the M68K target, which is only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE_BIG_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé ---

[PATCH 1/5] hw/i386: Mark devices as little-endian

These devices are only used by the X86 targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daud

[PATCH 4/5] hw/openrisc: Mark devices as big-endian

These devices are only used by the OpenRISC target, which is only built as big-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_BIG_ENDIAN (besides, the DEVICE_LITTLE_ENDIAN case isn't tested). Simplify directly using DEVICE_BIG_ENDIAN. Signed-off-by: Philippe Mathieu-Daudé

[PATCH 2/5] hw/tricore: Mark devices as little-endian

These devices are only used by the TriCore target, which is only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Da

Re: [PATCH 0/5] i386/hvf: x2apic support and some small fixes

Hi Roman, Welcome back, and thanks for reviewing these patches! On Wed, 6 Nov 2024 at 16:26, Roman Bolshakov wrote: > On Tue, Nov 05, 2024 at 04:57:55PM +0100, Phil Dennis-Jordan wrote: > > This is a loose collection of patches against the x86 hvf accel. They > > can be applied/pulled independe

Re: [PATCH v4 00/26] E500 Cleanup

Am 5. November 2024 22:55:20 UTC schrieb "Philippe Mathieu-Daudé" : >Hi Bernhard, > >On 3/11/24 14:33, Bernhard Beschow wrote: >> This series is part of a bigger series exploring data-driven machine creation >> using device tree blobs on top of the e500 machines [1]. It contains patches >> to

Re: [PATCH 2/2] hw/sd: Remove legacy sd_enable()

On 9/9/24 16:26, Peter Maydell wrote: On Tue, 3 Sept 2024 at 21:04, Philippe Mathieu-Daudé wrote: sd_enable() was only used by omap_mmc_enable() which got recently removed. Time to remove it. Since the SDState::enable boolean is now always %true, we can remove it and simplify. Signed-off-by:

Re: [PATCH v2] eif: cope with huge section offsets

On Thu, Nov 7, 2024 at 12:12 AM Paolo Bonzini wrote: > > Check for overflow to avoid that fseek() receives a sign-extended value. > > Cc: Dorjoy Chowdhury > Signed-off-by: Paolo Bonzini > --- > include/qemu/osdep.h | 4 > hw/core/eif.c| 4 > 2 files changed, 8 insertions(+) >

Re: [PATCH v7 0/3] vhost-user-blk: live resize additional APIs

On Wed, Nov 06, 2024 at 02:18:34PM +0300, Vladimir Sementsov-Ogievskiy wrote: > v7: update QAPI version 9.1 -> 9.2 Not like this. ypur patches are merged, pls post a fix patch on top. Thanks! > Vladimir Sementsov-Ogievskiy (3): > qdev-monitor: add option to report GenericError from find_devic

Re: linux-user: Add option to run `execve`d programs through QEMU

On Wed, Nov 6, 2024 at 11:53 AM Noah Goldstein wrote: > > On Wed, Nov 6, 2024 at 11:26 AM Richard Henderson > wrote: > > > > On 11/6/24 17:03, Noah Goldstein wrote: > > > On Wed, Nov 6, 2024 at 3:38 AM Richard Henderson > > > wrote: > > >> > > >> On 11/5/24 23:54, Noah Goldstein wrote: > > >

Re: [PATCH v6 10/15] hw/acpi: Generic Port Affinity Structure support

> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c > index 968b654e58..4aa4debf44 100644 > --- a/hw/acpi/aml-build.c > +++ b/hw/acpi/aml-build.c > @@ -1955,6 +1955,19 @@ static void build_append_srat_pci_device_handle(GArray > *table_data, > build_append_int_noprefix(table_data, 0, 12

[PATCH v2] eif: cope with huge section offsets

Check for overflow to avoid that fseek() receives a sign-extended value. Cc: Dorjoy Chowdhury Signed-off-by: Paolo Bonzini --- include/qemu/osdep.h | 4 hw/core/eif.c| 4 2 files changed, 8 insertions(+) diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index fe7c3c5f6

[PATCH] tests: Adjust path for swtpm state to use path under /var/tmp/

From: Stefan Berger To avoid AppArmor-related test failures when functional test are run from somewhere under /mnt, adjust the path to swtpm's state to use an AppArmor- supported path, such as /var/tmp, which is provided by the python function tempfile.TemporaryDirectory(). An update to swtpm's

[PULL v3 00/39] Rust changes for QEMU 9.2 soft freeze

The following changes since commit 11b8920ed2093848f79f93d106afe8a69a61a523: Merge tag 'pull-request-2024-11-04' of https://gitlab.com/thuth/qemu into staging (2024-11-04 17:37:59 +) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream-rust for

Re: [PATCH v5 3/3] qemu-ga: Avoiding freeing line prematurely

On Wed, Nov 6, 2024 at 10:42 AM Dehan Meng wrote: > It's now only freed at the end of the function. > > Signed-off-by: Dehan Meng > --- > qga/commands-linux.c | 7 ++- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/qga/commands-linux.c b/qga/commands-linux.c > index 55c3

[PULL v3 37/39] rust: allow older version of bindgen

Cope with the old version that is provided in Debian 12. --size_t-is-usize is needed on bindgen <0.61.0, and it was removed in bindgen 0.65.0, so check for it in meson.build. --merge-extern-blocks was added in 0.61.0. --formatter rustfmt was added in 0.65.0 and is the default, so remove it. Apa

Re: [PATCH] eif: cope with huge section offsets

On Wed, Nov 6, 2024 at 11:58 PM Paolo Bonzini wrote: > > On Wed, Nov 6, 2024 at 6:54 PM Pierrick Bouvier > wrote: > > > > On 11/6/24 09:49, Paolo Bonzini wrote: > > > On Wed, Nov 6, 2024 at 6:47 PM Pierrick Bouvier > > > wrote: > > > > > >>>for (int i = 0; i < MAX_SECTIONS; ++i) { > > >>

Re: [PATCH v5 1/3] qemu-ga: Add 'Null' check and Redefine 'route'

Best Regards, Konstantin Kostiuk. On Wed, Nov 6, 2024 at 10:41 AM Dehan Meng wrote: > sscanf return values are checked and add 'Null' check for > mandatory parameters. And merged redundant route and > networkroute variables. > > Signed-off-by: Dehan Meng > --- > qga/commands-linux.c | 86

Re: [PATCH] tests/functional: Bump timeouts of functional tests

On Wed, Nov 06, 2024 at 06:09:46PM +0100, Thomas Huth wrote: > When building QEMU with "--enable-debug" and running the tests > in parallel with "make -j$(nproc) check-functional", many tests are > still timing out due to our conservative timeout settings. Bump > the timeouts of the problematic tes

[PULL v2 37/39] rust: allow older version of bindgen

Cope with the old version that is provided in Debian 12. --size_t-is-usize is needed on bindgen <0.61.0, and it was removed in bindgen 0.65.0, so check for it in meson.build. --merge-extern-blocks was added in 0.61.0. --formatter rustfmt was added in 0.65.0 and is the default, so remove it. Apa

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