Re: [PATCH] vhost: fail device start if iotlb update fails

On Tue, 5 Nov 2024 at 16:19, Stefano Garzarella wrote: > VHOST_OPS_DEBUG() is usually used in the error path when calling a > `dev->vhost_ops` callback. In addition vhost_device_iotlb_miss() is > already reporting error through error_report() in the error path, so I > think we can remove this line

Re: [PATCH v7 15/15] hw/vmapple/vmapple: Add vmapple machine type

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: From: Alexander Graf Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device ad

Re: [PATCH v7 12/15] hw/vmapple/cfg: Introduce vmapple cfg region

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: From: Alexander Graf Instead of device tree or other more standardized means, VMApple passes platform configuration to the first stage boot loader in a binary encoded format that resides at a dedicated RAM region in physical address space. This pat

Re: [PATCH v6 0/3] Add support for the RAPL MSRs series

* Igor Mammedov さんが書きました: > On Tue, 5 Nov 2024 08:11:14 +0100 > Christian Horn wrote: > > > - For reading the metrics in the guest, I was tempted to suggest PCP with > > pmda-denki to cover RAPL, but it's right now just reading /sysfs, not > > MSR's. pmda-lmsensors for further sensors offere

Re: [PULL SUBSYSTEM qemu-pseries] pseries: Update SLOF firmware image

Of course, I meant Nick :-) Sorry for the noise. On Wed, 6 Nov 2024, at 15:57, Alexey Kardashevskiy wrote: > The following changes since commit bd4be4d9bd20a252e677239a18b6409ecee98f56: > > MAINTAINERS: Remove myself as reviewer (2024-11-04 10:09:36 +1000) > > are available in the Git reposito

Re: [PATCH v6 09/60] i386/tdx: Initialize TDX before creating TD vcpus

On Wed, Nov 06, 2024 at 10:01:04AM +0800, Xiaoyao Li wrote: > On 11/6/2024 4:51 AM, Edgecombe, Rick P wrote: > > +Tony > > > > On Tue, 2024-11-05 at 01:23 -0500, Xiaoyao Li wrote: > > > +int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) > > > +{ > > > +    X86CPU *x86cpu = X86_CPU(cpu); > > > +

[PULL SUBSYSTEM qemu-pseries] pseries: Update SLOF firmware image

The following changes since commit bd4be4d9bd20a252e677239a18b6409ecee98f56: MAINTAINERS: Remove myself as reviewer (2024-11-04 10:09:36 +1000) are available in the Git repository at: g...@github.com:aik/qemu.git tags/qemu-slof-20241106 for you to fetch changes up to 3866b650d567f79e78d6bd3

Re: [PATCH v7 11/15] hw/vmapple/bdif: Introduce vmapple backdoor interface

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: From: Alexander Graf The VMApple machine exposes AUX and ROOT block devices (as well as USB OTG emulation) via virtio-pci as well as a special, simple backdoor platform device. This patch implements this backdoor platform device to the best of my u

Re: [PATCH v7 10/15] hw/vmapple/aes: Introduce aes engine

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: From: Alexander Graf VMApple contains an "aes" engine device that it uses to encrypt and decrypt its nvram. It has trivial hard coded keys it uses for that purpose. Add device emulation for this device model. Signed-off-by: Alexander Graf Signed-

Re: [PULL 12/65] hw/acpi: Generic Port Affinity Structure support

On Tue, Nov 05, 2024 at 09:06:26AM +, Daniel P. Berrangé wrote: > On Mon, Nov 04, 2024 at 04:06:16PM -0500, Michael S. Tsirkin wrote: > > From: Jonathan Cameron > > > > These are very similar to the recently added Generic Initiators > > but instead of representing an initiator of memory traff

Re: [PULL 23/65] qapi: introduce device-sync-config

On Tue, Nov 05, 2024 at 09:10:07AM +, Daniel P. Berrangé wrote: > On Mon, Nov 04, 2024 at 04:07:00PM -0500, Michael S. Tsirkin wrote: > > From: Vladimir Sementsov-Ogievskiy > > > > Add command to sync config from vhost-user backend to the device. It > > may be helpful when VHOST_USER_SLAVE_CO

Re: [PATCH v7 04/15] hw/display/apple-gfx: Adds configurable mode list

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: This change adds a property 'display_modes' on the graphics device which permits specifying a list of display modes. (screen resolution and refresh rate) The property is an array of a custom type to make the syntax slightly less awkward to use, for e

Re: [PATCH v7 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On 2024/11/06 0:30, Phil Dennis-Jordan wrote: MacOS provides a framework (library) that allows any vmm to implement a paravirtualized 3d graphics passthrough to the host metal stack called ParavirtualizedGraphics.Framework (PVG). The library abstracts away almost every aspect of the paravirtualiz

Re: [PATCH v6 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On 2024/11/05 23:24, Phil Dennis-Jordan wrote: On Tue, 5 Nov 2024 at 09:22, Akihiko Odaki > wrote: On 2024/11/04 0:00, Phil Dennis-Jordan wrote: > MacOS provides a framework (library) that allows any vmm to implement a > paravirtualized 3d gr

Re: [PATCH 12/19] hw/net/xilinx_ethlite: Only expect big-endian accesses

On 11/6/24 00:29, Philippe Mathieu-Daudé wrote: We assumed most guest vCPUs run with the same endianness of the binary. Now we want to swap wrt the vCPU, not the binary. So indeed this patch effectively undo the memory.c swapping (feature). I suppose the better way is to modify memory.c, possib

[QEMU PATCH v10] xen/passthrough: use gsi to map pirq when dom0 is PVH

In PVH dom0, when passthrough a device to domU, QEMU code xen_pt_realize->xc_physdev_map_pirq wants to use gsi, but in current codes the gsi number is got from file /sys/bus/pci/devices//irq, that is wrong, because irq is not equal with gsi, they are in different spaces, so pirq mapping fails. To

Re: [PATCH v3] target-i386: Walk NPT in guest real mode

Hey Mark, On 05.11.24 23:54, Mark Cave-Ayland wrote: Hi Alex, This commit appears to break my WinXP boot test: with this patch applied, attempting to boot WinXP from CDROM fails with SeaBIOS getting stuck early in a boot loop. It is possible to reproduce the issue easily with:   ./build/qe

Re: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE unavailable

Hi Dongli, On Mon, Nov 04, 2024 at 01:40:16AM -0800, Dongli Zhang wrote: > Date: Mon, 4 Nov 2024 01:40:16 -0800 > From: Dongli Zhang > Subject: [PATCH 1/7] target/i386: disable PerfMonV2 when PERFCORE > unavailable > X-Mailer: git-send-email 2.43.5 > > When the PERFCORE is disabled with "-cpu

[PATCH v5 01/11 for v9.2?] i386/cpu: Mark avx10_version filtered when prefix is NULL

In x86_cpu_filter_features(), if host doesn't support AVX10, the configured avx10_version should be marked as filtered regardless of whether prefix is NULL or not. Check prefix before warn_report() instead of checking for have_filtered_features. Cc: qemu-sta...@nongnu.org Fixes: commit bccfb846fd

[PATCH v5 05/11] target/i386/kvm: Save/load MSRs of kvmclock2 (KVM_FEATURE_CLOCKSOURCE2)

MSR_KVM_SYSTEM_TIME_NEW and MSR_KVM_WALL_CLOCK_NEW are bound to kvmclock2 (KVM_FEATURE_CLOCKSOURCE2). Add the save/load support for these 2 MSRs just like kvmclock MSRs. Signed-off-by: Zhao Liu Reviewed-by: Zide Chen --- target/i386/cpu.h | 2 ++ target/i386/kvm/kvm.c | 16 +++

[PATCH v5 10/11] target/i386/kvm: Clean up error handling in kvm_arch_init()

Currently, there're following incorrect error handling cases in kvm_arch_init(): * Missed to handle failure of kvm_get_supported_feature_msrs(). * Missed to return when kvm_vm_enable_disable_exits() fails. * MSR filter related cases called exit() directly instead of returning to kvm_init(). (The

[PATCH v5 07/11] target/i386/confidential-guest: Fix comment of x86_confidential_guest_kvm_type()

Update the comment to match the X86ConfidentialGuestClass implementation. Reported-by: Xiaoyao Li Signed-off-by: Zhao Liu Reviewed-by: Pankaj Gupta Reviewed-by: Zide Chen --- target/i386/confidential-guest.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/confi

[PATCH v5 08/11] target/i386/kvm: Clean up return values of MSR filter related functions

Before commit 0cc42e63bb54 ("kvm/i386: refactor kvm_arch_init and split it into smaller functions"), error_report() attempts to print the error code from kvm_filter_msr(). However, printing error code does not work due to kvm_filter_msr() returns bool instead int. 0cc42e63bb54 fixed the error by r

[PATCH v5 02/11] target/i386/kvm: Add feature bit definitions for KVM CPUID

Add feature definitions for KVM_CPUID_FEATURES in CPUID ( CPUID[4000_0001].EAX and CPUID[4000_0001].EDX), to get rid of lots of offset calculations. Signed-off-by: Zhao Liu Reviewed-by: Zide Chen --- v3: Resolved a rebasing conflict. v2: Changed the prefix from CPUID_FEAT_KVM_* to CPUID_KVM_*. (

[PATCH v5 06/11] target/i386/kvm: Drop workaround for KVM_X86_DISABLE_EXITS_HTL typo

The KVM_X86_DISABLE_EXITS_HTL typo has been fixed in commit 77d361b13c19 ("linux-headers: Update to kernel mainline commit b357bf602"). Drop the related workaround. Signed-off-by: Zhao Liu Reviewed-by: Zide Chen --- target/i386/kvm/kvm.c | 5 + 1 file changed, 1 insertion(+), 4 deletions(-

[PATCH v5 04/11] target/i386/kvm: Only save/load kvmclock MSRs when kvmclock enabled

MSR_KVM_SYSTEM_TIME and MSR_KVM_WALL_CLOCK are attached with the (old) kvmclock feature (KVM_FEATURE_CLOCKSOURCE). So, just save/load them only when kvmclock (KVM_FEATURE_CLOCKSOURCE) is enabled. Signed-off-by: Zhao Liu Reviewed-by: Zide Chen --- target/i386/kvm/kvm.c | 12 1 file

[PATCH v5 00/11] i386: miscellaneous cleanup

Hi Paolo and all, Is it necessary to include the first patch (AVX10 cleanup/fix) in v9.2? Others are for v10.0. Compared with v4 [1], * patch 1 (AVX10 fix) and patch 9 (RAPL cleanup) are newly added. * rebased on commit 9a7b0a8618b1 ("Merge tag 'pull-aspeed-20241104' of https://github.com/l

[PATCH v5 09/11] target/i386/kvm: Return -1 when kvm_msr_energy_thread_init() fails

It is common practice to return a negative value (like -1) to indicate an error, and other functions in kvm_arch_init() follow this style. To avoid confusion (sometimes returned -1 indicates failure, and sometimes -1, in a same function), return -1 when kvm_msr_energy_thread_init() fails. Signed-

[PATCH v5 03/11] target/i386/kvm: Remove local MSR_KVM_WALL_CLOCK and MSR_KVM_SYSTEM_TIME definitions

These 2 MSRs have been already defined in kvm_para.h (standard-headers/ asm-x86/kvm_para.h). Remove QEMU local definitions to avoid duplication. Signed-off-by: Zhao Liu Reviewed-by: Xiaoyao Li Reviewed-by: Zide Chen --- target/i386/kvm/kvm.c | 3 --- 1 file changed, 3 deletions(-) diff --git

[PATCH v5 11/11] target/i386/kvm: Replace ARRAY_SIZE(msr_handlers) with KVM_MSR_FILTER_MAX_RANGES

kvm_install_msr_filters() uses KVM_MSR_FILTER_MAX_RANGES as the bound when traversing msr_handlers[], while other places still compute the size by ARRAY_SIZE(msr_handlers). In fact, msr_handlers[] is an array with the fixed size KVM_MSR_FILTER_MAX_RANGES, so there is no difference between the two

Re: [PATCH v5 0/9] Introduce SMP Cache Topology

Hi Philippe, On Tue, Nov 05, 2024 at 10:54:07PM +, Philippe Mathieu-Daudé wrote: > Date: Tue, 5 Nov 2024 22:54:07 + > From: Philippe Mathieu-Daudé > Subject: Re: [PATCH v5 0/9] Introduce SMP Cache Topology > > Hi Zhao, > > On 1/11/24 09:33, Zhao Liu wrote: > > Hi Paolo, > > > > This is

Re: [PATCH v3 5/5] hw/loongarch/virt: Enable cpu hotplug feature on virt machine

On 2024/11/5 下午9:58, Igor Mammedov wrote: On Mon, 4 Nov 2024 14:34:35 +0800 Bibo Mao wrote: On virt machine, enable CPU hotplug feature has_hotpluggable_cpus. For hot-added CPUs after power on, interrupt pin of extioi and ipi interrupt controller need connect to pins of new CPU. Also chan

Re: [PATCH v6 09/60] i386/tdx: Initialize TDX before creating TD vcpus

On 11/6/2024 4:51 AM, Edgecombe, Rick P wrote: +Tony On Tue, 2024-11-05 at 01:23 -0500, Xiaoyao Li wrote: +int tdx_pre_create_vcpu(CPUState *cpu, Error **errp) +{ +    X86CPU *x86cpu = X86_CPU(cpu); +    CPUX86State *env = &x86cpu->env; +    g_autofree struct kvm_tdx_init_vm *init_vm = NULL; + 

Re: [PATCH v6 13/60] i386/tdx: Validate TD attributes

On 11/6/2024 4:56 AM, Edgecombe, Rick P wrote: On Tue, 2024-11-05 at 01:23 -0500, Xiaoyao Li wrote: -static void setup_td_guest_attributes(X86CPU *x86cpu) +static int tdx_validate_attributes(TdxGuest *tdx, Error **errp) +{ +    if ((tdx->attributes & ~tdx_caps->supported_attrs)) { +    e

Re: [PATCH 2/2] hw/display: check frame buffer can hold blob

On 11/4/24 19:53, Alex Bennée wrote: > Coverity reports (CID 1564769, 1564770) that we potentially overflow > by doing some 32x32 multiplies for something that ends up in a 64 bit > value. Fix this by casting the first input to uint64_t to ensure a 64 > bit multiply is used. > > While we are at

Re: [PATCH 1/2] hw/display: factor out the scanout blob to fb conversion

On 11/4/24 19:53, Alex Bennée wrote: > There are two identical sequences of a code doing the same thing that > raise warnings with Coverity. Before fixing those issues lets factor > out the common code into a helper function we can share. > > Signed-off-by: Alex Bennée > Cc: Dmitry Osipenko > --

Re: [PATCH v4 1/9] target/riscv: fix henvcfg potentially containing stale bits

On Wed, Oct 30, 2024 at 6:57 PM Clément Léger wrote: > > > > On 23/10/2024 04:51, Alistair Francis wrote: > > On Mon, Oct 21, 2024 at 7:30 PM Clément Léger wrote: > >> > >> > >> > >> On 21/10/2024 02:46, Alistair Francis wrote: > >>> On Fri, Oct 18, 2024 at 12:55 AM Clément Léger > >>> wrote: >

Re: [PATCH] tests/functional: Convert the RV32-on-RV64 riscv test

On Tue, Nov 5, 2024 at 8:36 PM Thomas Huth wrote: > > A straggler that has been added to the Avocado framework while the > conversion to the functional framework was already in progress... > Move it over now, too! > > Signed-off-by: Thomas Huth Thanks! Applied to riscv-to-apply.next Alistair

Re: linux-user: Add option to run `execve`d programs through QEMU

On Tue, Nov 5, 2024 at 5:48 PM Noah Goldstein wrote: > > On Tue, Nov 5, 2024 at 5:37 AM Richard Henderson > wrote: > > > > On 10/30/24 14:10, Noah Goldstein wrote: > > > The new option '-qemu-children' makes it so that on `execve` the child > > > process will be launch by the same `qemu` executab

Re: [PATCH 4/8] user: Introduce host_interrupt_signal

On Tue, Nov 5, 2024 at 3:49 PM Ilya Leoshkevich wrote: > On Tue, 2024-11-05 at 22:30 +, Richard Henderson wrote: > > On 11/5/24 15:50, Ilya Leoshkevich wrote: > > > On Tue, 2024-11-05 at 08:39 -0700, Warner Losh wrote: > > > > On Thu, Oct 24, 2024 at 2:00 PM Ilya Leoshkevich > > > > > > > >

Re: [PATCH] tests/functional: Convert the RV32-on-RV64 riscv test

On Tue, Nov 5, 2024 at 8:36 PM Thomas Huth wrote: > > A straggler that has been added to the Avocado framework while the > conversion to the functional framework was already in progress... > Move it over now, too! > > Signed-off-by: Thomas Huth Sorry about that! Reviewed-by: Alistair Francis

Re: [PULL 00/50] riscv-to-apply queue

On Tue, Nov 5, 2024 at 5:45 PM Michael Tokarev wrote: > > 05.11.2024 01:57, Alistair Francis wrote: > > >>> RISC-V PR for 9.2 > >>> > >>> * Fix an access to VXSAT > >>> * Expose RV32 cpu to RV64 QEMU > >>> * Don't clear PLIC pending bits on IRQ lowering > >>> * Make PLIC zeroth priority register r

Re: linux-user: Add option to run `execve`d programs through QEMU

On Tue, Nov 5, 2024 at 5:37 AM Richard Henderson wrote: > > On 10/30/24 14:10, Noah Goldstein wrote: > > The new option '-qemu-children' makes it so that on `execve` the child > > process will be launch by the same `qemu` executable that is currently > > running along with its current commandline

Re: [PULL 04/50] target/riscv: Correct SXL return value for RV32 in RV64 QEMU

On Tue, Nov 5, 2024 at 5:27 PM Michael Tokarev wrote: > > 31.10.2024 06:52, Alistair Francis wrote: > > From: TANG Tiancheng > ... > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 1619c3acb6..a63a29744c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -709

Re: [PATCH 2/2] target/riscv/kvm: Update kvm exts to Linux v6.11

On Tue, Sep 24, 2024 at 10:57 PM wrote: > > From: Quan Zhou > > Add support for a few Zc* extensions, Zimop, Zcmop and Zawrs. > > Signed-off-by: Quan Zhou Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/kvm/kvm-cpu.c | 7 +++ > 1 file changed, 7 insertions(+) > > di

Re: [PATCH 12/19] hw/net/xilinx_ethlite: Only expect big-endian accesses

On 5/11/24 14:18, Paolo Bonzini wrote: On 11/5/24 14:04, Philippe Mathieu-Daudé wrote: The Xilinx 'ethlite' device was added in commit b43848a100 ("xilinx: Add ethlite emulation"), being only built back then for a big-endian MicroBlaze target (see commit 72b675caac "microblaze: Hook into the bui

[PULL v2 01/29] target/microblaze: Alias CPU endianness property as 'little-endian'

Alias the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-2-phi...@linaro.org> Reviewed-by: Edgar E. Iglesias Message-I

[PULL v2 00/29] Misc HW patches for 2024-11-05

The following changes since commit 44a9394b1d272b53306d097d4bc20ff7ad14b159: Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into staging (2024-11-05 14:23:22 +) are available in the Git repository at: https://github.com/philmd/qemu.git tags/hw-misc-202

Re: [PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

On Tue, Nov 05, 2024 at 11:18:31PM +, Philippe Mathieu-Daudé wrote: > On 5/11/24 23:01, Philippe Mathieu-Daudé wrote: > > Hi Edgar, > > > > On 5/11/24 23:54, Edgar E. Iglesias wrote: > > > On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wrote: > > > > Rename the 'endian' prope

Re: [PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

On 5/11/24 23:01, Philippe Mathieu-Daudé wrote: Hi Edgar, On 5/11/24 23:54, Edgar E. Iglesias wrote: On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wrote: Rename the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and

Re: [PATCH 12/19] hw/net/xilinx_ethlite: Only expect big-endian accesses

On Tue, Nov 05, 2024 at 02:04:24PM +0100, Philippe Mathieu-Daudé wrote: > The Xilinx 'ethlite' device was added in commit b43848a100 > ("xilinx: Add ethlite emulation"), being only built back > then for a big-endian MicroBlaze target (see commit 72b675caac > "microblaze: Hook into the build-system"

Re: [PATCH 08/19] hw/microblaze: Propagate CPU endianness to microblaze_load_kernel()

On Tue, Nov 05, 2024 at 02:04:20PM +0100, Philippe Mathieu-Daudé wrote: > Pass vCPU endianness as argument so we can load kernels > with different endianness (different from the qemu-system-binary > builtin one). Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- >

Re: [PATCH 11/19] hw/timer/xilinx_timer: Allow down to 8-bit memory access

On Tue, Nov 05, 2024 at 02:04:23PM +0100, Philippe Mathieu-Daudé wrote: > Allow down to 8-bit access, per the datasheet (reference added > in previous commit): > > "Timer Counter registers are accessed as one of the following types: > • Byte (8 bits) > • Half word (2 bytes) > • Word (4 byte

Re: [PATCH 10/19] hw/timer/xilinx_timer: Only expect big-endian accesses

On Tue, Nov 05, 2024 at 02:04:22PM +0100, Philippe Mathieu-Daudé wrote: > Per the datasheet (reference added in file header, p.10): > 'Register Data Types and Organization': > > "The XPS Timer/Counter registers are organized as big-endian data." Haven't checked but pretty sure this will break t

Re: [PATCH 09/19] hw/intc/xilinx_intc: Only expect big-endian accesses

On Tue, Nov 05, 2024 at 02:04:21PM +0100, Philippe Mathieu-Daudé wrote: > Per the datasheet (reference added in file header, p.9) > 'Programming Model' -> 'Register Data Types and Organization': > > "The XPS INTC registers are read as big-endian data" Hi Phil, Some of these devices exist in

Re: [PATCH qemu 05/10] hw/cxl: Check the length of data requested fits in get_log()

On Fri, Nov 01, 2024 at 01:39:12PM +, Jonathan Cameron wrote: > Checking offset + length is of no relevance when verifying the CEL > data will fit in the mailbox payload. Only the length is is relevant. s/is is/is/ > > Note that this removes a potential overflow. > > Reported-by: Esifiel > S

Re: [PATCH v4 00/26] E500 Cleanup

Hi Bernhard, On 3/11/24 14:33, Bernhard Beschow wrote: This series is part of a bigger series exploring data-driven machine creation using device tree blobs on top of the e500 machines [1]. It contains patches to make this exploration easier which are also expected to provide value in themselves

[PULL 16/29] hw/i2c/mpc_i2c: Convert DPRINTF to trace events for register access

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Acked-by: Corey Minyard Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-12-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/mpc_i2c.c| 9 + hw/i2c/trace-events | 5 + 2 files changed, 10

Re: [PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

Hi Edgar, On 5/11/24 23:54, Edgar E. Iglesias wrote: On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wrote: Rename the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Hi Phil, Unfortunately, t

Re: [PATCH 06/19] hw/microblaze: Fix MemoryRegionOps coding style

On Tue, Nov 05, 2024 at 02:04:18PM +0100, Philippe Mathieu-Daudé wrote: > Fix few MemoryRegionOps style before adding new fields > in the following commits. Wasn't aware of this style rule :-) Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/char/xilinx_ua

Re: [PATCH 05/19] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro

On Tue, Nov 05, 2024 at 02:04:17PM +0100, Philippe Mathieu-Daudé wrote: > Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the > class_init() handler. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/microblaze/petalogix_s3adsp1800_mmu.c | 17

[PULL 14/29] hw/ppc/e500: Add missing device tree properties to i2c controller node

From: Bernhard Beschow When compiling a decompiled device tree blob created with dumpdtb, dtc complains with: /soc@e000/i2c@3000: incorrect #address-cells for I2C bus /soc@e000/i2c@3000: incorrect #size-cells for I2C bus Fix this by adding the missing device tree properties. Review

Re: [PATCH 03/19] hw/microblaze/s3adsp1800: Explicit CPU endianness

On Tue, Nov 05, 2024 at 02:04:15PM +0100, Philippe Mathieu-Daudé wrote: > By default the machine's CPU endianness is 'big' order > ('little-endian' property set to %false). > > This corresponds to the default when this machine was added; > see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800

Re: [PATCH 04/19] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio

On Tue, Nov 05, 2024 at 02:04:16PM +0100, Philippe Mathieu-Daudé wrote: > The machine datasheet mentions the GPIO device as 'xps_gpio'. > Rename it accordingly to easily find its documentation. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/microblaze/pet

[PULL 24/29] hw/sd/sdhci: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-21-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/sd/sdhci.c | 62 +-- 1 file changed, 26 insertions(+), 36 d

[PULL 04/29] hw/microblaze/s3adsp1800: Rename unimplemented MMIO region as xps_gpio

The machine datasheet mentions the GPIO device as 'xps_gpio'. Rename it accordingly to easily find its documentation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-5-phi...@linaro.org> --- hw/microblaze/petalo

[PULL 23/29] hw/ppc/mpc8544_guts: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-19-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/mpc8544_guts.c | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git

Re: [PATCH 13/19] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx

On Tue, Nov 5, 2024 at 11:07 PM Philippe Mathieu-Daudé wrote: > > Extract the implicit MO_TE definition in order to replace > it by runtime variable in the next commit. > > Mechanical change using: > > $ for n in UW UL UQ UO SW SL SQ; do \ > sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \ >

Re: [PATCH 02/19] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu

On Tue, Nov 05, 2024 at 02:04:14PM +0100, Philippe Mathieu-Daudé wrote: > The petalogix-ml605 machine was explicitly added as little-endian only > machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU > little-endian ref design"). Mark the big-endian version as deprecated. > > When t

Re: [PATCH v3] target-i386: Walk NPT in guest real mode

On 21/09/2024 09:57, Alexander Graf wrote: When translating virtual to physical address with a guest CPU that supports nested paging (NPT), we need to perform every page table walk access indirectly through the NPT, which we correctly do. However, we treat real mode (no page table walk) special

Re: [PATCH v2] hw/riscv: fix build error with clang

On 5/11/24 05:29, Pierrick Bouvier wrote: Thanks for the review. Feel free to pull the patch in your next PR, so it can be available for release 9.2. Regards, Pierrick On 11/4/24 18:37, Alistair Francis wrote: On Tue, Nov 5, 2024 at 8:23 AM Pierrick Bouvier wrote: Introduced in 0c54ac, "h

Re: [PATCH 01/19] target/microblaze: Rename CPU endianness property as 'little-endian'

On Tue, Nov 05, 2024 at 02:04:13PM +0100, Philippe Mathieu-Daudé wrote: > Rename the 'endian' property as 'little-endian' because the 'ENDI' > bit is set when the endianness is in little order, and unset in > big order. Hi Phil, Unfortunately, these properties are not only QEMU internal these got

[PULL 13/29] hw/ppc/e500: Remove unused "irqs" parameter

From: Bernhard Beschow Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-5-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500

[PULL 26/29] hw/i2c/smbus_eeprom: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Acked-by: Corey Minyard Message-ID: <20241103133412.73536-23-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/smbus_eeprom.c | 19 --- 1 file changed, 8 insertions(+), 11 d

Re: [PATCH v5 0/9] Introduce SMP Cache Topology

Hi Zhao, On 1/11/24 09:33, Zhao Liu wrote: Hi Paolo, This is my v5, if you think it's okay, could this feature get the final merge? (Before the 9.2 cycle ends) :-) --- Zhao Liu (8): i386/cpu: Don't enumerate the "invalid" CPU topology level hw/core: Make CPU topology enumeration arch-

[PULL 11/29] hw/core: Add a helper to check the cache topology level

From: Zhao Liu Currently, we have no way to expose the arch-specific default cache model because the cache model is sometimes related to the CPU model (e.g., i386). Since the user might configure "default" level, any comparison with "default" is meaningless before the machine knows the specific

[PULL 18/29] hw/pci-host/ppce500: Reuse TYPE_PPC_E500_PCI_BRIDGE define

From: Bernhard Beschow Prefer a macro rather than a string literal when instantiaging device models. Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-14-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/ppce500.c | 2 +- 1 f

[PULL 15/29] hw/ppc/mpc8544_guts: Populate POR PLL ratio status register

From: Bernhard Beschow Populate this read-only register with some arbitrary values which avoids U-Boot's get_clocks() to hang(). Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-11-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/pp

[PULL 25/29] hw/block/pflash_cfi01: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Reviewed-by: Kevin Wolf Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-22-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 21 - 1 file changed, 8 insertions(+),

[PULL 27/29] hw/rtc/ds1338: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-24-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/rtc/ds1338.c | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/hw/rtc/ds1338.c b/hw/rtc/ds1338.c i

[PULL 03/29] hw/microblaze/s3adsp1800: Explicit CPU endianness

By default the machine's CPU endianness is 'big' order ('little-endian' property set to %false). This corresponds to the default when this machine was added; see commits 6a8b1ae2020 "microblaze: Add petalogix s3a1800dsp MMU linux ref-design." and 72b675caacf "microblaze: Hook into the build-system

[PULL 19/29] hw/pci-host/ppce500: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-15-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/ppce500.c | 42 ++ 1 file changed, 18 insertions(+), 24 de

[PULL 05/29] hw/microblaze/s3adsp1800: Declare machine type using DEFINE_TYPES macro

Replace DEFINE_MACHINE() by DEFINE_TYPES(), converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-6-phi...@linaro.org> --- hw/microblaze/petalogix_s3adsp1800_mmu.c | 17 +++

[PULL 17/29] hw/i2c/mpc_i2c: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Acked-by: Corey Minyard Message-ID: <20241103133412.73536-13-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i2c/mpc_i2c.c | 20 1 file changed, 8 insertions(+), 12 delet

[PULL 21/29] hw/net/fsl_etsec/etsec: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-17-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/net/fsl_etsec/etsec.c | 22 +- 1 file changed, 9 insertions(+), 13 deletions(-) diff -

[PULL 20/29] hw/net/fsl_etsec/miim: Reuse MII constants

From: Bernhard Beschow Instead of defining redundant constants and using magic numbers reuse the existing MII constants. Signed-off-by: Bernhard Beschow cc: Akihiko Odaki Reviewed-by: Akihiko Odaki Message-ID: <20241103133412.73536-16-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé

[PULL 29/29] hw/riscv/iommu: fix build error with clang

From: Pierrick Bouvier Introduced in 0c54acb8243, "hw/riscv: add RISC-V IOMMU base emulation". ../hw/riscv/riscv-iommu.c:187:17: error: redefinition of '_pext_u64' 187 | static uint64_t _pext_u64(uint64_t val, uint64_t ext) | ^ D:/a/_temp/msys64/clang64/lib/clang/18/in

[PULL 28/29] hw/usb/hcd-ehci-sysbus: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow The naming of the TypeInfo array is inspired by hcd-ohci-sysbus. Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-25-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/usb/hcd-ehci-sysbus.c | 118 +

[PULL 22/29] hw/gpio/mpc8xxx: Prefer DEFINE_TYPES() macro

From: Bernhard Beschow Reviewed-by: Cédric Le Goater Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-18-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/gpio/mpc8xxx.c | 22 +- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/

[PULL 12/29] hw/ppc/e500: Prefer QOM cast

From: Bernhard Beschow Reviewed-by: BALATON Zoltan Signed-off-by: Bernhard Beschow Message-ID: <20241103133412.73536-4-shen...@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/e500.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500

[PULL 08/29] hw/core: Make CPU topology enumeration arch-agnostic

From: Zhao Liu Cache topology needs to be defined based on CPU topology levels. Thus, define CPU topology enumeration in qapi/machine.json to make it generic for all architectures. To match the general topology naming style, rename CPU_TOPO_LEVEL_* to CPU_TOPOLOGY_LEVEL_*, and rename SMT and pac

Re: [PATCH 4/8] user: Introduce host_interrupt_signal

On Tue, 2024-11-05 at 22:30 +, Richard Henderson wrote: > On 11/5/24 15:50, Ilya Leoshkevich wrote: > > On Tue, 2024-11-05 at 08:39 -0700, Warner Losh wrote: > > > On Thu, Oct 24, 2024 at 2:00 PM Ilya Leoshkevich > > > > > > wrote: > > > > Attaching to the gdbstub of a running process requires

[PULL 06/29] hw/core/machine: Add missing 'units.h' and 'error-report.h' headers

Include the missing "qemu/units.h" to fix when refactoring code: ../hw/core/machine.c:743:34: error: use of undeclared identifier 'MiB' 743 | mc->default_ram_size = 128 * MiB; | ^ ../hw/core/machine.c:750:44: error: use of undeclared identifier 'TiB

[PULL 10/29] hw/core: Check smp cache topology support for machine

From: Zhao Liu Add cache_supported flags in SMPCompatProps to allow machines to configure various caches support. And check the compatibility of the cache properties with the machine support in machine_parse_smp_cache(). Signed-off-by: Zhao Liu Tested-by: Yongwei Ma Reviewed-by: Jonathan Came

[PULL 09/29] qapi/qom: Define cache enumeration and properties for machine

From: Zhao Liu The x86 and ARM need to allow user to configure cache properties (current only topology): * For x86, the default cache topology model (of max/host CPU) does not always match the Host's real physical cache topology. Performance can increase when the configured virtual topolog

[PULL 07/29] i386/cpu: Don't enumerate the "invalid" CPU topology level

From: Zhao Liu In the follow-up change, the CPU topology enumeration will be moved to QAPI. And considerring "invalid" should not be exposed to QAPI as an unsettable item, so, as a preparation for future changes, remove "invalid" level from the current CPU topology enumeration structure and defin

[PULL 00/29] Misc HW patches for 2024-11-05

The following changes since commit 44a9394b1d272b53306d097d4bc20ff7ad14b159: Merge tag 'pull-nvme-20241104' of https://gitlab.com/birkelund/qemu into staging (2024-11-05 14:23:22 +) are available in the Git repository at: https://github.com/philmd/qemu.git tags/hw-misc-202

[PULL 02/29] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu

The petalogix-ml605 machine was explicitly added as little-endian only machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU little-endian ref design"). Mark the big-endian version as deprecated. When the xlnx-zynqmp-pmu machine's CPU was added in commit 133d23b3ad1 ("xlnx-zynqmp-pmu

[PULL 01/29] target/microblaze: Rename CPU endianness property as 'little-endian'

Rename the 'endian' property as 'little-endian' because the 'ENDI' bit is set when the endianness is in little order, and unset in big order. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Alistair Francis Message-Id: <20241105130431.22564-2-phi...@linaro.org> -

Re: [PATCH 02/19] hw/microblaze: Deprecate big-endian petalogix-ml605 & xlnx-zynqmp-pmu

On Tue, Nov 5, 2024 at 11:06 PM Philippe Mathieu-Daudé wrote: > > The petalogix-ml605 machine was explicitly added as little-endian only > machine in commit 00914b7d970 ("microblaze: Add PetaLogix ml605 MMU > little-endian ref design"). Mark the big-endian version as deprecated. > > When the xlnx-

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