Re: [PATCH v2 3/3] tests/qtest/tpm: add unit test to tis-spi

On 10/25/24 4:12 PM, dan tan wrote: Add qtest cases to exercise main TPM locality functionality The TPM device emulation is provided by swtpm, which is TCG TPM 2.0, and TCG TPM TIS compliant. See https://trustedcomputinggroup.org/wp-content/uploads/TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1

Re: [PATCH v2 1/3] tpm/tpm_tis_spi: Support TPM for SPI (Serial Peripheral Interface)

On 10/25/24 4:12 PM, dan tan wrote: Implement support for TPM via SPI interface. The SPI bus master is provided by PowerNV SPI device which is an SSI peripheral. It can uses the tpm_emulator driver backend with the external swtpm. Although the implementation is endian neutral, the SPI bus mas

[PATCH qemu.git 1/1] hw/intc/sifive_plic: add const qualifier to signature

From: Axel Heider Signed-off-by: Axel Heider --- hw/intc/sifive_plic.c | 2 +- include/hw/intc/sifive_plic.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 7f43e96310..3e9e4b40e5 100644 --- a/hw/intc/sifive_plic

[PATCH qemu.git 0/1] hw/intc/sifive_plic: add const qualifier to signature

Add const qualifier to function signature. The function does not modify the string. This allows passing read-only strings also. Axel Heider (1): hw/intc/sifive_plic: add const qualifier to signature hw/intc/sifive_plic.c | 2 +- include/hw/intc/sifive_plic.h | 2 +- 2 files changed, 2

[PATCH qemu.git 1/1] docs/devel/reset: add missing words

From: Axel Heider Signed-off-by: Axel Heider --- docs/devel/reset.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/reset.rst b/docs/devel/reset.rst index 74c7c0171a..3e64a7259f 100644 --- a/docs/devel/reset.rst +++ b/docs/devel/reset.rst @@ -286,7 +286,7 @@ eve

[PATCH qemu.git 0/1] docs/devel/reset: add missing words

Add missing words in documentation Axel Heider (1): docs/devel/reset: add missing words docs/devel/reset.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.45.2

Re: [PATCH 03/36] next-cube: remove overlap between next.dma and next.mmio memory regions

On 26/10/2024 08:56, Thomas Huth wrote: Am Wed, 23 Oct 2024 09:58:19 +0100 schrieb Mark Cave-Ayland : Change the start of the next.mmio memory region so that it follows on directly after the next.dma memory region, adjusting the address offsets in next_mmio_read() and next_mmio_write() accordi

Re: [PATCH 12/21] target/sparc: Explicitly set 2-NaN propagation rule

On 25/10/2024 15:12, Peter Maydell wrote: Set the NaN propagation rule explicitly in the float_status words we use. Signed-off-by: Peter Maydell --- target/sparc/cpu.c | 8 target/sparc/fop_helper.c | 10 -- fpu/softfloat-specialize.c.inc | 6 ++ 3

Re: [PATCH 11/21] target/sparc: Move cpu_put_fsr(env, 0) call to reset

On 25/10/2024 15:12, Peter Maydell wrote: Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which initializes various fields in the CPU struct: * fsr_cexc_ftt * fcc[] * fsr_qne * fsr It also sets the rounding mode in env->fp_status. This is largely pointless, because when we la

Re: [PATCH v2 7/7] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree

On 31/8/23 21:29, Richard Henderson wrote: On 8/31/23 13:30, Philippe Mathieu-Daudé wrote: From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed inte

[PATCH v3 6/9] target/mips: Convert Loongson [D]DIVU.G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert DIVU.G (divide 32-bit unsigned integers) and DDIVU.G (divide 64-bit unsigned integers) opcodes to decodetree. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/godson2.decode

[PATCH v3 5/9] target/mips: Convert Loongson DIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé DIV.G and DDIV.G are very similar. Provide gen_lext_DIV_G() a 'is_double' argument so it can generate DIV.G (divide 32-bit signed integers). With this commit we explicit the template used to generate opcode for 32/64-bit word variants. Next commits will be less verbo

[PATCH v3 7/9] target/mips: Convert Loongson [D]MOD[U].G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MOD.G - mod 32-bit signed integers - MODU.G - mod 32-bit unsigned integers - DMOD.G - mod 64-bit signed integers - DMODU.G - mod 64-bit unsigned integers Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-D

Re: [PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree

On 26/10/24 14:53, Philippe Mathieu-Daudé wrote: target/mips/tcg/translate.h | 3 + target/mips/tcg/godson2.decode| 27 +++ target/mips/tcg/loong-ext.decode | 28 +++ target/mips/tcg/loong_translate.c | 271 ++ target/mips/tcg/translate.c |

[PATCH v3 9/9] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/loong_translate.c | 41 ++

[PATCH v3 3/9] target/mips: Re-introduce OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP

From: Philippe Mathieu-Daudé There is no issue having multiple enum declarations with the same value. As we are going to remove the OPC_MULT_G_2E definition in few commits, restore the OPC_ADDUH_QB_DSP and OPC_MUL_PH_DSP definitions and use them where they belong. Signed-off-by: Philippe Mathieu

[PATCH v3 8/9] target/mips: Convert Loongson [D]MULT[U].G opcodes to decodetree

From: Philippe Mathieu-Daudé Convert the following opcodes to decodetree: - MULT.G - multiply 32-bit signed integers - MULTU.G - multiply 32-bit unsigned integers - DMULT.G - multiply 64-bit signed integers - DMULTU.G - multiply 64-bit unsigned integers Now that all opcodes from the extension h

[PATCH v3 4/9] target/mips: Convert Loongson DDIV.G opcodes to decodetree

From: Philippe Mathieu-Daudé Introduce decode_loongson() to decode all Loongson vendor specific opcodes. Start converting a single opcode: DDIV.G (divide 64-bit signed integers). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé --- ta

[PATCH v3 1/9] target/mips: Extract decode_64bit_enabled() helper

Extract the decode_64bit_enabled() helper which detects whether CPUs can run 64-bit instructions. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.h | 2 ++ target/mips/tcg/translate.c | 7 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/mips/tcg/t

[PATCH v3 0/9] target/mips: Convert Loongson LEXT opcodes to decodetree

Missing review: 1 & 9 Since v2: - Extract decode_64bit_enabled() - Remove unreachable 32-bit code Since v1: - Fixed '!is_double' check (rth) - Rebased (removing tcg_temp_free calls) - Simplified MULT[U].G (rth) - Added R-b Philippe Mathieu-Daudé (9): target/mips: Extract decode_64bit_enabled()

[PATCH v3 2/9] target/mips: Simplify Loongson MULTU.G opcode

Since MULTU opcodes don't record the most significant bits of the infinite result, sign-extending the sources make no difference in the result. Once we remove the sign extension of source registers, MULT and MULTU are identical (as are DMULT and DMULTU). Suggested-by: Richard Henderson Signed-of

Re: [PATCH] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

On 26/10/24 14:20, Philippe Mathieu-Daudé wrote: On 26/10/24 12:45, Philippe Mathieu-Daudé wrote: Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Sign

Re: [PATCH] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

On 26/10/24 12:45, Philippe Mathieu-Daudé wrote: Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <

[PATCH v4 0/5] block: allow commit to unmap zero blocks

This patch series adds support for zero blocks in non-active commits. The first three patches in the series refactor the relevant code, patch four makes the actual changes, and the last patch adds a test for the new functionality. --- Changes since v3: - minor reformating based on checkpatch.pl -

[PATCH v4 5/5] block: add test non-active commit with zeroed data

Signed-off-by: Vincent Vanlaer Tested-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Vladimir Sementsov-Ogievskiy --- tests/qemu-iotests/tests/commit-zero-blocks | 96 +++ .../qemu-iotests/tests/commit-zero-blocks.out | 54 +++ 2 files changed, 150 insertions(+) create

[PATCH v4 1/5] block: get type of block allocation in commit_run

bdrv_co_common_block_status_above not only returns whether the block is allocated, but also if it contains zeroes. Signed-off-by: Vincent Vanlaer Reviewed-by: Vladimir Sementsov-Ogievskiy --- block/commit.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/block/c

[PATCH v4 4/5] block: allow commit to unmap zero blocks

Non-active block commits do not discard blocks only containing zeros, causing images to lose sparseness after the commit. This commit fixes that by writing zero blocks using blk_co_pwrite_zeroes rather than writing them out as any other arbitrary data. Signed-off-by: Vincent Vanlaer Reviewed-by:

[PATCH v4 3/5] block: refactor error handling of commit_iteration

Signed-off-by: Vincent Vanlaer --- block/commit.c | 61 -- 1 file changed, 34 insertions(+), 27 deletions(-) diff --git a/block/commit.c b/block/commit.c index 078e54f51f..5c24c8b80a 100644 --- a/block/commit.c +++ b/block/commit.c @@ -129,51 +129,

[PATCH v4 2/5] block: move commit_run loop to separate function

Signed-off-by: Vincent Vanlaer Reviewed-by: Vladimir Sementsov-Ogievskiy --- block/commit.c | 89 +- 1 file changed, 52 insertions(+), 37 deletions(-) diff --git a/block/commit.c b/block/commit.c index 8dee25b313..078e54f51f 100644 --- a/block/com

[PATCH] target/mips: Remove unreachable 32-bit code on 64-bit Loongson Ext

Loongson fixed-point multiplies and divisions opcodes are specific to 64-bit cores (Loongson-2 and Loongson-3 families). Simplify by removing the 32-bit checks. Reported-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20230831203024.87300-1-phi...@linaro.org> --- targ

Re: [PATCH 0/2] arm: Add collie and sx functional tests

On 10/26/24 03:02, Cédric Le Goater wrote: [ ... ] I don't mind a single file. What bothers me is that the partitioning is made mandatory for ast2600 even if not used. Our only use case, in 2019, was to boot QEMU ast2600 machines from an eMMC device using an OpenBMC FW image like the ones we f

Re: [PATCH v4 15/15] hw/vmapple/vmapple: Add vmapple machine type

On Sat, 26 Oct 2024 at 08:21, Akihiko Odaki wrote: > On 2024/10/24 19:28, Phil Dennis-Jordan wrote: > > From: Alexander Graf > > > > Apple defines a new "vmapple" machine type as part of its proprietary > > macOS Virtualization.Framework vmm. This machine type is similar to the > > virt one, but

Re: [PATCH v4 02/15] hw/display/apple-gfx: Introduce ParavirtualizedGraphics.Framework support

On Sat, 26 Oct 2024 at 06:40, Akihiko Odaki wrote: > On 2024/10/26 4:43, Phil Dennis-Jordan wrote: > > > > > > On Fri, 25 Oct 2024 at 08:03, Akihiko Odaki > > wrote: > > > > On 2024/10/24 19:28, Phil Dennis-Jordan wrote: > > > +/* For running PVG mem

Re: [PATCH 00/11] Rust device model patches and misc cleanups

Hi Paolo, Please reply with review comments underneath individual patches, this is hard to follow and I might miss some points. On Fri, 25 Oct 2024 at 12:33, Paolo Bonzini wrote: > > On 10/24/24 16:02, Manos Pitsidianakis wrote: > > Hello everyone, the pathological corrosion of QEMU code continu

Re: [PATCH 0/2] arm: Add collie and sx functional tests

On 10/26/24 07:54, Guenter Roeck wrote: On 10/25/24 21:47, Philippe Mathieu-Daudé wrote: On 25/10/24 12:25, Jan Lübbe wrote: On Fri, 2024-10-25 at 06:59 -0700, Guenter Roeck wrote: On 10/25/24 02:57, Jan Lübbe wrote: On Fri, 2024-10-25 at 08:55 +0200, Cédric Le Goater wrote: On 10/24/24 19:5

[PATCH v3 3/4] virtio_net: Add the 2rd acceptable situation for Mac setup.

When using a VDPA device, the following situations are also acceptable: the hardware MAC address is not 0, and the MAC address in the QEMU command line is 0. Signed-off-by: Cindy Lu --- hw/net/virtio-net.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/hw/net/virtio-net.c b/

[PATCH v3 4/4] virtio_net: Add the 3rd acceptable situation for Mac setup.

While the hardware MAC address is 0 and the MAC address in the QEMU command line is also 0, this configuration is acceptable. Signed-off-by: Cindy Lu --- hw/net/virtio-net.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 6900e3c

[PATCH v3 2/4] virtio_net: Add the check for vdpa's mac address

When using a VDPA device, it is important to ensure that the MAC address is correctly set. The MAC address in the hardware should match the MAC address from the QEMU command line. This is a recommended configuration and will allow the system to boot. Signed-off-by: Cindy Lu --- hw/net/virtio-net

[PATCH v3 1/4] vhost_vdpa : Add a new parameter to enable check mac address

When using a VDPA device, it's important to ensure that the MAC address is correctly set. Add a new parameter in qemu cmdline to enable this check, default value is false The usage is: -netdev type=vhost-vdpa,vhostdev=/dev/vhost-vdpa-0,id=vhost-vdpa0,macstrickcheck=true\ -device virtio-net-p

[PATCH v3 0/4] virtio_net: Add the check for vdpa's mac address

When using a VDPA device, it is important to ensure that the MAC address is correctly set.Here we add Add a new parameter to enable this check. There are only three acceptable situations for MAC setup; any other configuration will fail to boot. The usage is: -netdev type=vhost-vdpa,vhostdev

Re: [PATCH 04/36] next-cube: remove cpu parameter from next_scsi_init()

Am Wed, 23 Oct 2024 09:58:20 +0100 schrieb Mark Cave-Ayland : > The parameter is not used. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/next-cube.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Thomas Huth

Re: [PATCH 03/36] next-cube: remove overlap between next.dma and next.mmio memory regions

Am Wed, 23 Oct 2024 09:58:19 +0100 schrieb Mark Cave-Ayland : > Change the start of the next.mmio memory region so that it follows on directly > after the next.dma memory region, adjusting the address offsets in > next_mmio_read() and next_mmio_write() accordingly. > > Signed-off-by: Mark Cave-Ay

Re: [PATCH 01/36] next-cube: fix up compilation when DEBUG_NEXT is enabled

Am Wed, 23 Oct 2024 09:58:17 +0100 schrieb Mark Cave-Ayland : > These were accidentally introduced by my last series. > > Signed-off-by: Mark Cave-Ayland > --- > hw/m68k/next-cube.c | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Thomas Huth

Re: [PATCH 02/36] next-cube: remove 0x14020 dummy value from next_mmio_read()

Am Wed, 23 Oct 2024 09:58:18 +0100 schrieb Mark Cave-Ayland : > This is a dummy value for the SCSI CSR which appears to have no effect when > removed. Eventually the reads/writes to this register will be directed > towards the WIP implementations in next_scr_readfn() and next_scr_writefn(). > > S

Re: [PULL 0/6] loongarch-to-apply queue

Peter Maydell 于2024年10月26日周六 02:12写道： > > On Thu, 24 Oct 2024 at 10:44, Song Gao wrote: > > > > The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5: > > > > Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into > > staging (2024-10-21 17:12:59 +0100)