On Wed, 23 Oct 2024 at 02:35, Cédric Le Goater wrote:
>
> On 10/22/24 13:54, Joel Stanley wrote:
> > On Wed, 16 Oct 2024 at 01:23, Jamin Lin wrote:
> >
> >> 3. Test HACE model with u-boot hash command
> >> a. load test file to address 8300 via tftp
> >> ast# tftp 8300 jamin_lin/32MB
> >>
Ping #5?
Thanks,
/mjt
27.09.2024 09:10, Michael Tokarev wrote:
This is a re-send of this patchset from Apr-24, after multiple pings.
I rebased it on top of current qemu/master, though nothing has really
changed - it is still the same changes. We should either apply it or
drop it if it is not
> -Original Message-
> From: JeeHeng Sia
> Sent: Thursday, 29 August, 2024 9:59 AM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org; qemu-ri...@nongnu.org
> Cc: m...@redhat.com; imamm...@redhat.com; anisi...@redhat.com;
> peter.mayd...@linaro.org; JeeHeng Sia
> ; shannon.zha...@gmail.c
Cal Peake writes:
> Hello,
>
> This is a follow up to commit 8f525028bc6f52e4af3f737928d16c3f39a6ea54 to
> take care of a few remaining QCryptoAFAlg -> QCryptoAFAlgo renames.
>
> Signed-off-by: Cal Peake
I posted the same fix, and it's in a pull request now:
Subject: [PULL 07/14] crypto/h
A straight forward conversion, only the usual changes were required
here (i.e. adjustment for asset downloading, machine selection).
Signed-off-by: Thomas Huth
---
MAINTAINERS | 2 +-
.../test_aarch64_tcg_plugins.py} | 37 ---
2 fil
On 22/10/2024 22.12, Jared Rossi wrote:
On 10/22/24 1:36 PM, Thomas Huth wrote:
On 20/10/2024 03.29, jro...@linux.ibm.com wrote:
From: Jared Rossi
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple
On Mon, Oct 21, 2024 at 06:35:29PM +0200, Paolo Bonzini wrote:
> Date: Mon, 21 Oct 2024 18:35:29 +0200
> From: Paolo Bonzini
> Subject: [PATCH v2 04/13] rust: do not use --no-size_t-is-usize
> X-Mailer: git-send-email 2.46.2
>
> This not necessary and makes it harder to write code that
> is porta
On Fri, Sep 13, 2024 at 12:54 AM Eugenio Pérez wrote:
>
> Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net
> structures if peer nic is present") effectively delayed the backend
> cleanup, allowing the frontend or the guest to access it resources as
> long as the frontend is still
From: Alexander Graf
When translating virtual to physical address with a guest CPU that
supports nested paging (NPT), we need to perform every page table walk
access indirectly through the NPT, which we correctly do.
However, we treat real mode (no page table walk) special: In that case,
we curr
On Fri, Sep 6, 2024 at 2:13 AM Daniel P. Berrangé wrote:
>
> The eBPF code is currently reporting error messages through trace
> events. Trace events are fine for debugging, but they are not to be
> considered the primary error reporting mechanism, as their output
> is inaccessible to callers.
>
>
From: Yao Zi
Commit 9651cead2f ("linux-user: add openat2 support in linux-user")
ships a definition of struct open_how_ver0 while assuming type __u64 is
available in code, which is not the case when building QEMU on musl.
Let's replaces __u64 with uint64_t.
Fixes: 9651cead2f ("linux-user: add op
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-9-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 4 ++--
tcg/riscv/tcg-target.c.inc | 41 +
This argument is no longer used.
Suggested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-ID: <20241013184733.1423747-4-richard.hender...@linaro.org>
---
target/i386/tcg/sysemu/excp_helper.c | 18 +-
1 file changed, 9 ins
From: Huang Shiyuan
The RISC-V vector instruction set utilizes the LMUL field to group
multiple registers, enabling variable-length vector registers. This
implementation uses only the first register number of each group while
reserving the other register numbers within the group.
In TCG, each VE
Hi Alexandre,
On 22/10/24 06:06, Alexandre Ratchov wrote:
On Fri, Sep 13, 2024 at 10:04:29AM +0200, Markus Armbruster wrote:
Alexandre Ratchov writes:
On Tue, Sep 10, 2024 at 03:28:57PM +0100, Daniel P. Berrangé wrote:
This is the single use of the ISC license in the more than 10k
files in
From: TANG Tiancheng
Add support for probing RISC-V vector extension availability in
the backend. This information will be used when deciding whether
to use vector instructions in code generation.
Cache lg2(vlenb) for the backend. The storing of lg2(vlenb) means
we can convert all of the divisio
From: Ilya Leoshkevich
do_setcontext() copies the target sigmask without endianness handling
and then uses target_to_host_sigset_internal(), which expects a
byte-swapped one. Use target_to_host_sigset() instead.
Fixes: bcd4933a23f1 ("linux-user: ppc signal handling")
Signed-off-by: Ilya Leoshkev
Suggested-by: Alex Bennée
Reviewed-by: Pierrick Bouvier
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-ID: <20241013184733.1423747-2-richard.hender...@linaro.org>
---
include/exec/exec-all.h | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-
The following changes since commit 6f625ce2f21d6a1243065d236298277c56f972d5:
Merge tag 'pull-request-2024-10-21' of https://gitlab.com/thuth/qemu into
staging (2024-10-21 17:12:59 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202
From: Yao Zi
Current definition yields a negative 32bits value, messing up hwprobe
result when Zvfhmin extension presents. Replace it by using a 1ULL bit
shift value as done in kernel upstream.
Link:
https://github.com/torvalds/linux/commit/5ea6764d9095e234b024054f75ebbccc4f0eb146
Fixes: a3432c
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-6-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 3 ++
tcg/riscv/tcg-target-con-str.h | 1 +
tcg/
Use vrsub.vi to subtract from a constant.
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 8 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg
From: Ilya Leoshkevich
If one thread modifies the mappings and another thread prints them,
a situation may occur that the printer thread sees a guest mapping
without a corresponding host mapping, leading to a crash in
open_self_maps_2().
Cc: qemu-sta...@nongnu.org
Fixes: 7b7a3366e142 ("linux-use
The probe_access_full_mmu function was designed for this purpose,
and does not report the memory operation event to plugins.
Cc: qemu-sta...@nongnu.org
Fixes: 6d03226b422 ("plugins: force slow path when plugins instrument memory
ops")
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-8-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 +-
tcg/riscv/tcg-target.c.inc | 7 +++
2 files
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-5-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 76 +-
1 file chan
From: Dani Szebenyi
The TCG IR sequence:
mov_i32 tmp97,$0xc424 dead: 1 pref=0x
mov_i32 tmp98,$0x0pref=0x
rotr_i32 tmp97,tmp97,tmp98dead: 1 2 pref=0x
was translated to `slwi r15, r14, 0` instead of `slwi r14, r14, 0`
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Message-ID: <20241007025700.47259-12-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 6 +++---
tcg/riscv/tcg-target.c.inc | 36
2 fi
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-10-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 2 +-
tcg/riscv/tcg-target.c.inc | 33 ++
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-11-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.h | 6 +--
tc
From: TANG Tiancheng
Extend comparison results from mask registers to SEW-width elements,
following recommendations in The RISC-V SPEC Volume I (Version 20240411).
This aligns with TCG's cmp_vec behavior by expanding compare results to
full element width: all 1s for true, all 0s for false.
Signe
From: Ilya Leoshkevich
Add a function for formatting target sigsets. It can be useful for
other syscalls in the future, so put it into the beginning of strace.c.
For simplicity, do not implement the strace's ~[] output syntax.
Add a rt_sigprocmask return handler.
Example outputs:
753914 rt
The first immediate field is unsigned, whereas operand_vimm
extracts a signed value. There is no need to mask the result
with 'u'; just print the immediate with 'i'.
Fixes: 07f4964d178 ("disas/riscv.c: rvv: Add disas support for vector
instructions")
Reviewed-by: Alistair Francis
Reviewed-by: P
This pointer needs to be reset after overflow just like
code_buf and code_ptr.
Cc: qemu-sta...@nongnu.org
Fixes: 57a269469db ("tcg: Infrastructure for managing constant pools")
Acked-by: Alistair Francis
Reviewed-by: Pierrick Bouvier
Reviewed-by: LIU Zhiwei
Signed-off-by: Richard Henderson
---
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Richard Henderson
Message-ID: <20241007025700.47259-13-zhiwei_...@linux.alibaba.com>
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Hi Cedric,
> Subject: Re: [PATCH v2 07/18] aspeed: Fix hardcode attach flash model of spi
> controllers
>
> oops. R-b sent on the wrong patch.
>
> On 10/22/24 12:48, Cédric Le Goater wrote:
> > On 10/22/24 11:40, Jamin Lin wrote:
> >> It only attached flash model of fmc and spi[0] in aspeed_mach
On Mon, Oct 21, 2024 at 7:30 PM Clément Léger wrote:
>
>
>
> On 21/10/2024 02:46, Alistair Francis wrote:
> > On Fri, Oct 18, 2024 at 12:55 AM Clément Léger wrote:
> >>
> >> With the current implementation, if we had the current scenario:
> >> - set bit x in menvcfg
> >> - set bit x in henvcfg
>
On Tue, Oct 22, 2024 at 10:11 AM Richard Henderson
wrote:
>
> Introduce support for the RISC-V vector extension in the TCG backend.
>
> Changes for v7:
> - Adjust cpuinfo-riscv.c probing for vector support.
>
> In addition to adjusting @left, assert expected value in vlenb.
> I wondered what wou
On Tue, Oct 22, 2024 at 10:11 AM Richard Henderson
wrote:
>
> Use vrsub.vi to subtract from a constant.
>
> Signed-off-by: Richard Henderson
Acked-by: Alistair Francis
Alistair
> ---
> tcg/riscv/tcg-target-con-set.h | 1 +
> tcg/riscv/tcg-target.c.inc | 8 ++--
> 2 files changed, 7 i
From: Hyman Huang
Introudce kvm_dirty_log_manual_enabled to indicate if dirty
logging manually was enabled in KVM.
The kvm_dirty_log_manual_enabled will be used in the next commit.
Signed-off-by: Hyman Huang
---
accel/kvm/kvm-all.c | 2 ++
include/sysemu/kvm.h | 8
2 files changed,
From: Hyman Huang
As discussed in:
https://lore.kernel.org/qemu-devel/ZvbQ0RQx-zxOeo4Y@x1n/
RAMBlock dirty sync in ram_init_bitmaps() appears to be unnecessary;
this patchset attempts to eliminate it and asks for comments on how
to do so.
Please review, thanks
Yong
Hyman Huang (2):
accel/kvm
From: Hyman Huang
KVM always returns 1 when userspace retrieves a dirty bitmap for
the first time when KVM_DIRTY_LOG_INITIALLY_SET is enabled; in such
scenario, the RAMBlock dirty sync of the initial iteration can be
skipped.
Signed-off-by: Hyman Huang
---
migration/cpu-throttle.c | 3 ++-
mi
Hi Igor,
Thanks for taking time to review the series. Please find my replies inline.
> From: qemu-devel-bounces+salil.mehta=huawei@nongnu.org devel-bounces+salil.mehta=huawei@nongnu.org> On Behalf Of Igor
> Mammedov
> Sent: Friday, October 18, 2024 3:46 PM
> To: Salil Mehta
>
>
Hi Cedric,
> Subject: Re: [PATCH v2 01/18] aspeed/smc: Fix write incorrect data into flash
> in
> user mode
>
> >>
> >> static const VMStateDescription vmstate_aspeed_smc = {
> >> .name = "aspeed.smc",
> >> -.version_id = 2,
> >> +.version_id = 3,
> >> .minimum_version_id
Hi Cedric,
> Subject: Re: [PATCH v2 12/18] test/qtest/aspeed_smc-test: Introducing a
> "page_addr" data field
>
> On 10/22/24 11:41, Jamin Lin wrote:
> > Currently, these test cases used the hardcode offset 0x140
> > (0x14000 * 256) which was beyond the 16MB flash size for flash page
> read/w
On 2024/10/23 上午2:54, Richard Henderson wrote:
On 10/22/24 05:42, Bibo Mao wrote:
For user tcg, there is no physical cpu id provided and logic cpuid
is used. For system emulation, physical cpu id is provided, initial
value of register CSR CPUID can be set from physical cpu id.
Signed-off-by:
Hi Gustavo,
> From: Gustavo Romero
> Sent: Monday, October 21, 2024 3:10 AM
> To: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com
>
> Hi Salil,
>
> On 10/14/24 16:22, Salil Mehta wrote:
> > Reflect the ACPI CPU hotplug `is_{present, enabled}` states in the
>
On 10/22/24 17:16, Ilya Leoshkevich wrote:
On Tue, 2024-10-22 at 13:36 -0700, Pierrick Bouvier wrote:
On 10/22/24 03:56, Alex Bennée wrote:
From: Ilya Leoshkevich
commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before
translation")
fixed cross-modifying code handling, but did not add a test
Running qemu-i386 on a system running with SELinux in enforcing mode
(more precisely: s390x trixie container on Fedora 40) fails with:
qemu-i386: tests/tcg/i386-linux-user/sigreturn-sigmask: Unable to find a
guest_base to satisfy all guest address mapping requirements
-
On Tue, 2024-10-22 at 13:36 -0700, Pierrick Bouvier wrote:
> On 10/22/24 03:56, Alex Bennée wrote:
> > From: Ilya Leoshkevich
> >
> > commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before
> > translation")
> > fixed cross-modifying code handling, but did not add a test. The
> > changed code wa
Order the helper arguments to match the Principles of Operation.
Implement the "Results: MULTIPLY AND ADD" table in pickNaNMulAdd().
Reported-by: Peter Maydell
Signed-off-by: Ilya Leoshkevich
---
fpu/softfloat-specialize.c.inc| 19 +++
target/s390x/tcg/fpu_helper.c | 8
Add a test to prevent regressions.
Share some useful pieces with the vfminmax test.
Remove the duplicates from the floating point class values.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 5 +-
tests/tcg/s390x/float.h | 104 ++
tests/tcg/s390x/fma.
Hi,
Peter reported on IRC that FMA NaN handling was likely broken on s390x.
Patch 1 of this series fixes the issue, patch 2 adds a test. For the
sake of readability, the test sacrifices the 90-character line length
rule.
Best regards,
Ilya
Ilya Leoshkevich (2):
target/s390x: Fix the floating-p
Hi Igor,
> From: Igor Mammedov
> Sent: Friday, October 18, 2024 3:25 PM
> To: Salil Mehta
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; m...@redhat.com;
> m...@kernel.org; jean-phili...@linaro.org; Jonathan Cameron
> ; lpieral...@kernel.org;
> peter.mayd...@linaro.org; richard.hender.
> From: Igor Mammedov
> Sent: Friday, October 18, 2024 3:19 PM
> To: Zhao Liu
> Cc: Salil Mehta ; qemu-devel@nongnu.org;
> qemu-...@nongnu.org; m...@redhat.com; m...@kernel.org; jean-
> phili...@linaro.org; Jonathan Cameron
> ; lpieral...@kernel.org;
> peter.mayd...@linaro.org; richard.h
Hi Zhao,
Sorry, for the late reply. I was away last week with only intermittent access
to the mails.
> From: Zhao Liu
> Sent: Friday, October 18, 2024 6:13 AM
> To: Salil Mehta
>
> Hi Salil,
>
> On Mon, Oct 14, 2024 at 08:22:04PM +0100, Salil Mehta wrote:
> > Date: Mon, 14 Oct 2024 20
Hi Igor,
> From: Igor Mammedov
> Sent: Friday, October 18, 2024 3:31 PM
> To: Salil Mehta
>
> On Mon, 14 Oct 2024 20:22:05 +0100
> Salil Mehta wrote:
>
> > The ACPI CPU hotplug states `is_{present, enabled}` must be migrated
> > alongside other vCPU hotplug states to the destination
On Wed, Oct 16, 2024 at 02:28:27PM +0800, Jiqian Chen wrote:
> --- a/hw/xen/xen_pt.h
> +++ b/hw/xen/xen_pt.h
> @@ -36,6 +36,7 @@ void xen_pt_log(const PCIDevice *d, const char *f, ...)
> G_GNUC_PRINTF(2, 3);
> # define XEN_PT_LOG_CONFIG(d, addr, val, len)
> #endif
>
> +#define DOMID_RUN_QEMU
Hi Igor,
> From: Igor Mammedov
> Sent: Friday, October 18, 2024 3:18 PM
> To: Salil Mehta
>
> On Mon, 14 Oct 2024 20:22:03 +0100
> Salil Mehta wrote:
>
> > Update the `AcpiCpuStatus` for `is_enabled` and `is_present`
> > accordingly when vCPUs are hot-plugged or hot-unplugged, taking
On 22/10/24 07:56, Alex Bennée wrote:
We didn't notice breakage of aarch64_be because we don't have any TCG
tests for it. However while the existing aarch64 compiler can target
big-endian builds no one packages a BE libc. Instead we bang some
rocks together to do the most basic of hello world wit
On Fri, Oct 11, 2024 at 1:14 PM Noah Goldstein wrote:
>
> On Wed, Oct 2, 2024 at 11:42 AM Noah Goldstein
> wrote:
> >
> > On Wed, Oct 2, 2024 at 11:39 AM Ilya Leoshkevich wrote:
> > >
> > > On Wed, 2024-10-02 at 09:05 -0500, Noah Goldstein wrote:
> > > > On Wed, Oct 2, 2024 at 3:08 AM Ilya Leos
On Tue, Oct 22, 2024 at 06:11:19PM +0200, Cédric Le Goater wrote:
> On 10/22/24 18:07, Peter Xu wrote:
> > Migration object can be freed before some other device codes run, while we
> > do have a bunch of migration helpers exported in migration/misc.h that
> > logically can be invoked at any time o
On Tue, Oct 22, 2024 at 02:08:29PM -0600, Alex Williamson wrote:
> Thanks to work by Peter Xu, support is introduced in Linux v6.12 to
> allow pfnmap insertions at PMD and PUD levels of the page table. This
> means that provided a properly aligned mmap, the vfio driver is able
> to map MMIO at sig
On 22/10/24 06:02, Peter Maydell wrote:
On Tue, 22 Oct 2024 at 08:09, Daniel P. Berrangé wrote:
On Tue, Oct 22, 2024 at 01:11:31AM -0300, Philippe Mathieu-Daudé wrote:
On 17/10/24 13:32, Peter Maydell wrote:
Add a functional test for the collie board that uses the kernel and
rootfs provided
On Tue, Oct 22, 2024 at 02:08:28PM -0600, Alex Williamson wrote:
> Move error handling code to the end of the function so that it can more
> easily be shared by new mmap failure conditions. No functional change
> intended.
>
> Signed-off-by: Alex Williamson
> ---
> hw/vfio/helpers.c | 34 ++
On 22/10/24 02:23, Paolo Bonzini wrote:
On Tue, Oct 22, 2024 at 6:31 AM Philippe Mathieu-Daudé
wrote:
-void qdev_property_add_static(DeviceState *dev, Property *prop)
+void qdev_property_add_static(DeviceState *dev, const Property *prop)
{
Object *obj = OBJECT(dev);
ObjectPrope
From: William Roche
On HW memory error, we need to report better what the impact of this
error is. So when an entire large page is impacted by an error (like the
hugetlbfs case), we give a warning message when this page is first hit:
Memory error: Loosing a large page (size: X) at QEMU addr Y and
From: William Roche
When the VM reboots, a memory reset is performed calling
qemu_ram_remap() on all hwpoisoned pages.
While we take into account the recorded page sizes to repair the
memory locations, a large page also needs to punch a hole in the
backend file to regenerate a usable memory, clea
From: William Roche
This set of patches fixes several problems with hardware memory errors
impacting hugetlbfs memory backed VMs. When using hugetlbfs large
pages, any large page location being impacted by an HW memory error
results in poisoning the entire page, suddenly making a large chunk of
t
On 22/10/24 07:56, Alex Bennée wrote:
Make it easy for people to see what is already queued.
Signed-off-by: Alex Bennée
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
From: William Roche
The SIGBUS signal siginfo reporting a HW memory error
provides a si_addr_lsb field with an indication of the
impacted memory page size.
This information should be used to track the hwpoisoned
page sizes.
Signed-off-by: William Roche
---
accel/kvm/kvm-all.c| 6 --
ac
From: William Roche
Add the page size information to the hwpoison_page_list elements.
As the kernel doesn't always report the actual poisoned page size,
we adjust this size from the backend real page size.
We take into account the recorded page size to adjust the size
and location of the memory h
On 10/22/24 01:21, Julian Ganz wrote:
Hi, Pierrick,
October 21, 2024 at 11:59 PM, "Pierrick Bouvier" wrote:
On 10/21/24 14:02, Julian Ganz wrote:
The motivation for this API is a plugin that simulates a RISC-V tracing
unit (and produces a trace). For that we actually also needed to
track
Hello,
This is a follow up to commit 8f525028bc6f52e4af3f737928d16c3f39a6ea54 to
take care of a few remaining QCryptoAFAlg -> QCryptoAFAlgo renames.
Signed-off-by: Cal Peake
diff --git a/crypto/hash-afalg.c b/crypto/hash-afalg.c
index 06e1e4699c..8c0ce5b520 100644
--- a/crypto/hash-afalg.c
+++
On 10/22/24 03:56, Alex Bennée wrote:
Now gdbstub has gained the ability to extend its command tables we can
allow it to trigger plugin callbacks. This is probably most useful for
QEMU developers debugging plugins themselves but might be useful for
other stuff.
Trigger the callback by sending:
Am 21.10.2024 um 18:35 hat Paolo Bonzini geschrieben:
> This series integrates some of the observations from the MSRV patches at
> https://lore.kernel.org/qemu-devel/20241015131735.518771-1-pbonz...@redhat.com/.
>
> The main changes here are two: first, build an integration test that
> actually tr
On 10/22/24 03:56, Alex Bennée wrote:
From: Gustavo Romero
Use list and set comprehension to simplify code. Also, gently handle
invalid gdb filenames.
Signed-off-by: Gustavo Romero
Message-Id: <20241015145848.387281-1-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée
---
scripts/probe-
On 10/22/24 03:56, Alex Bennée wrote:
Make it easier to find where plugin patches are being staged.
Signed-off-by: Alex Bennée
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 81396c9f15..02b8b2dfd6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
On 10/22/24 03:56, Alex Bennée wrote:
We didn't notice breakage of aarch64_be because we don't have any TCG
tests for it. However while the existing aarch64 compiler can target
big-endian builds no one packages a BE libc. Instead we bang some
rocks together to do the most basic of hello world wit
On 10/22/24 03:56, Alex Bennée wrote:
Attempting to run the binary asserts when it can't find the XML entry.
We can fix it so we don't although I suspect other stuff is broken.
Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2580
Signed-off-by: Alex Bennée
---
configs/targets/aarch64_be-
On 10/22/24 03:56, Alex Bennée wrote:
From: Ilya Leoshkevich
commit f025692c992c ("accel/tcg: Clear PAGE_WRITE before translation")
fixed cross-modifying code handling, but did not add a test. The
changed code was further improved recently [1], and I was not sure
whether these modifications wer
Signed-off-by: Matthieu Castet
---
hw/intc/armv7m_nvic.c| 38 +-
target/arm/cpu.c | 4 ++--
target/arm/ptw.c | 23 +++
target/arm/tcg/cpu-v7m.c | 21 -
4 files changed, 74 insertions(+), 12 deletions(-
Hello,
I have a patch that should allow to support cortex-m0+.
I used it in a special arm virtual machine that is still in progress (and not
submitted).
I think this can be usefull.
Matthieu Castet (1):
target/arm: Add cortex-m0+ support
hw/intc/armv7m_nvic.c| 38
On 10/22/24 03:56, Alex Bennée wrote:
We were missing s390x here. There isn't much point testing for the
architecture here as we will fail anyway if the appropriate package
list is missing.
Signed-off-by: Alex Bennée
---
scripts/ci/setup/ubuntu/build-environment.yml | 2 --
1 file changed, 2
Am 22.10.2024 um 08:00 hat Junjie Mao geschrieben:
>
> Paolo Bonzini writes:
>
> > On Tue, Oct 22, 2024 at 4:12 AM Junjie Mao wrote:
> >> > +($type:ident => $body:block) => {
> >> > +const _: () = {
> >> > +#[used]
> >> > +#[cfg_attr(
> >> > +
On 10/22/24 03:55, Alex Bennée wrote:
From: Ilya Leoshkevich
GCC produces invalid code for microblaze atomics.
The fix is unfortunately not upstream, so fetch it from an external
location and apply it locally.
Suggested-by: Peter Maydell
Signed-off-by: Ilya Leoshkevich
Message-Id: <20240919
On 10/22/24 03:55, Alex Bennée wrote:
Testing non-auto built docker containers (i.e. custom built compilers)
is a bit fiddly as you couldn't continue a build with a previously
locally built container. While you can play games with REGISTRY its
simpler to allow a NOFETCH that will go through the c
On 10/22/24 1:36 PM, Thomas Huth wrote:
On 20/10/2024 03.29, jro...@linux.ibm.com wrote:
From: Jared Rossi
We are already using the libc from SLOF for the s390-netboot.img, and
this libc implementation is way more complete and accurate than the
simple implementation that we currently use fo
Hi, Alex,
October 22, 2024 at 10:58 AM, "Alex Bennée" wrote:
> How easy would it be to expose a Rust API? I'm curious because now we
> are looking to integrate Rust into QEMU we could consider transitioning
> to a Rust API for plugins. It has been done before:
>
> https://github.com/novafacing/q
Hello,
Please ignore this mail,
I was doing some test and didn't realise real email was added.
I will resend the real one.
Thanks.
- Mail original -
De: "Matthieu Castet"
À: "castet matthieu"
Cc: "Peter Maydell" , "open list:ARM cores"
, "open list:All patches CC here"
Move error handling code to the end of the function so that it can more
easily be shared by new mmap failure conditions. No functional change
intended.
Signed-off-by: Alex Williamson
---
hw/vfio/helpers.c | 34 +-
1 file changed, 17 insertions(+), 17 deletions(-)
Thanks to work by Peter Xu, support is introduced in Linux v6.12 to
allow pfnmap insertions at PMD and PUD levels of the page table. This
means that provided a properly aligned mmap, the vfio driver is able
to map MMIO at significantly larger intervals than PAGE_SIZE. For
example on x86_64 (the o
As described in patch /2, newer kernels may support pfnmap with PMD or
PUD sized mappings. Mappings must be aligned in order to see the full
benefit of this support. We're largely able to get PMD alignment for
free from mmap, but PUD alignment requires some effort. Further, we
don't actually hav
Signed-off-by: Matthieu Castet
---
hw/intc/armv7m_nvic.c| 38 +-
target/arm/cpu.c | 4 ++--
target/arm/ptw.c | 23 +++
target/arm/tcg/cpu-v7m.c | 21 -
4 files changed, 74 insertions(+), 12 deletions(-
Am 21.10.2024 um 18:35 hat Paolo Bonzini geschrieben:
> Use the "struct update" syntax to initialize most of the fields to zero,
> and simplify the handmade type-checking of $name.
>
> Reviewed-by: Junjie Mao
> Signed-off-by: Paolo Bonzini
> ---
> rust/qemu-api/src/device_class.rs | 29 ++--
Per previous discussion [1,2], this patch deprecates query-migrationthreads
command.
To summarize, the major reason of the deprecation is due to no sensible way
to consume the API properly:
(1) The reported list of threads are incomplete (ignoring destination
threads and non-multifd threa
On 10/22/24 03:56, Alex Bennée wrote:
We didn't notice breakage of aarch64_be because we don't have any TCG
tests for it. However while the existing aarch64 compiler can target
big-endian builds no one packages a BE libc. Instead we bang some
rocks together to do the most basic of hello world wit
On 10/10/2024 18.20, Daniel P. Berrangé wrote:
From: Alejandro Zeise
Changes the public hash API implementation to support accumulative hashing.
Implementations for the public functions are added to call the new
driver functions that implement context creation, updating,
finalization, and dest
On 10/22/24 05:42, Bibo Mao wrote:
For user tcg, there is no physical cpu id provided and logic cpuid
is used. For system emulation, physical cpu id is provided, initial
value of register CSR CPUID can be set from physical cpu id.
Signed-off-by: Bibo Mao
---
hw/intc/loongarch_ipi.c
Am 22. Oktober 2024 14:53:31 UTC schrieb Michael Tokarev :
>On 13.02.2024 16:03, Philippe Mathieu-Daudé wrote:
>> We should not wire IRQs on unrealized device.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> Reviewed-by: Peter Maydell
>> Reviewed-by: Yoshinori Sato
>> ---
>> hw/sh4/r2d.c |
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