On 13/10/2024 17.27, Alex Bennée wrote:
Thomas Huth writes:
This patch series converts the tests/avocado/tuxrun_baselines.py
to the new functional test framework. While converting the sh4 test,
I noticed that the Avocado test was completely broken, so I included
a fix (revert) for that problem
> -Original Message-
> From: qemu-devel-bounces+chen.zhang=intel@nongnu.org devel-bounces+chen.zhang=intel@nongnu.org> On Behalf Of Peter Xu
> Sent: Friday, October 11, 2024 11:37 PM
> To: qemu-devel@nongnu.org
> Cc: Fabiano Rosas ; pet...@redhat.com; Yong Huang
> ; Zhang, Haili
> > > On 10/9/2024 11:56 AM, Chuang Xu wrote:
> > > > When QEMU is started with:
> > > > -cpu host,migratable=on,host-cache-info=on,l3-cache=off
> > > > -smp 180,sockets=2,dies=1,cores=45,threads=2
> > > >
> > > > On Intel platform:
> > > > CPUID.01H.EBX[23:16] is defined as "max number of address
Hi Stefan,
Thank you for the review comments! Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 13:02, Stefan Berger wrote:
On 9/12/24 12:09 PM, dan tan wrote:
From: dan tan
SPI interface to TPM TIS implemen
Hi Daniel,
Thanks for the reminder.
I'll take over Tommy's work to send out the v7 patchset later this week.
Regards,
Frank Chang
On Fri, Oct 11, 2024 at 7:38 PM Daniel Henrique Barboza <
dbarb...@ventanamicro.com> wrote:
> Hi Tommy,
>
>
> Do you plan to send a new version of this work soon? Th
On Wed, 9 Oct 2024 at 16:30, Jason Wang wrote:
>
> On Mon, Sep 30, 2024 at 12:01 AM Cindy Lu wrote:
> >
> > While the hardware MAC address is 0 and the MAC address in
> > the QEMU command line is also 0, this configuration is
> > acceptable.
> >
> > Signed-off-by: Cindy Lu
> > ---
> > hw/net/vi
On Wed, 9 Oct 2024 at 16:30, Jason Wang wrote:
>
> On Mon, Sep 30, 2024 at 12:01 AM Cindy Lu wrote:
> >
> > When using a VDPA device, the following situations are
> > also acceptable: the hardware MAC address is not 0,
> > and the MAC address in the QEMU command line is 0.
> >
> > Signed-off-by:
On 10/14/2024 8:36 AM, Xiaoyao Li wrote:
On 10/12/2024 5:35 PM, Chuang Xu wrote:
On 10/12/24 下午4:21, Xiaoyao Li wrote:
On 10/9/2024 11:56 AM, Chuang Xu wrote:
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2
On In
some 8 years ago this patch was sent to qemu-devel:
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg05333.html
"[Qemu-devel] [PATCH 7/7] Add ALSA ioctls"
I wonder why it was rejected, may be as part of series?
Right now I use OSS Proxy Daemon providing oss and ALSA output at the same
t
Hi Cédric,
Thank you for the review comments. Please see my response below.
thank you,
---
dan tan
power simulation
phone:+1.7373.099.138
email:dan...@linux.ibm.com
On 2024-09-12 12:20, Cédric Le Goater wrote:
Hello Dan,
On 9/12/24 18:09, dan tan wrote:
From: dan tan
SPI interface to TPM
On 10/12/2024 5:35 PM, Chuang Xu wrote:
On 10/12/24 下午4:21, Xiaoyao Li wrote:
On 10/9/2024 11:56 AM, Chuang Xu wrote:
When QEMU is started with:
-cpu host,migratable=on,host-cache-info=on,l3-cache=off
-smp 180,sockets=2,dies=1,cores=45,threads=2
On Intel platform:
CPUID.01H.EBX[23:16] is defi
In Chapter 5, Interruptions, the group 3 exceptions lists
"Unaligned data reference trap" has higher priority than
"Data memory break trap".
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
From: Paolo Bonzini
It is used in a couple of places only, both within the same target.
Those can use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini
Message-ID: <20241010083641.1785069-1-pbonz...@redhat.com>
Reviewed-by: Richard Henderson
Signed-off-by: Ric
Determine cache attributes, and thence Device vs Normal memory,
earlier in the function. We have an existing regime_is_stage2
if block into which this can be slotted.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 49 -
Fill in the tlb_fill_align hook. Handle alignment not due to
memory type, since that's no longer handled by generic code.
Pass memop to get_phys_addr.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 6 ++---
target/arm/cpu.c| 2 +-
ta
Now that we have the MemOp for the access, we can order
the alignment fault caused by memory type before the
permission fault for the page.
For subsequent page hits, permission and stage 2 checks
are known to pass, and so the TLB_CHECK_ALIGNED fault
raised in generic code is not mis-ordered.
Revi
Rename to use "memop_" prefix, like other functions
that operate on MemOp.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 4 ++--
accel/tcg/cputlb.c | 4 ++--
accel/tcg/
Add a new callback to handle softmmu paging. Return the page
details directly, instead of passing them indirectly to
tlb_set_page. Handle alignment simultaneously with paging so
that faults are handled with target-specific priority.
Route all calls of the two hooks through a tlb_fill_align
funct
This function is specific to MemOp, not TCG in general.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 23 +++
include/tcg/tcg.h| 23 ---
2 files c
Convert hppa_cpu_tlb_fill to hppa_cpu_tlb_fill_align so that we
can recognize alignment exceptions in the correct priority order.
Resolves: https://bugzilla.kernel.org/show_bug.cgi?id=219339
Tested-by: Helge Deller
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/cpu.
Pass memop through get_phys_addr_twostage with its
recursion with get_phys_addr_nogpc.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-
Just add the argument, unused at this point.
Zero is the safe do-nothing value for all callers.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h| 2 +-
target/hppa/int_helper.c | 2 +-
target/hppa/mem_helper.c | 9
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr_gpc and
get_phys_addr_with_space_nogpc.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 14 -
In Chapter 5, Interruptions, the group 3 exceptions lists
"Data memory access rights trap" in priority order ahead of
"Data memory protection ID trap".
Swap these checks in hppa_get_physical_address.
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 12 +
From: Ilya Leoshkevich
i386 gdbstub handles both i386 and x86_64. Factor out two functions
for reading and writing registers without knowing their bitness.
While at it, simplify the TARGET_LONG_BITS == 32 case.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-ID: <202409
From: Ilya Leoshkevich
Now that orig_ax is exposed and GDB is happy, don't skip
test-proc-mappings.py on i386. In fact, it's broken only on
m68k now, so skip only this architecture.
Acked-by: Alex Bennée
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240912093012.402366-6-...@linux.ibm.com>
Si
From: Thomas Huth
Since commit 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault")
a bunch of other "static inline" function are now unused, too. Clang
warns about such unused "static inline" functions in .c files, so the
build currently breaks when compiling with "--enable-werror". Remove
From: Ilya Leoshkevich
It's the same as env_cpu(), but for const objects.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240912093012.402366-2-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 13 -
linux-user/elflo
The following changes since commit 7e3b6d8063f245d27eecce5aabe624b5785f2a77:
Merge tag 'crypto-fixes-pull-request' of https://gitlab.com/berrange/qemu
into staging (2024-10-10 18:05:43 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tc
Drop the 'else' so that ret is overridden with the
highest priority fault.
Fixes: d8bc1381250 ("target/hppa: Implement PSW_X")
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/hppa/mem_helper.c | 8 +---
1 file changed, 5 insertions(
Zero is the safe do-nothing value for callers to use.
Pass the value through from get_phys_addr.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 11 ++-
1 file changed, 6 insertions(+), 5
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/ptw.c| 2 +-
target/arm/tcg/m_helper.c | 8
target/arm/tcg/tlb_helper.
From: Ilya Leoshkevich
Copy XML files describing orig_ax from GDB and glue them with
CPUX86State.orig_ax.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240912093012.402366-5-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
target/i386/cpu.h
Split out of mmu_lookup.
Reviewed-by: Helge Deller
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/memop.h | 24
accel/tcg/cputlb.c | 16 ++--
2 files changed, 26 insertions(+), 14 deletion
Zero is the safe do-nothing value for callers to use.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 3 ++-
target/arm/helper.c| 9 +
target/arm/ptw.c | 2 +-
3 files chan
Pass the value through from get_phys_addr_nogpc.
Reviewed-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/ptw.c b/target/a
There should be no "just in case"; the page is already
in the tlb, and known to be not readable.
Reviewed-by: Helge Deller
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cputl
From: Ilya Leoshkevich
The kernel uses orig_rax/orig_eax to store the syscall number before
a syscall. One can see this value in core dumps and ptrace.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-ID: <20240912093012.402366-3-...@linux.ibm.com>
Signed-off-by: Richard
When we have a tlb miss, defer the alignment check to
the new tlb_fill_align hook. Move the existing alignment
check so that we only perform it with a tlb hit.
Reviewed-by: Helge Deller
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 88 --
On 11.10.2024 19:18, Thomas Huth wrote:
Since commit 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault")
a bunch of other "static inline" function are now unused, too. Clang
warns about such unused "static inline" functions in .c files, so the
build currently breaks when compiling with "--
This argument is no longer used.
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/i386/tcg/sysemu/excp_helper.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/sysemu/excp_helper.c
b/target/i386/tcg/sysemu/e
Changes for v2:
- Improve probe_access_full{,_mmu} documentation
- Remove ra parameter from ptw_translate
r~
Richard Henderson (3):
include/exec: Improve probe_access_full{,_mmu} documentation
target/i386: Use probe_access_full_mmu in ptw_translate
target/i386: Remove ra parameter fro
Suggested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 29 ++---
1 file changed, 14 insertions(+), 15 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 72240ef426..2e4c4cc4b4 100644
--- a/include/exec/exec
The probe_access_full_mmu function was designed for this purpose,
and does not report the memory operation event to plugins.
Cc: qemu-sta...@nongnu.org
Fixes: 6d03226b422 ("plugins: force slow path when plugins instrument memory
ops")
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathie
Il sab 12 ott 2024, 16:02 Peter Maydell ha
scritto:
> Deleting the whole subprojects/unicode-ident-1-rs/ subdirectory
> seems to have fixed this -- it then realised it needed to
> do the download and put it in the right place. I guess that was a
> leftover from trying to build the previous versio
On 10/11/24 09:18, Thomas Huth wrote:
Since commit 95b9c27c81 ("linux-user: Remove unused handle_vm86_fault")
a bunch of other "static inline" function are now unused, too. Clang
warns about such unused "static inline" functions in .c files, so the
build currently breaks when compiling with "--en
On 10/11/24 09:24, Peter Maydell wrote:
Currently we store the FPSR cumulative exception bits in the
float_status fields, and use env->vfp.fpsr only for the NZCV bits.
(The QC bit is stored in env->vfp.qc[].)
This works for TCG, but if QEMU was built without CONFIG_TCG (i.e.
with KVM support onl
On 10/10/24 01:36, Paolo Bonzini wrote:
It is used in a couple of places only, both within the same target. Those can
use the cflags just as well, so remove the separate field.
Signed-off-by: Paolo Bonzini
---
include/exec/translator.h | 2 --
accel/tcg/translator.c | 1 -
target/mip
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
mips_cpu_create_with_clock() creates a vCPU. Pass it the vCPU
endianness requested by argument. Update the board call sites.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
---
target/mips/cpu.h| 4 +
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Have the CPS expose a 'cpu-big-endian' property so it can
set it to the vCPUs it creates.
Note, since the number of vCPUs created is dynamic, we can
not use QOM aliases.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jia
Hi,
I think there maybe some bugs caused by the recent crypto patches that got
merged to master. ref:
https://lore.kernel.org/qemu-devel/cafeaca-e_1wflun2hpttt2bszxksmbnxkak_uzuhwrh_fb6...@mail.gmail.com/T/#t
I think before these patches the "qcrypto_hash_bytes" or
"qcrypto_hash_bytesv" apis used
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
---
target/mips/cpu.h | 3 +++
target/mips/cpu.c | 12
2 files changed,
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Replace tcg_gen_movi_tl() + gen_op_addr_add() by a single
gen_op_addr_addi() call.
gen_op_addr_addi() calls tcg_gen_addi_tl() which might
optimize if the immediate is zero.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson
r~
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
+++ b/target/mips/tcg/msa_helper.c
@@ -8213,7 +8213,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t
df, uint32_t wd,
#if !defined(CONFIG_USER_ONLY)
#define MEMOP_IDX(DF) \
-
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Introduce mo_endian() which returns the endian MemOp
corresponding to the vCPU DisasContext.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
---
target/mips/tcg/translate.h | 5 +
1 file changed, 5 inse
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
In commit 6d0cad12594 ("target/mips: Finish conversion to
tcg_gen_qemu_{ld,st}_*") we renamed the argument of the user
definition. Rename the system part for coherency. Since the
argument is ignored, prefix with 'ignored_'.
Signed-off-by: Philippe
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Extract the implicit MO_TE definition in order to replace
it by runtime variable in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Instead of swapping the reversed target endianness
using MO_BSWAP, directly return the correct endianness.
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg/translate.h | 5 +
target/mips/tcg/mxu_
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Replace compile-time MO_TE evaluation by runtime mo_endian_env()
one, which expand target endianness from vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
---
target/mips/tcg/sysemu/tlb_helper.c | 2
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Introduce mo_endian_env() which returns the endian
MemOp corresponding to the vCPU env.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
---
target/mips/internal.h | 5 +
1 file changed, 5 insertions(+)
On 10/10/24 14:50, Philippe Mathieu-Daudé wrote:
Methods using the 'cpu_' prefix usually take a (Arch)CPUState
argument. Since this method takes a DisasContext argument,
rename it as disas_is_bigendian().
Suggested-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
---
target/mips/tcg
On 10/10/24 14:49, Philippe Mathieu-Daudé wrote:
In order to re-use cpu_is_bigendian(), declare it on "internal.h"
after renaming it as mips_env_is_bigendian().
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Signed-off-by: Philippe Mathieu-Daudé
Message-Id:<20241004162118.84570-6-phi...@linaro.
Thomas Huth writes:
> This patch series converts the tests/avocado/tuxrun_baselines.py
> to the new functional test framework. While converting the sh4 test,
> I noticed that the Avocado test was completely broken, so I included
> a fix (revert) for that problem in this series, too.
How can I ru
+atexit(drain_call_rcu);
rcu_register_thread();
}
---
base-commit: 31669121a01a14732f57c49400bc239cf9fd505f
change-id: 20241013-rcu-b4864052a103
Best regards,
--
Akihiko Odaki
65 matches
Mail list logo
