Variable env->cf[i] is defined as bool type, it is treated as int type
with shift operation. However the max possible width is 56 for the shift
operation, exceeding the width of int type. And there is existing api
read_fcc() which is converted to u64 type with bitwise shift, it can be
used to dump
Add support to retrieve mpidr value via qom-get.
Signed-off-by: Mauro Carvalho Chehab
---
scripts/arm_processor_error.py | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/scripts/arm_processor_error.py b/scripts/arm_processor_error.py
index 62e0c566
While the spec defines a CPER size of 4KiB for each record,
currently it is set to 1KiB. Fix the documentation and add
a pointer to the macro name there, as this may help to keep
it updated.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
---
docs/specs/acpi_hest_ghes.rst | 6 -
This series add support for injecting generic CPER records. Such records
are generated outside QEMU via a provided script.
On this version, the patch reworking the way offsets are calculated were
split on several other patches, to make one logical change per patch and
make review easier.
Despi
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
if physical_address is not defined, just return with an error
set.
That reduces the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 56 ++
1 file changed
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/acpi/g
The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c | 2 +-
include/hw/acpi/
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Reviewed-by: Igor Mammedov
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 32 +++-
1 file chan
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill GEGB part of the record.
The remaining code t
Creates a QMP command to be used for generic ACPI APEI hardware error
injection (HEST) via GHESv2, and add support for it for ARM guests.
Error injection uses ACPI_HEST_SRC_ID_QMP source ID to be platform
independent. This is mapped at arch virt bindings, depending on the
types supported by QEMU a
GHES has two fields with somewhat meanings:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
between different implemented hardware report mec
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported.
Signed-off-by: Mauro Carvalho Chehab
---
MAINTAINERS| 3 +
scrip
Instead, produce an error and continue working
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c
index f54865423f69..e47c0238f3c5 100644
--- a/hw/acpi/ghes.c
+++ b/hw/acpi/ghes.c
@@ -421
Store HEST table address at GPA, placing its content at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
---
Change from v8:
- hest_addr_lr is now pointing to the error source size and data.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 15 +++
incl
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 7 ++-
include/hw/acpi/ghes.h | 3 ++-
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/acpi/ghes.c b/h
The current logic is based on a lot of duct tape, with
offsets calculated based on one define with the number of
source IDs and an enum.
Rewrite the logic in a way that it would be more resilient
of code changes, by moving the source ID count to an enum
and make the offset calculus more explicit.
HEST source ID is actually a 16-bit value. Yet, make it a little
bit more generic using just an integer type.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes-stub.c| 2 +-
hw/acpi/ghes.c | 2 +-
include/hw/acpi/ghes.h | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
di
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
The number of sources is architecture-dependent. Usually,
architectures will implement one synchronous and/or one
asynchronous source.
Change the logic to better cope with such model.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 53 +++-
The GHES migration logic at GED should now support HEST table
location too.
Increase migration version and change needed to check for both
ghes_addr_le and hest_addr_le.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/generic_event_device.c | 11 ++-
1 file changed, 6 insertions(+), 5
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
---
hw/acpi/ghes.c | 5 +
include/hw/acpi/ghes.h | 3 +++
2 files changed, 8 insertions(+)
diff
Accurately injecting an ARM Processor error ACPI/APEI GHES
error record requires the value of the ARM Multiprocessor
Affinity Register (mpidr).
While ARM implements it, this is currently not visible.
Add a field at CPU storing it, and place it at arm_cpu_properties
as experimental, thus allowing
Manos Pitsidianakis writes:
> Add rust/qemu-api, which exposes rust-bindgen generated FFI bindings and
> provides some declaration macros for symbols visible to the rest of
> QEMU.
>
> Co-authored-by: Junjie Mao
> Co-authored-by: Paolo Bonzini
> Signed-off-by: Junjie Mao
> Signed-off-by: Paolo
Em Fri, 13 Sep 2024 14:28:02 +0200
Igor Mammedov escreveu:
> > > 5. Just return an error code without doing any resets. To me, this is
> > >the worse scenario.
> > >
> > > I don't like (5), as if something bad happens, there's nothing to be
> > > done.
> >
> > If it happens on a real s
Hi Igor,
Em Fri, 13 Sep 2024 15:25:18 +0200
Igor Mammedov escreveu:
> > > in addition to this, it needs a patch on top to make sure
> > > that we migrate hest_addr_le.
> > > See a08a64627b6b 'ACPI: Record the Generic Error Status Block address'
> > > and fixes on top of that for an example.
On 9/11/24 03:28, Peter Maydell wrote:
> On Wed, 11 Sept 2024 at 07:27, Jacob Abrams wrote:
>> On 9/10/24 02:34, Peter Maydell wrote:
>>> If we make the .impl and .valid changes, then the result is
>>> that we permit 16 bit writes to come through to the read
>>> and write functions. Since we do
On 2024/9/14 上午10:58, Richard Henderson wrote:
On 9/13/24 18:43, Bibo Mao wrote:
Variable env->cf[i] is defined as bool type, it cannot be used with left
shifting operation.
Not true; it promotes to 'int'. But that isn't wide enough for the
value that you're trying to construct.
yeap, yo
On 9/13/24 18:43, Bibo Mao wrote:
Variable env->cf[i] is defined as bool type, it cannot be used with left
shifting operation.
Not true; it promotes to 'int'. But that isn't wide enough for the value that you're
trying to construct.
There is existing api read_fcc(), it can be used when
du
On 2024-09-10 10:06 p.m., Brian Cain wrote:
On 9/10/2024 5:26 PM, Brad Smith wrote:
On 2024-09-10 4:17 p.m., Thomas Huth wrote:
Some systems (like OpenBSD) do not have the sha256sum or sha512sum
programs
installed by default. Use the Python hashlib instead so we don't
have to
rely on the ext
On 2024/9/13 下午8:41, Igor Mammedov wrote:
On Wed, 11 Sep 2024 11:09:21 +0800
Bibo Mao wrote:
Macro definition is added for acpi sleep control register, so that
ged emulation driver can use this, also it can be used in FDT table if
ged is exposed with FDT table.
Signed-off-by: Bibo Mao
---
On 2024/9/14 上午1:19, Philippe Mathieu-Daudé wrote:
On 12/9/24 04:35, Bibo Mao wrote:
From: bibo mao
For header file hw/intc/loongarch_pch_pic.h, add common file
hw/intc/loongarch_pic_common.h and remove duplicated macro definition
in file loongarch_pch_pic.h
Signed-off-by: Bibo Mao
---
Variable env->cf[i] is defined as bool type, it cannot be used with left
shifting operation. There is existing api read_fcc(), it can be used when
dumping fp registers into coredump note segment.
Resolves: Coverity CID 1561133
Signed-off-by: Bibo Mao
---
target/loongarch/arch_dump.c | 6 +-
Hello Guenter, Gerd,
Thanks for bringing up the question. To be honest I do not know a lot about
USB internals.
When adding the orangepi-pc board emulation, it seemed fairly easy to add
it, but apart from a few basic tests, I did not use the USB functionality
extensively.
I do own the actual Oran
Fix a segmentation fault in multifd when rb->receivedmap is cleared
too early.
After commit 5ef7e26bdb ("migration/multifd: solve zero page causing
multiple page faults"), multifd started using the rb->receivedmap
bitmap, which belongs to ram.c and is initialized and *freed* from the
ram SaveVMHan
There are two qemu_loadvm_state_cleanup() calls that were introduced
when qemu_loadvm_state_setup() was still called before loading the
configuration section, so there was state to be cleaned up if the
header checks failed.
However, commit 9e14b84908 ("migration/savevm: load_header before
load_set
This fixes the crash we've been seing recently in migration-test. The
first patch is a cleanup to have only one place calling
qemu_loadvm_state_cleanup() and the second patch reorders the cleanup
calls to make multifd_recv_cleanup() run first and stop the recv
threads.
CI run: https://gitlab.com/f
Maybe a line like "See the justification in the next commit"?
On 10/9/24 23:23, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 12 ++--
tcg/tcg-op.c | 23 +++
2 files changed, 21 insertions(+), 14 deletions(-)
On Thu, Sep 12, 2024 at 07:19:16PM +0800, Changqi Lu wrote:
> +static int nvme_read_reservation_cb(NvmeReadReservation *reservation)
> +{
> +int rc;
> +NvmeReservationStatus *nvme_status;
> +NvmeRequest *req = reservation->req;
> +NvmeCtrl *n = req->sq->ctrl;
> +NvmeResvKeys *ke
On 9/13/24 11:44, scan-ad...@coverity.com wrote:
** CID 1561133: Integer handling issues (BAD_SHIFT)
/builds/qemu-project/qemu/target/loongarch/arch_dump.c: 102 in
loongarch_write_elf64_fprpreg()
__
v3: Fixed TMP105 tests
The following changes since commit 28ae3179fc52d2e4d870b635c4a412aab99759e7:
Merge tag 'pull-target-arm-20240913' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-09-13
16:14:33 +0100)
are available in the Git repository at:
https://
From: Guenter Roeck
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit
of the limit registers are unused and always report 0.
The lower 4 bit should not be used for temperature comparisons,
so mask the unused bits before storing the limits.
Signed-off-by: Guenter Roeck
Reviewed-by:
Mux is a character backend (host side) device, which multiplexes
multiple frontends with one backend device. The following is a
few lines from the QEMU manpage [1]:
A multiplexer is a "1:N" device, and here the "1" end is your
specified chardev backend, and the "N" end is the various parts
o
This patch implements multiplexing capability of several backend
devices, which opens up an opportunity to use a single frontend
device on the guest, which can be manipulated from several
backend devices.
The idea of the change is trivial: keep list of backend devices
(up to 4), init them on deman
This adds a few lines describing multiplexer configuration for
multiplexing several backend devices with a single frontend
device.
Signed-off-by: Roman Penyaev
Cc: "Marc-André Lureau"
Cc: Paolo Bonzini
Cc: qemu-devel@nongnu.org
---
qemu-options.hx | 44 -
On 13/9/24 19:26, Alex Bennée wrote:
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Tested-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-3-rowanbh...@gmail.com>
[AJB: tweak fmt string for vaddr]
Signed-off-by: Alex Bennée
---
vAJB
- tweak fmt string f
On 13/9/24 19:26, Alex Bennée wrote:
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-2-rowanbh...@gmail.com>
[AJB: tweaked cpu_memory_rw_debug call]
Signed-off-by: Alex Bennée
---
vAJB:
- explicit bool for cpu_memory_rw_debug
--
On 13/9/24 19:26, Alex Bennée wrote:
While the compilers will generally happily synthesise a 64 bit value
for you on 32 bit systems it doesn't exercise anything on QEMU. It
also makes it hard to accurately compare the accesses to test_data
when instrumenting.
Message-Id: <20240910140733.4007719-
On 13/9/24 19:51, Thomas Huth wrote:
Commit d2fce37597c2 added a test that downloads an asset from the
internet, so this test should not be run by default anymore and be
put into the thorough category instead.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 5 +
1 file chan
Cc: qemu-sta...@nongnu.org
stable-8.2, stable-9.0 and stable-9.1
> From: Volker Rümelin
>
> Currently, the guest may write to the device configuration space,
> whereas the virtio sound device specification in chapter 5.14.4
> clearly states that the fields in the device configuration space
> are
Peter Xu writes:
> On Fri, Sep 13, 2024 at 12:04:00PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Fri, Sep 13, 2024 at 10:21:39AM -0300, Fabiano Rosas wrote:
>> >> Peter Xu writes:
>> >>
>> >> > On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote:
>> >> >> Peter Xu w
ilable in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git
> tags/pull-target-arm-20240913
>
> for you to fetch changes up to 110684c9a69a02cbabfbddcd3afa921826ad565c:
>
> hw/intc/arm_gic: fix spurious leve
Commit d2fce37597c2 added a test that downloads an asset from the
internet, so this test should not be run by default anymore and be
put into the thorough category instead.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff
Peter Xu writes:
> On Fri, Sep 13, 2024 at 12:17:40PM -0300, Fabiano Rosas wrote:
>> Fabiano Rosas writes:
>>
>> > Peter Xu writes:
>> >
>> >> On Thu, Sep 12, 2024 at 07:52:48PM -0300, Fabiano Rosas wrote:
>> >>> Fabiano Rosas writes:
>> >>>
>> >>> > Peter Xu writes:
>> >>> >
>> >>> >> On T
Although we asks for instructions per second we work in quanta and
that cannot be 0. Fail to load the plugin instead and report the
minimum IPS we can handle.
Signed-off-by: Alex Bennée
Reported-by: Elisha Hollander
---
contrib/plugins/ips.c | 5 +
1 file changed, 5 insertions(+)
diff --gi
From: Akihiko Odaki
SimPoint is a widely used tool to find the ideal microarchitecture
simulation points so Valgrind[2] and Pin[3] support generating basic
block vectors for use with them. Let's add a corresponding plugin to
QEMU too.
Note that this plugin has a different goal with tests/plugin/
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Tested-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-3-rowanbh...@gmail.com>
[AJB: tweak fmt string for vaddr]
Signed-off-by: Alex Bennée
---
vAJB
- tweak fmt string for PRIu64
---
docs/about/emulation.rst
From: Rowan Hart
Signed-off-by: Rowan Hart
Reviewed-by: Pierrick Bouvier
Message-Id: <20240827215329.248434-2-rowanbh...@gmail.com>
[AJB: tweaked cpu_memory_rw_debug call]
Signed-off-by: Alex Bennée
---
vAJB:
- explicit bool for cpu_memory_rw_debug
---
include/qemu/qemu-plugin.h | 32 +++
The softmmu memory instrumentation test sees so many more accesses
than a normal translated host and its really not worth fixing up. Lets
deprecate this odd configuration and save on the CI cycles.
Message-Id: <20240910140733.4007719-13-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed
At first I thought I could compile the user-mode test for system mode
however we already have a fairly comprehensive test case for system
mode in "memory" so lets use that.
As tracking every access will quickly build up with "print-access" we
add a new mode to track groups of reads and writes to r
This is useful information when debugging memory issues so lets
improve by:
- include the ptr address for u8 fills (like the others)
- indicate the number of operations for reads and writes
- explicitly note when we are flushing
- move the fill printf to after the reset
Message-Id: <20240
The existing plugins already liberally use host pointer stuffing for
passing user data which will fail when doing 64 bit guests on 32 bit
hosts. We should discourage this by officially deprecating support and
adding another nail to the 32 bit host coffin.
Message-Id: <20240910140733.4007719-12-ale
When we shut down a guest we disable the timers. However this can
cause deadlock if the guest has queued some async work that is trying
to advance system time and spins forever trying to wind time forward.
Pay attention to the return code and bail early if we can't wind time
forward.
Signed-off-by
This is a simple control flow tracking plugin that uses the latest
inline and conditional operations to detect and track control flow
changes. It is currently an exercise at seeing how useful the changes
are.
Reviewed-by: Pierrick Bouvier
Message-Id: <20240910140733.4007719-14-alex.ben...@linaro.
From: Pierrick Bouvier
A specific plugin test can now read and check a plugin output, to ensure
it contains expected values.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Message-Id: <20240724194708.1843704-5-pierrick.bouv...@linaro.org>
Signed-off-by:
The multiarch system tests output serial data which should be
redirected to the "output" chardev rather than echoed to the console.
Remove the unused EXTFLAGS variable while we are at it.
Signed-off-by: Alex Bennée
---
tests/tcg/s390x/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(
While the compilers will generally happily synthesise a 64 bit value
for you on 32 bit systems it doesn't exercise anything on QEMU. It
also makes it hard to accurately compare the accesses to test_data
when instrumenting.
Message-Id: <20240910140733.4007719-21-alex.ben...@linaro.org>
Reviewed-by:
From: Pierrick Bouvier
Add an explicit test to check expected memory values are read/written.
8,16,32 load/store are tested for all arch.
64,128 load/store are tested for aarch64/x64.
atomic operations (8,16,32,64) are tested for x64 only.
By default, atomic accesses are non atomic if a single c
From: Pierrick Bouvier
Different code paths handle memory accesses:
- tcg generated code
- load/store helpers
- atomic helpers
This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are
written only for accessed word size (upper bits are not set).
Atomic operations are doing read/w
From: Pierrick Bouvier
This value can be accessed only during a memory callback, using
new qemu_plugin_mem_get_value function.
Returned value can be extended when QEMU will support accesses wider
than 128 bits.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1719
Resolves: https://gitla
From: Pierrick Bouvier
By using "print-accesses=true" option, mem plugin will now print every
value accessed, with associated size, type (store vs load), symbol,
instruction address and phys/virt address accessed.
Reviewed-by: Richard Henderson
Reviewed-by: Xingtao Yao
Signed-off-by: Pierrick
I think all these are ready to go having been mostly reviewed in previous
series. The following still need review:
util/timer: avoid deadlock when shutting down
tests/tcg: add a system test to check memory instrumentation
tests/tcg: ensure s390x-softmmu output redirected
tests/tcg/multiarc
From: Pierrick Bouvier
Only multiarch tests are run with plugins, and we want to be able to run
per-arch test with plugins too.
Tested-by: Xingtao Yao
Reviewed-by: Richard Henderson
Signed-off-by: Pierrick Bouvier
Message-Id: <20240724194708.1843704-4-pierrick.bouv...@linaro.org>
Signed-off-b
On 12/9/24 04:35, Bibo Mao wrote:
From: bibo mao
For header file hw/intc/loongarch_pch_pic.h, add common file
hw/intc/loongarch_pic_common.h and remove duplicated macro definition
in file loongarch_pch_pic.h
Signed-off-by: Bibo Mao
---
include/hw/intc/loongarch_pch_pic.h | 36 +-
On 13/9/24 16:48, Thomas Huth wrote:
The pci-bridge device is not usable on s390x, so introduce a Kconfig
switch that allows to disable it.
Signed-off-by: Thomas Huth
---
hw/pci-bridge/Kconfig | 5 +
hw/pci-bridge/meson.build | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
On 13/9/24 16:30, Peter Maydell wrote:
On Thu, 12 Sept 2024 at 07:53, Philippe Mathieu-Daudé wrote:
v2:
- Fill Pierrick's commit description suggested by Eric Blake
- Include TMP105 fixes from Guenter
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
Merge tag '
On Fri, 13 Sept 2024 at 16:55, Peter Xu wrote:
>
> On Thu, Sep 12, 2024 at 03:27:55PM +0100, Peter Maydell wrote:
> > Coverity is pretty unhappy about this trick, because it isn't able
> > to recognise that we can figure out the address of 'bounce'
> > from the address of 'bounce->buffer' and free
This would ease debugging of write zeroes and discard operations.
Signed-off-by: Andrey Drobyshev
Reviewed-by: Alexander Ivanov
Reviewed-by: Alberto Garcia
---
block/file-posix.c | 1 +
block/trace-events | 1 +
2 files changed, 2 insertions(+)
diff --git a/block/file-posix.c b/block/file-pos
We are going to need it for discarding separate subclusters. The
function itself doesn't do anything with the refcount tables, it simply
adds a discard request to the queue, so rename it to qcow2_queue_discard().
Signed-off-by: Andrey Drobyshev
Reviewed-by: Alexander Ivanov
Reviewed-by: Hanna C
This helper simply obtains the l2 table parameters of the cluster which
contains the given subclusters range. Right now this info is being
obtained and used by zero_l2_subclusters(). As we're about to introduce
the subclusters discard operation, this helper would let us avoid code
duplication.
A
When zeroizing the last non-zero subclusters within single cluster, it
makes sense to go zeroize the entire cluster and go down zero_in_l2_slice()
path right away. That way we'd also update the corresponding refcount
table.
Signed-off-by: Andrey Drobyshev
Reviewed-by: Alexander Ivanov
Reviewed-
This commit makes the discard operation work on the subcluster level
rather than cluster level. It introduces discard_l2_subclusters()
function and makes use of it in qcow2 discard implementation, much like
it's done with zero_in_l2_slice() / zero_l2_subclusters(). It also
changes the qcow2 drive
When zeroizing subclusters within single cluster, detect usage of the
BDRV_REQ_MAY_UNMAP flag and fall through to the subcluster-based discard
operation, much like it's done with the cluster-based discards. That
way subcluster-aligned operations "qemu-io -c 'write -z -u ...'" will
lead to actual u
Add a bunch of test cases covering new subclusters behaviour: unmap of
last allocated subclusters; unmap of subclusters within unallocated
cluster; discard of unallocated subclusters within a cluster; regular discard
of subclusters within a cluster; discard of last allocated subclusters.
Also make
Move the definition from iotests/250 to common.rc. This is used to
detect real disk usage of sparse files. In particular, we want to use
it for checking subclusters-based discards.
Signed-off-by: Andrey Drobyshev
Reviewed-by: Alexander Ivanov
Reviewed-by: Alberto Garcia
---
tests/qemu-iotest
We basically fill 2 images with identical data and perform discard
operations with and without 'discard-no-unref' enabled. Then we check
that images still read identically, that their disk usage is the same
(i.e. fallocate(FALLOC_FL_PUNCH_HOLE|FALLOC_FL_KEEP_SIZE) is called for
both) and that with
Introduce Qcow2 runtime boolean option "discard-subclusters". This
option influences discard alignment value (either cluster_size or
subcluster_size) and essentially makes subcluster-based discard optional.
We disable it by default.
Also tweak iotests/271 to enable this option and really test sub
Commits 42a2890a and b2b10904 introduce handling of discard-no-unref
option in discard_in_l2_slice() and zero_in_l2_slice(). They add even
more if's when chosing the right l2 entry. What we really need for this
option is the new entry simply to contain the same host cluster offset,
no matter whet
v2: https://lists.nongnu.org/archive/html/qemu-devel/2024-05/msg02396.html
v2 -> v3:
* Added patch 12/12 "qcow2: add discard-subclusters option" which
makes subcluster-based discards optional;
* Added a bunch of R-b's.
Andrey Drobyshev (12):
qcow2: make function update_refcount_discard(
Normally discard requests are stored in the queue attached to BDRVQcow2State
to be processed later at once. Currently discard-no-unref option handling
causes these requests to be processed straight away. Let's fix that.
Note that when doing regular discards qcow2_free_any_cluster() would check
f
On 9/13/24 03:23, Alex Bennée wrote:
Note that the branch is X < 0 (unsigned), which is always false, and
thus the branch is optimized away.
I'm obviously missing something reading this. How can TCG know the state
of the scoreboard variables and optimise away the branch?
0 < 0 is of course fa
From: Frederic Barrat
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This
patch defines it.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
---
include/hw/ppc/xive_regs.h | 1 +
hw/intc/xive.c | 4
2 files changed, 5 ins
From: Michael Kowal
Making some pre-requisite alignment changes ahead of the following patch
sets. Making these changes now will ease the review of the patch sets.
Checkpatch wants the closing comment '*/' on a separate line, unless it is
on the same line as the starting comment '/*'.
There ar
From: Glenn Miles
Adds support for single byte read of offset 0x838 of the TIMA address
space. According to the XIVE2 Specification, this causes the hardware
to atomically:
1. Read the number of bytes requested (lbz or lhz are supported).
2. Reset the valid bit of the thread context.
3. Re
From: Glenn Miles
Hypervisor "pool" targets do not get their own interrupt line and instead
must share an interrupt line with the hypervisor "physical" targets.
This also means that the pool ring must use some of the registers from the
physical ring in the TIMA. Specifically, the NSR, PIPR and C
From: Glenn Miles
PHYP uses 8-byte writes to the 2nd doubleword of the OS context
line when dispatching an OS level virtual processor. This
support was not used by OPAL/Linux and so was never added.
Without this support, the XIVE code doesn't notice that a new
context is being pushed and fails
From: Frederic Barrat
The 'info pic' HMP command dumps the state of the interrupt controller.
Add the dump of the NVG and NVC tables to its output to ease debug.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
---
include/hw/ppc/xive2.h | 12 +++
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified by the NVT structure indexed by the THREA
From: Glenn Miles
Current code was updating the PIPR inside the xive_tctx_accept() function
instead of the xive_tctx_set_cppr function, which is where the HW would
have it updated.
Moved the update to the xive_tctx_set_cppr function which required
additional support for pool interrupts.
Fixes:
Some of the TIMA Special CI operations perform the same operation at
alternative byte offsets and lengths. The following
xive2_tm_opertions[] table entries are missing when they exist for
other offsets/sizes and have been added:
- lwz@0x810 Pull/Invalidate O/S Context to registeradded
lwz@0x
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