Re: [PATCH v9 01/12] acpi/ghes: add a firmware file with HEST address

Em Wed, 11 Sep 2024 15:51:08 +0200 Igor Mammedov escreveu: > On Sun, 25 Aug 2024 05:45:56 +0200 > Mauro Carvalho Chehab wrote: > > > Store HEST table address at GPA, placing its content at > > hest_addr_le variable. > > > > Signed-off-by: Mauro Carvalho Chehab > > This looks good to me. >

Re: [PATCH v8 06/13] acpi/ghes: add support for generic error injection via QAPI

Em Thu, 12 Sep 2024 14:42:33 +0200 Igor Mammedov escreveu: > On Wed, 11 Sep 2024 16:34:36 +0100 > Jonathan Cameron wrote: > > > On Wed, 11 Sep 2024 15:21:32 +0200 > > Igor Mammedov wrote: > > > > > On Sun, 25 Aug 2024 05:29:23 +0200 > > > Mauro Carvalho Chehab wrote: > > > > > > > Em Mon,

Re: [PATCH] target/ppc: Fix lxv/stxv MSR facility check

Hi Fabiano, On 9/10/24 04:36, Fabiano Rosas wrote: Nicholas Piggin writes: The move to decodetree flipped the inequality test for the VEC / VSX MSR facility check. This caused application crashes under Linux, where these facility unavailable interrupts are used for lazy-switching of VEC/VSX

[PATCH] target/ppc: Fix inequality check in do_lstxv_X

This fix was earlier introduced for do_lstxv_D form with 2cc0e449d173 however got missed for _X form. This patch fixes the same. Cc: qemu-sta...@nongnu.org Suggested-by: Fabiano Rosas Fixes: 70426b5bb738 ("target/ppc: moved stxvx and lxvx from legacy to decodtree") Signed-off-by: Harsh Prateek B

Re: [PATCH v2 5/7] target/ppc: optimize p9 exception handling routines for lpcr

Hi Nick, On 7/4/24 13:13, Nicholas Piggin wrote: On Thu May 23, 2024 at 3:14 PM AEST, Harsh Prateek Bora wrote: Like pending_interrupts, env->spr[SPR_LPCR] is being used at multiple places across p9 exception handlers. Pass the value during entry and avoid multiple indirect accesses. Ditto fo

[PATCH v3 09/10] target/ppc: simplify var usage in ppc_next_unmasked_interrupt

As previously done for arch specific handlers, simplify var usage in ppc_next_unmasked_interrupt by caching the env->pending_interrupts and env->spr[SPR_LPCR] in local vars and using it later at multiple places. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 54

[PATCH v3 02/10] target/ppc: optimize hreg_compute_pmu_hflags_value

Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple conditions to avoid multiple indirect accesses. Signed-off-by: Harsh Prateek Bora Reviewed-by: Nicholas Piggin --- target/ppc/helper_regs.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target

[PATCH v3 04/10] target/ppc: optimize p9 exception handling routines

Currently, p9 exception handling has multiple if-condition checks where it does an indirect access to pending_interrupts via env. Pass the value during entry to avoid multiple indirect accesses. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 47 +

[PATCH v3 10/10] target/ppc: combine multiple ail checks into one

ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary. Combine them as appropriate. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c

[PATCH v3 05/10] target/ppc: optimize p9 exception handling routines for lpcr

Like pending_interrupts, env->spr[SPR_LPCR] is being used at multiple places across p9 exception handlers. Pass the value during entry and avoid multiple indirect accesses. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 33 ++--- 1 file changed, 18 i

[PATCH v3 01/10] target/ppc: use locally stored msr and avoid indirect access

hreg_compute_hflags_value already stores msr locally to be used in most of the logic in the routine however some instances are still using env->msr which is unnecessary. Use locally stored value as available. Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora --- target/ppc/helper_r

[PATCH v3 06/10] target/ppc: reduce duplicate code between init_proc_POWER{9, 10}

Historically, the registration of sprs have been inherited alongwith every new Power arch support being added leading to a lot of code duplication. It's time to do necessary cleanups now to avoid further duplication with newer arch support being added. Signed-off-by: Harsh Prateek Bora --- targe

[PATCH v3 03/10] target/ppc: optimize hreg_compute_pmu_hflags_value

The second if-condition can be true only if the first one above is true. Enclose the latter into the former to avoid un-necessary check if first condition fails. Reviewed-by: BALATON Zoltan Reviewed-by: Nicholas Piggin Signed-off-by: Harsh Prateek Bora --- target/ppc/helper_regs.c | 6 +++---

[PATCH v3 07/10] target/ppc: optimize p8 exception handling routines

Most of the p8 exception handling accesses env->pending_interrupts and env->spr[SPR_LPCR] at multiple places. Passing it directly as local variables simplifies the code and avoids multiple indirect accesses. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 60

[PATCH v3 00/10] misc ppc improvements/optimizations

This a set of misc ppc arch specific code improvements/optimizations. This version of series extended improvements to p7 and p8 alongwith additional minor improvements. Since patch 7/7 of v2 series have been picked by Aditya in his patchset for P11 support, I have excluded that patch in this serie

[PATCH v3 08/10] target/ppc: optimize p7 exception handling routines

Like p8 and p9, simplifying p7 exception handling rotuines to avoid un-necessary multiple indirect accesses to env->pending_interrupts and env->spr[SPR_LPCR]. Signed-off-by: Harsh Prateek Bora --- target/ppc/excp_helper.c | 46 ++-- 1 file changed, 25 insertio

Re: [PATCH] docs/fuzz: fix outdated mention to enable-sanitizers

On 9/12/2024 7:47 AM, Matheus Tavares Bernardino wrote: This options has been removed at cb771ac1f5 (meson: Split --enable-sanitizers to --enable-{asan, ubsan}, 2024-08-13), so let's update its last standing mention in the docs. Signed-off-by: Matheus Tavares Bernardino --- docs/devel/testi

[PATCH v16 06/13] s390x/pci: Check for multifunction after device realization

The SR-IOV PFs set the multifunction bit during device realization so check them after that. There is no functional change because we explicitly ignore the multifunction bit for SR-IOV devices. Signed-off-by: Akihiko Odaki --- hw/s390x/s390-pci-bus.c | 28 +--- 1 file cha

[PATCH v16 10/13] pcie_sriov: Remove num_vfs from PCIESriovPF

num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 1 - hw/pci/pcie_sriov.c | 38 +++--- hw/pci/trace-events | 2 +- 3 files changed, 28 insertions(+), 13

[PATCH v16 01/13] hw/pci: Rename has_power to enabled

The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 7 ++- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c| 14 +++--- hw/pci/pci_host

[PATCH v16 11/13] pcie_sriov: Register VFs after migration

pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- in

[PATCH v16 09/13] pcie_sriov: Release VFs failed to realize

Release VFs failed to realize just as we do in unregister_vfs(). Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri

[PATCH v16 13/13] hw/qdev: Remove opts member

It is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- include/hw/qdev-core.h | 4 hw/core/qdev.c | 1 - system/qdev-monitor.c | 12 +++- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/i

[PATCH v16 12/13] hw/pci: Use -1 as the default value for rombar

vfio_pci_size_rom() distinguishes whether rombar is explicitly set to 1 by checking dev->opts, bypassing the QOM property infrastructure. Use -1 as the default value for rombar to tell if the user explicitly set it to 1. The property is also converted from unsigned to signed. -1 is signed so it is

[PATCH v16 03/13] hw/ppc/spapr_pci: Do not reject VFs created after a PF

A PF may automatically create VFs and the PF may be function 0. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index f63182a03c41..ed4454bbf79e 100644 --- a/hw/ppc/spapr_pci.c +++

[PATCH v16 04/13] s390x/pci: Avoid creating zpci for VFs

VFs are automatically created by PF, and creating zpci for them will result in unexpected usage of fids. Currently QEMU does not support multifunction for s390x so we don't need zpci for VFs anyway. Signed-off-by: Akihiko Odaki --- hw/s390x/s390-pci-bus.c | 19 +-- 1 file changed

[PATCH v16 08/13] pcie_sriov: Reuse SR-IOV VF device instances

Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 8 ++-- in

[PATCH v16 07/13] pcie_sriov: Do not manually unrealize

A device gets automatically unrealized when being unparented. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 4 1 file changed, 4 deletions(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index e9b23221d713..499becd5273f 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_

[PATCH v16 05/13] s390x/pci: Allow plugging SR-IOV devices

The guest cannot use VFs due to the lack of multifunction support but can use PFs. Signed-off-by: Akihiko Odaki --- hw/s390x/s390-pci-bus.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 1a620f5b2a04..eab9a4f978

[PATCH v16 00/13] hw/pci: SR-IOV related fixes and improvements

Supersedes: <20240714-rombar-v2-0-af1504ef5...@daynix.com> ("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto") I submitted a RFC series[1] to add support for SR-IOV emulation to virtio-net-pci. During the development of the series, I fixed some trivial bugs and made improvements that I think

[PATCH v16 02/13] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

Disabled means it is a disabled SR-IOV VF or it is powered off, and hidden from the guest. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7cf9904c3546..f63182a03c41 100644 --- a/hw/ppc/spap

Re: [PATCH v2 12/17] migration/multifd: Device state transfer support - send side

On Thu, Sep 12, 2024 at 03:43:39PM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > Hi Peter, sorry if I'm not very enthusiastic by this, I'm sure you > understand the rework is a little frustrating. That's OK. [For some reason my email sync program decided to give up working for hours. I g

Re: [PATCH v1] virtio-mem: don't warn about THP sizes on a kernel without THP support

On 9/11/24 2:34 AM, David Hildenbrand wrote: If the config directory in sysfs does not exist at all, we are dealing with a system that does not support THPs. Simply use 1 MiB block size then, instead of warning "Could not detect THP size, falling back to ..." and falling back to the default THP s

[PATCH v14 09/20] target/riscv: Expose zicfilp extension as a cpu property

Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a0490e29f9..b4b578003f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1495,6 +1495,7 @@ const RISCVCPUM

[PATCH v14 18/20] disas/riscv: enable disassembly for zicfiss instructions

Enable disassembly for sspush, sspopchk, ssrdp & ssamoswap. Disasembly is only enabled if zimop and zicfiss ext is set to true. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 40 +++- disas/riscv.h | 1 + 2 files changed, 40 inser

[PATCH v14 17/20] target/riscv: compressed encodings for sspush and sspopchk

sspush/sspopchk have compressed encodings carved out of zcmops. compressed sspush is designated as c.mop.1 while compressed sspopchk is designated as c.mop.5. Note that c.sspush x1 exists while c.sspush x5 doesn't. Similarly c.sspopchk x5 exists while c.sspopchk x1 doesn't. Signed-off-by: Deepak

[PATCH v14 11/20] target/riscv: introduce ssp and enabling controls for zicfiss

zicfiss introduces a new state ssp ("shadow stack register") in cpu. ssp is expressed as a new unprivileged csr (CSR_SSP=0x11) and holds virtual address for shadow stack as programmed by software. Shadow stack (for each mode) is enabled via bit3 in *envcfg CSRs. Shadow stack can be enabled for a m

[PATCH v14 01/20] target/riscv: expose *envcfg csr and priv to qemu-user as well

Execution environment config CSR controlling user env and current privilege state shouldn't be limited to qemu-system only. *envcfg CSRs control enabling of features in next lesser mode. In some cases bits *envcfg CSR can be lit up by kernel as part of kernel policy or software (user app) can choos

[PATCH v14 07/20] target/riscv: zicfilp `lpad` impl and branch tracking

Implements setting lp expected when `jalr` is encountered and implements `lpad` instruction of zicfilp. `lpad` instruction is taken out of auipc x0, . This is an existing HINTNOP space. If `lpad` is target of an indirect branch, cpu checks for 20 bit value in x7 upper with 20 bit value embedded in

[PATCH v14 05/20] target/riscv: additional code information for sw check

sw check exception support was recently added. This patch further augments sw check exception by providing support for additional code which is provided in *tval. Adds `sw_check_code` field in cpuarchstate. Whenever sw check exception is raised *tval gets the value deposited in `sw_check_code`. Si

[PATCH v14 20/20] target/riscv: Expose zicfiss extension as a cpu property

Signed-off-by: Deepak Gupta Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4172774087..3e72df6ef8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1499,6 +1499,7 @@ const RISCVCPUM

[PATCH v14 13/20] target/riscv: mmu changes for zicfiss shadow stack protection

zicfiss protects shadow stack using new page table encodings PTE.W=1, PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not implemented or if shadow stack are not enabled. Loads on shadow stack memory are allowed while stores to shadow stack memory leads to access faults. Shadow stack ac

[PATCH v14 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp

zicfilp protects forward control flow (if enabled) by enforcing all indirect call and jmp must land on a landing pad instruction `lpad`. If target of an indirect call or jmp is not `lpad` then cpu/hart must raise a sw check exception with tval = 2. This patch implements the mechanism using TCG. Ta

[PATCH v14 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp

zicfilp introduces a new state elp ("expected landing pad") in cpu. During normal execution, elp is idle (NO_LP_EXPECTED) i.e not expecting landing pad. On an indirect call, elp moves LP_EXPECTED. When elp is LP_EXPECTED, only a subsquent landing pad instruction can set state back to NO_LP_EXPECTED

[PATCH v14 04/20] target/riscv: save and restore elp state on priv transitions

elp state is recorded in *status on trap entry (less privilege to higher privilege) and restored in elp from *status on trap exit (higher to less privilege). Additionally this patch introduces a forward cfi helper function to determine if current privilege has forward cfi is enabled or not based o

[PATCH v14 15/20] target/riscv: update `decode_save_opc` to store extra word2

Extra word 2 is stored during tcg compile and `decode_save_opc` needs additional argument in order to pass the value. This will be used during unwind to get extra information about instruction like how to massage exceptions. Updated all callsites as well. Resolves: https://gitlab.com/qemu-project/

[PATCH v14 19/20] disas/riscv: enable disassembly for compressed sspush/sspopchk

sspush and sspopchk have equivalent compressed encoding taken from zcmop. cmop.1 is sspush x1 while cmop.5 is sspopchk x5. Due to unusual encoding for both rs1 and rs2 from space bitfield, this required a new codec. Signed-off-by: Deepak Gupta Acked-by: Alistair Francis --- disas/riscv.c | 19 +

[PATCH v14 10/20] target/riscv: Add zicfiss extension

zicfiss [1] riscv cpu extension enables backward control flow integrity. This patch sets up space for zicfiss extension in cpuconfig. And imple- ments dependency on A, zicsr, zimop and zcmop extensions. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta Co-developed-by: Jim Sh

[PATCH v14 08/20] disas/riscv: enable `lpad` disassembly

Signed-off-by: Deepak Gupta Co-developed-by: Jim Shu Co-developed-by: Andy Chiu Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- disas/riscv.c | 18 +- disas/riscv.h | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/r

[PATCH v14 14/20] target/riscv: AMO operations always raise store/AMO fault

This patch adds one more word for tcg compile which can be obtained during unwind time to determine fault type for original operation (example AMO). Depending on that, fault can be promoted to store/AMO fault. Signed-off-by: Deepak Gupta Suggested-by: Richard Henderson Reviewed-by: Richard Hende

[PATCH v14 16/20] target/riscv: implement zicfiss instructions

zicfiss has following instructions - sspopchk: pops a value from shadow stack and compares with x1/x5. If they dont match, reports a sw check exception with tval = 3. - sspush: pushes value in x1/x5 on shadow stack - ssrdp: reads current shadow stack - ssamoswap: swaps contents of shadow sta

[PATCH v14 12/20] target/riscv: tb flag for shadow stack instructions

Shadow stack instructions can be decoded as zimop / zcmop or shadow stack instructions depending on whether shadow stack are enabled at current privilege. This requires a TB flag so that correct TB generation and correct TB lookup happens. `DisasContext` gets a field indicating whether bcfi is enab

[PATCH v14 00/20] riscv support for control flow integrity extensions

v14 for riscv zicfilp and zicfiss extensions support in qemu. v14 is rebased on https://github.com/alistair23/qemu/blob/riscv-to-apply.next zicfilp and zicfiss spec pdf https://github.com/riscv/riscv-cfi/releases/download/v1.0/riscv-cfi.pdf github sources to spec https://github.com/riscv/riscv-c

[PATCH v14 02/20] target/riscv: Add zicfilp extension

zicfilp [1] riscv cpu extension enables forward control flow integrity. If enabled, all indirect calls must land on a landing pad instruction. This patch sets up space for zicfilp extension in cpuconfig. zicfilp is dependend on zicsr. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepa

Re: [PATCH RFC 10/10] tests/migration-tests: Add test case for responsive CPU throttle

Fabiano Rosas writes: > Peter Xu writes: > >> On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote: >>> On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas wrote: >>> > I don't think we're discussing total CI time at this point, so the math >>> > doesn't really add up. We're not looking into

[PATCH v3 04/14] pnv/xive2: Support for "OS LGS Push" TIMA operation

From: Glenn Miles Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we j

[PATCH v3 01/14] pnv/xive: TIMA patch sets pre-req alignment and formatting changes

From: Michael Kowal Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets. Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'. There ar

[PATCH v3 03/14] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"

From: Frederic Barrat Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CA

[PATCH v3 11/14] pnv/xive: Add special handling for pool targets

From: Glenn Miles Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use some of the registers from the physical ring in the TIMA. Specifically, the NSR, PIPR and C

[PATCH v3 07/14] ppc/xive2: Allow 1-byte write of Target field in TIMA

From: Glenn Miles When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Sign

[PATCH v3 13/14] pnv/xive2: TIMA support for 8-byte OS context push for PHYP

From: Glenn Miles PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails

[PATCH v3 14/14] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths

Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to registeradded lwz@0x

[PATCH v3 08/14] ppc/xive2: Support "Pull Thread Context to Register" operation

From: Glenn Miles Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Re

[PATCH v3 05/14] ppc/xive2: Dump more NVP state with 'info pic'

From: Frederic Barrat The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group. Also, print the Reporting Cache Line address, if defined. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater --- include/hw/ppc/xive2_regs.

[PATCH v3 12/14] pnv/xive: Update PIPR when updating CPPR

From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Fixes:

[PATCH v3 09/14] ppc/xive2: Change context/ring specific functions to be generic

Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations. Signed-off-by: Michael Kowal --- include/hw/pp

[PATCH v3 10/14] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"

From: Glenn Miles Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREA

[PATCH v3 00/14] XIVE2 changes for TIMA operations

In XIVE Gen 2 there are many operations that were not modeled and are needed for PowerVM. These changes are associated with the following Thread Interrupt Management Area subjects: - OS context - Thread context - Pulling contexts to 'cache lines' - Pool targets - Enhaced trace data for XIVE G

[PATCH v3 02/14] pnv/xive2: Define OGEN field in the TIMA

From: Frederic Barrat The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater --- include/hw/ppc/xive_regs.h | 1 + hw/intc/xive.c | 4 2 files changed, 5 ins

[PATCH v3 06/14] ppc/xive2: Dump the VP-group and crowd tables with 'info pic'

From: Frederic Barrat The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater --- include/hw/ppc/xive2.h | 12 +++

Re: [PATCH v1 01/14] s390x/s390-virtio-ccw: don't crash on weird RAM sizes

On Tue, 2024-09-10 at 19:57 +0200, David Hildenbrand wrote: > KVM is not happy when starting a VM with weird RAM sizes: > > # qemu-system-s390x --enable-kvm --nographic -m 1234K > qemu-system-s390x: kvm_set_user_memory_region: KVM_SET_USER_MEMORY_REGION > failed, slot=0, start=0x0, size=0x

Re: [PATCH v2 12/17] migration/multifd: Device state transfer support - send side

Peter Xu writes: Hi Peter, sorry if I'm not very enthusiastic by this, I'm sure you understand the rework is a little frustrating. > On Wed, Aug 28, 2024 at 09:41:17PM -0300, Fabiano Rosas wrote: >> > +size_t multifd_device_state_payload_size(void) >> > +{ >> > +return sizeof(MultiFDDeviceSt

Re: [PATCH v2 47/48] tests/qtest: remove return after g_assert_not_reached()

On 9/12/24 09:11, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- tests/qtest/acpi-utils.c | 1 - 1 file changed, 1 deletion(-

Re: [PATCH v2 46/48] qom: remove return after g_assert_not_reached()

On 9/12/24 09:11, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- qom/object.c | 1 - 1 file changed, 1 deletion(-) diff --gi

Re: [PATCH v2 45/48] qobject: remove return after g_assert_not_reached()

On 9/12/24 09:11, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- qobject/qnum.c | 4 1 file changed, 4 deletions(-) Rev

Re: [PATCH v2 44/48] migration: remove return after g_assert_not_reached()

On 9/12/24 09:11, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- migration/dirtyrate.c| 1 - migration/postcopy-ram.c | 7

Re: [PATCH v2 01/48] docs/spin: replace assert(0) with g_assert_not_reached()

On 9/12/24 09:14, Paolo Bonzini wrote: On 9/12/24 09:38, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouv

Re: [PATCH v2 43/48] hw/ppc: remove return after g_assert_not_reached()

On 9/12/24 00:39, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- hw/ppc/ppc.c | 1 - hw/ppc/spapr_events.c | 1 - 2

Re: [PATCH v2 42/48] hw/pci: remove return after g_assert_not_reached()

On 9/12/24 00:39, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- hw/pci/pci-stub.c | 2 -- 1 file changed, 2 deletions(-) Re

Re: [PATCH v2 41/48] hw/net: remove return after g_assert_not_reached()

On 9/12/24 00:39, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- hw/net/e1000e_core.c | 2 -- hw/net/igb_core.c| 2 -- hw

Re: [PATCH v2 40/48] hw/hyperv: remove return after g_assert_not_reached()

On 9/12/24 00:39, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- hw/hyperv/hyperv_testdev.c | 1 - hw/hyperv/vmbus.c

Re: [PATCH v2 39/48] include/qemu: remove return after g_assert_not_reached()

On 9/12/24 00:39, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- include/qemu/pmem.h | 1 - 1 file changed, 1 deletion(-) Re

Re: [PATCH] ppc/pnv: Add support for TPM with SPI interface

On 9/12/24 12:09 PM, dan tan wrote: From: dan tan SPI interface to TPM TIS implementation via swtpm Apart from Cedric's comments: Can you say a bit more about the specs you followed and details how many localities are supported etc. Is this device pnv-specific or can it be used on other

Re: [PATCH] ppc/pnv: Add support for TPM with SPI interface

Hello Dan, On 9/12/24 18:09, dan tan wrote: From: dan tan SPI interface to TPM TIS implementation via swtpm I would split this patch in 3 : 1. device model 2. activation for the PowerNV machines 3. unit tests Each with a slightly more detailed commit log please. one line is very minimal fo

Re: [RFC RESEND 0/6] hugetlbfs largepage RAS project

On 9/12/24 00:07, David Hildenbrand wrote: Hi again, This is a Qemu RFC to introduce the possibility to deal with hardware memory errors impacting hugetlbfs memory backed VMs. When using hugetlbfs large pages, any large page location being impacted by an HW memory error results in poisoning th

Re: [PATCH-for-9.1 v2 0/4] hw/ssi/pnv_spi: Fixes Coverity CID 1558831

Chalapthi, On 8/7/24 22:28, Philippe Mathieu-Daudé wrote: v2: - Cover PowerNV SSI in MAINTAINERS - Use GLib API in pnv_spi_xfer_buffer_free() - Simplify returning early Supersedes: <20240806134829.351703-3-chalapath...@linux.ibm.com> I was wondering where we were on this series. I see there w

[PATCH v2 1/2] net: parameterize the removing client from nc list

This change is used in later commits so we can avoid the removal of the netclient if it is delayed. No functional change intended. Reviewed-by: Si-Wei Liu Acked-by: Jason Wang Signed-off-by: Eugenio Pérez --- net/net.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff

[PATCH v2 0/2] Move net backend cleanup to NIC cleanup

Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net structures if peer nic is present") effectively delayed the backend cleanup, allowing the frontend or the guest to access it resources as long as the frontend NIC is still visible to the guest. However it does not clean up the resou

[PATCH v2 2/2] net: move backend cleanup to NIC cleanup

Commit a0d7215e33 ("vhost-vdpa: do not cleanup the vdpa/vhost-net structures if peer nic is present") effectively delayed the backend cleanup, allowing the frontend or the guest to access it resources as long as the frontend is still visible to the guest. However it does not clean up the resources

Re: [PATCH v2] .gitlab-ci.d/crossbuilds.yml: Force 'make check' single-threaded for cross-i686-tci

On 12/09/2024 17.10, Peter Maydell wrote: The cross-i686-tci CI job is persistently flaky with various tests hitting timeouts. One theory for why this is happening is that we're running too many tests in parallel and so sometimes a test gets starved of CPU and isn't able to complete within the t

Re: [PATCH 3/3] vhost_user.rst: Add GET_SHMEM_CONFIG message

Albert Esteve writes: > Add GET_SHMEM_CONFIG vhost-user frontend > message to the spec documentation. > > Signed-off-by: Albert Esteve > --- > docs/interop/vhost-user.rst | 39 + > 1 file changed, 39 insertions(+) Reviewed-by: Alyssa Ross signature.asc De

Re: [PATCH v2 09/14] ppc/xive2: Change context/ring specific functions to be generic

On 9/12/2024 1:27 AM, Cédric Le Goater wrote: On 9/9/24 23:10, Michael Kowal wrote: Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This  will simplify the next patch sets that are addi

Re: [PATCH v2 01/48] docs/spin: replace assert(0) with g_assert_not_reached()

On 9/12/24 09:38, Pierrick Bouvier wrote: This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier This is not C code, so please dro

[PATCH v2 44/48] migration: remove return after g_assert_not_reached()

This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- migration/dirtyrate.c| 1 - migration/postcopy-ram.c | 7 --- migration/ram.c | 2 -- 3 f

[PATCH v2 47/48] tests/qtest: remove return after g_assert_not_reached()

This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- tests/qtest/acpi-utils.c | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/qtest/acpi-utils.c b/tes

[PATCH v2 46/48] qom: remove return after g_assert_not_reached()

This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- qom/object.c | 1 - 1 file changed, 1 deletion(-) diff --git a/qom/object.c b/qom/object.c index 157a45c5

[PATCH v2 48/48] scripts/checkpatch.pl: emit error when using assert(false)

This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- scripts/checkpatch.pl | 3 +++ 1 file changed, 3 insertions(+) diff --git

[PATCH v2 45/48] qobject: remove return after g_assert_not_reached()

This patch is part of a series that moves towards a consistent use of g_assert_not_reached() rather than an ad hoc mix of different assertion mechanisms. Signed-off-by: Pierrick Bouvier --- qobject/qnum.c | 4 1 file changed, 4 deletions(-) diff --git a/qobject/qnum.c b/qobject/qnum.c inde

[PATCH] ppc/pnv: Add support for TPM with SPI interface

From: dan tan SPI interface to TPM TIS implementation via swtpm Signed-off-by: dan tan --- include/sysemu/tpm.h | 3 + hw/tpm/tpm_tis_spi.c | 347 + tests/qtest/pnv-tpm-tis-spi-test.c | 223 ++ hw/ppc/Kconfig

Re: [PATCH RFC 10/10] tests/migration-tests: Add test case for responsive CPU throttle

Peter Xu writes: > On Thu, Sep 12, 2024 at 09:13:16AM +0100, Peter Maydell wrote: >> On Wed, 11 Sept 2024 at 22:26, Fabiano Rosas wrote: >> > I don't think we're discussing total CI time at this point, so the math >> > doesn't really add up. We're not looking into making the CI finish >> > faste

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