repository at:
https://github.com/philmd/qemu.git tags/hw-misc-20240911
for you to fetch changes up to d6bda15a00b46778e577c95c77f066f95ed58e07:
ui: remove break after g_assert_not_reached() (2024-09-11 13:54:06 +0200)
Mi
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
assert(0);
| }
| ^
Solve tha
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
g_assert_not_reached();
break
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
assert(0);
| }
| ^
Solve tha
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
g_assert_not_reached();
break
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
assert(0);
| }
| ^
Solve tha
Per datasheet, "ONE-SHOT (OS)", the OS bit always returns 0 when reading
the configuration register.
Clear the ONE_SHOT bit in the WRITE path. Now than the READ path is
simpler, we can also simplify tmp105_alarm_update().
Signed-off-by: Guenter Roeck
Signed-off-by: Philippe Mathieu-Daudé
Review
From: Guenter Roeck
Coding style asks for no space between variable and "++". The next patch
in this series will change one of those assignments. Instead of changing
just one with that patch, change all of them for consistency.
While at it, also fix other coding style problems reported by checkp
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
assert(0);
| }
| ^
Solve tha
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
g_assert_not_reached();
break
From: Pierrick Bouvier
Use of assert(false) can trip spurious control flow warnings from
some versions of GCC (i.e. using -fsanitize=thread with gcc-12):
error: control reaches end of non-void function [-Werror=return-type]
default:
g_assert_not_reached();
break
From: Guenter Roeck
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit
of the limit registers are unused and always report 0.
The lower 4 bit should not be used for temperature comparisons,
so mask the unused bits before storing the limits.
Signed-off-by: Guenter Roeck
Reviewed-by:
The next commit will clear the ONE_SHOT bit in the WRITE
path (to keep the READ path trivial). As a preliminary step,
pass the 'oneshot' value as argument to tmp105_alarm_update().
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
Message-Id: <202409061
To improve readability, use the registerfields API.
Define the register bits with FIELD(), and use the
FIELD_EX8() and FIELD_DP8() macros. Remove the
abbreviations in comments.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Guenter Roeck
Message-Id: <20240906154911.86803-3-phi...@linaro.org>
v2:
- Fill Pierrick's commit description suggested by Eric Blake
- Include TMP105 fixes from Guenter
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
Merge tag 'pull-testing-gdbstub-oct-100924-1' of
https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +
Currently starting a pSeries machine, with lesser than 128MiB shows
below error:
qemu-system-ppc64: pSeries SLOF firmware requires >= 80ldMiB guest RMA
(Real Mode Area memory)
Above '80ldMib' is in hex, and it means 0x80 MiB = 128 MiB.
Change format specifier for this value to use 'HWADDR_P
On 6/9/24 17:49, Philippe Mathieu-Daudé wrote:
Respin of Guenter fixes with:
- Use registerfields API
- Clear OS bit in WRITE path
Supersedes: <20240906132912.3826089-1-li...@roeck-us.net>
Guenter Roeck (2):
hw/sensor/tmp105: Coding style fixes
hw/sensor/tmp105: Lower 4 bit of limit regis
On 2024/09/12 6:11, Matthew Rosato wrote:
On 9/11/24 11:15 AM, Akihiko Odaki wrote:
On 2024/09/11 22:53, Matthew Rosato wrote:
On 9/11/24 6:58 AM, Akihiko Odaki wrote:
On 2024/09/11 18:38, Cédric Le Goater wrote:
+Matthew +Eric
Side note for the maintainers :
Before this change, the igb dev
Hi Cédric,
Thank you very much for the quick response!
I have checked the error API again. It seems to be my porting issue of
set_iommu_device() callback.
I think "pci_device_set_iommu_device(..., *errp)" should set 'errp' if
this function returns false, right?
Thanks,
Jim
On Thu, Sep 12, 2024
On 9/9/24 23:10, Michael Kowal wrote:
Some the functions that have been created are specific to a ring or context.
Some
of these same functions are being changed to operate on any ring/context. This
will
simplify the next patch sets that are adding additional ring/context operations.
Signed-o
On 9/9/24 23:10, Michael Kowal wrote:
From: Glenn Miles
Adds support for single byte writes to offset 0xC38 of the TIMA address
space. When this offset is written to, the hardware disables the thread
context and copies the current state information to the odd cache line of
the pair specified b
Refactor setting up of dirty ring code in kvm_init() so that is can be
reused in the future patchsets.
Signed-off-by: Ani Sinha
---
accel/kvm/kvm-all.c | 88 +
1 file changed, 50 insertions(+), 38 deletions(-)
diff --git a/accel/kvm/kvm-all.c b/accel/
Hello Jim,
On 9/12/24 07:17, Jim Shu wrote:
pci_dev_realize() use the local error variable, which requires
`error_setg()` API to allocate the error object at first.
Signed-off-by: Jim Shu
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c b/h
On 11/9/24 18:50, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 31 ---
2 files changed, 29 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
From: Alvin Chang
According to RISC-V Debug specification, the optional textra32 and
textra64 trigger CSRs can be used to configure additional matching
conditions for the triggers. For example, if the textra.MHSELECT field
is set to 4 (mcontext), this trigger will only match or fire if the low
bi
From: Alvin Chang
This commit allows program to write textra trigger CSR for type 2, 3, 6
triggers. In this preliminary patch, the textra.MHVALUE and the
textra.MHSELECT fields are allowed to be configured. Other fields, such
as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired t
Hi Michael,
On 9/11/2024 1:44 AM, Michael S. Tsirkin wrote:
> On Wed, Sep 04, 2024 at 05:02:52AM -0500, Santosh Shukla wrote:
>> Series adds following feature support for emulated amd vIOMMU
>> 1) Pass Through(PT) mode
>> 2) Interrupt Remapping(IR) mode
>>
>> 1) PT mode
>> Introducing the shared '
From: Daniel Henrique Barboza
Add an additional test to further exercise the IOMMU where we attempt to
initialize the command, fault and page-request queues.
These steps are taken from chapter 6.2 of the RISC-V IOMMU spec,
"Guidelines for initialization". It emulates what we expect from the
soft
Model fp_exception state, in which only fp stores are allowed
until such time as the FQ has been flushed.
Signed-off-by: Richard Henderson
Acked-by: Mark Cave-Ayland
Tested-by: Carl Hauser
---
target/sparc/translate.c | 90 +++-
1 file changed, 61 insertions
From: Tomasz Jeznach
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Daniel Henrique Barboza
The RISC-V IOMMU PCI device we're going to add next is a reference
implementation of the riscv-iommu spec [1], which predicts that the
IOMMU can be implemented as a PCIe device.
However, RISC-V International (RVI), the entity that ratified the
riscv-iommu spec, didn
From: Carl Hauser
Add support for, and migrate, a single-entry fp
instruction queue for sparc32.
Signed-off-by: Carl Hauser
[rth: Split from a larger patch;
adjust representation with union;
add migration state]
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1908-4-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
b
From: Tomasz Jeznach
Add PCIe Address Translation Services (ATS) capabilities to the IOMMU.
This will add support for ATS translation requests in Fault/Event
queues, Page-request queue and IOATC invalidations.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Fr
From: Thomas Huth
If QEMU has been configured with "--without-default-devices", the build
is currently failing with:
/usr/bin/ld: libqemu-riscv32-softmmu.a.p/target_riscv_cpu_helper.c.o:
in function `riscv_cpu_do_interrupt':
.../qemu/target/riscv/cpu_helper.c:1678:(.text+0x2214): undefined
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Carl Hauser
Implement a single instruction floating point queue,
populated while delivering an fp exception.
Signed-off-by: Carl Hauser
[rth: Split from a larger patch]
Signed-off-by: Richard Henderson
Acked-by: Mark Cave-Ayland
Tested-by: Carl Hauser
---
target/sparc/int32_helper.c |
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1908-18-itac...@freebsd.org>
Signed-off-by: Alistair Francis
---
configs/targets/riscv64-bsd-u
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Daniel Henrique Barboza
To test the RISC-V IOMMU emulation we'll use its PCI representation.
Create a new 'riscv-iommu-pci' libqos device that will be present with
CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
device will only be consumed by the RISC-V libqos machin
From: Andrew Jones
C doesn't extend the sign bit for unsigned types since there isn't a
sign bit to extend. This means a promotion of a u32 to a u64 results
in the upper 32 bits of the u64 being zero. If that result is then
used as a mask on another u64 the upper 32 bits will be cleared. rv32
phy
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1908-14-itac.
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Jason Chien
RVV spec allows implementations to set vl with values within
[ceil(AVL/2),VLMAX] when VLMAX < AVL < 2*VLMAX. This commit adds a
property "rvv_vl_half_avl" to enable setting vl = ceil(AVL/2). This
behavior helps identify compiler issues and bugs.
Signed-off-by: Jason Chien
Revi
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Tomasz Jeznach
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
Reviewed-by: Frank Chang
Revie
From: Andrew Jones
Just as the hart bit setting of the AIA should be calculated as
ceil(log2(max_hart_id + 1)) the group bit setting should be
calculated as ceil(log2(max_group_id + 1)). The hart bits are
implemented by passing max_hart_id to find_last_bit() and adding
one to the result. Do the s
From: Alexandre Ghiti
The Svvptc extension describes a uarch that does not cache invalid TLB
entries: that's the case for qemu so there is nothing particular to
implement other than the introduction of this extension.
Since qemu already exposes Svvptc behaviour, let's enable it by default
since
Hi!
While looking at some recent CI jobs, I noticed that the caching of the
Gitlab-CI jobs is not working at all anymore. In the build jobs, the ccache
saving is not working and causing a complete cache miss of each compile:
https://gitlab.com/qemu-project/qemu/-/jobs/7802183187#L5328
An
From: Tomasz Jeznach
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Acked-by: Mark Cave-Ayland
Tested-by: Carl Hauser
---
target/sparc/cpu.h | 8 +++-
target/sparc/translate.c | 10 +++---
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/sparc/cpu.h b/targ
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Tomasz Jeznach
This header will be used by the RISC-V IOMMU emulation to be added
in the next patch. Due to its size it's being sent in separate for
an easier review.
One thing to notice is that this header can be replaced by the future
Linux RISC-V IOMMU driver header, which would become
From: Daniel Henrique Barboza
Add a simple guideline to use the existing RISC-V IOMMU support we just
added.
This doc will be updated once we add the riscv-iommu-sys device.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240903201633.93182-13-dbarb...@vent
From: Andrew Jones
While the spec doesn't state it, setting timecmp to UINT64_MAX is
another way to stop a timer, as it's considered setting the next
timer event to occur at infinity. And, even if the time CSR does
eventually reach UINT64_MAX, the very next tick will bring it back to
zero, once a
From: Maria Klauchek
FCSR is a part of F extension. Print it to log if FPU option is enabled.
Signed-off-by: Maria Klauchek
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Message-ID: <20240902103433.18424-1-m.klauc...@syntacore.com>
Signed-off-by: Alistair Francis
---
ta
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Milan P. Stanić
build fails on musl libc (alpine linux) with this error:
../util/cpuinfo-riscv.c: In function 'cpuinfo_init':
../util/cpuinfo-riscv.c:63:21: error: '__NR_riscv_hwprobe' undeclared (first
use in this function); did you mean 'riscv_hwprobe'?
63 | if (syscall(__NR_
From: Tomasz Jeznach
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair F
From: Vladimir Isaev
za64rs requires priv 1.12 when enabled by priv 1.11.
This fixes annoying warning:
warning: disabling za64rs extension for hart 0x because privilege spec
version does not match
on priv 1.11 CPUs.
Fixes: 68c9e54beae8 ("target/riscv: do not enable all named features
From: Tomasz Jeznach
The RISC-V IOMMU specification is now ratified as-per the RISC-V
international process. The latest frozen specifcation can be found at:
https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
Add the foundation of the device emulation for RISC-V
From: Daniel Henrique Barboza
Gitlab issue [1] reports a misleading error when trying to run a 'rv64'
cpu with 'zfinx' and without 'f':
$ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false
qemu-system-riscv64: Zfinx cannot be supported together with F extension
The user
From: Samuel Holland
When riscv_load_firmware() loads an ELF, the ELF segment addresses are
used, not the passed-in firmware_load_addr. The machine models assume
the firmware entry point is what they provided for firmware_load_addr,
and use that address to generate the boot ROM, so if the ELF is
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
Message-ID: <20240907031927.1908-8-itac...@freebsd.org>
Signed-off-by: Alistai
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
Invalid encoding of addr should raise TT_ILL_INSN, so
check before supervisor, which might raise TT_PRIV_INSN.
Clear QNE after execution.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2340
Signed-off-by: Richard Henderson
Acked-by: Mark Cave-Ayland
Tested-by: Carl Hauser
---
target/s
From: Haibo Xu
As per process documented (steps 1-3) in bios-tables-test.c, add
empty AML data file for RISC-V ACPI SRAT table and add the entry
in bios-tables-test-allowed-diff.h.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
<0e30216273f2f59916bc6513
From: Alistair Francis
The OpenTitan Ibex CPU now supports the the Zba, Zbb, Zbc
and Zbs bit-manipulation sub-extensions ratified in
v.1.0.0 of the RISC-V Bit- Manipulation ISA Extension, so let's enable
them in QEMU as well.
1: https://github.com/lowRISC/opentitan/pull/9748
Signed-off-by: Alis
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
pull-sparc-20240911
for you to fetch changes up to d2a0c3a7f7740a3d563c8c3ef1fffcc87a36213d:
target/sparc: Add gen_trap_if_nofpu_fpexception (2024-09-11 19:54:55 -0700)
target/sparc: Implement single entr
The following changes since commit a4eb31c678400472de0b4915b9154a7c20d8332f:
Merge tag 'pull-testing-gdbstub-oct-100924-1' of
https://gitlab.com/stsquad/qemu into staging (2024-09-11 13:17:29 +0100)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-ris
From: Tomasz Jeznach
The RISC-V IOMMU spec predicts that the IOMMU can use translation caches
to hold entries from the DDT. This includes implementation for all cache
commands that are marked as 'not implemented'.
There are some artifacts included in the cache that predicts s-stage and
g-stage e
From: Haibo Xu
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI SRAT AML data file for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff
From: Tomasz Jeznach
Generate device tree entry for riscv-iommu PCI device, along with
mapping all PCI device identifiers to the single IOMMU device instance.
Signed-off-by: Tomasz Jeznach
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Frank Chang
Reviewed-by: Alistair Francis
Message-I
From: Haibo Xu
Add ACPI SRAT table test case for RISC-V when NUMA was enabled.
Signed-off-by: Haibo Xu
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
Message-ID:
Signed-off-by: Alistair Francis
---
tests/qtest/bios-tables-test.c | 28
1 file changed, 28 ins
pci_dev_realize() use the local error variable, which requires
`error_setg()` API to allocate the error object at first.
Signed-off-by: Jim Shu
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 0a99e55247..d994ad8bb9 100644
On 2024/9/10 下午8:18, Xianglai Li wrote:
Added extioi interrupt controller for kvm emulation.
The main process is to send the command word for
creating an extioi device to the kernel.
When the VM is saved, the ioctl obtains the related
data of the extioi interrupt controller in the kernel
and s
Instead of cmp+and or cmp+andc, use cmpsel. This will
be better for hosts that use predicate registers for cmp.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/gengvec.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/targ
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 223 ++---
target/arm/tcg/a64.decode | 36 +-
2 files changed, 128 insertions(+), 131 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 12
target/arm/tcg/translate.h | 7 ++
target/arm/tcg/gengvec.c| 36 +++
target/arm/tcg/neon_helper.c| 33 ++
target/arm/tcg/translate-neon.c | 110 +--
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 121 +
target/arm/tcg/a64.decode | 5 ++
2 files changed, 53 insertions(+), 73 deletions(-)
diff --git a/target/arm/tcg/tr
This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR,
SRSRA, URSRA, SRI.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 140 -
target/arm/tcg/a64.decode | 16
2 files changed, 86 insertions(+), 70 deletio
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 117 ++---
target/arm/tcg/a64.decode | 9 +++
2 files changed, 59 insertions(+), 67 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/trans
The extract2 tcg op performs the same operation
as the do_ext64 function.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 23 +++
1 file changed, 3 insertions(+), 20 deletions(-)
diff --gi
Instead of cmp+and or cmp+andc, use cmpsel. This will
be better for hosts that use predicate registers for cmp.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/gengvec.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/arm/tcg/ge
This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 86 +++---
target/arm/tcg/a64.decode | 63 -
2 files changed, 89 inser
Use simple shift and add instead of ctpop, ctz, shift and mask.
Unlike SVE, there is no predicate to disable elements.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 40 +++---
1 file changed, 13 insertions(+), 27 del
Handle the two special cases within these new
functions instead of higher in the call stack.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 5 +
target/arm/tcg/gengvec.c| 19 +++
target/arm/tcg/translate-a64.c | 16
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 176 ++---
target/arm/tcg/a64.decode | 14 +++
2 files changed, 67 insertions(+), 123 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran
We always pass the same value for round; compute it
within common code.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 32 ++--
1 file changed, 6 insertions(+), 26 deletions(-)
di
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 160 +++--
target/arm/tcg/a64.decode | 30 +++
2 files changed, 63 insertions(+), 127 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/
This includes SHL and SLI.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 44 +++---
target/arm/tcg/a64.decode | 4
2 files changed, 13 insertions(+), 35 deletions(-)
diff --git a/target/arm/tcg/translate-
> -Original Message-
> From: Michael S. Tsirkin
> Sent: Tuesday, September 10, 2024 11:17 PM
> To: Yao, Xingtao/姚 幸涛
> Cc: marcel.apfelb...@gmail.com; qemu-devel@nongnu.org
> Subject: Re: [PATCH v4] pci-bridge: avoid linking a single downstream port
> more
> than once
>
> On Thu, Jul
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 47 ++
target/arm/tcg/a64.decode | 4 +++
2 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/target/arm/tcg/tr
This includes SHL and SLI.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 33 +++--
target/arm/tcg/a64.decode | 15 +++
2 files changed, 18 insertions(+), 30 deletions(-)
diff --git a/target/arm/tcg/
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