07.09.2024 02:59, Kenneth Adam Miller wrote:
Hello,
I'm on commit bd80b59 and my host is:
$ git desc bd80b59
v2.4.0-rc3-9-gbd80b5963f
Date: Mon Aug 3 11:44:07 2015 +0100
FWIW :)
/mjt
Hi Yao,
On 22/7/24 09:40, Xingtao Yao (Fujitsu) wrote:
Please add to scripts/coccinelle/range.cocci.
OK, I will add this file in next revision.
Please Cc me on v3 (I'm dropping v2 from my queue).
Thanks,
Phil.
On 20/8/24 11:51, CLEMENT MATHIEU--DRIF wrote:
Signed-off-by: Clément Mathieu--Drif
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
Patch queued, thanks.
On 1/9/24 15:01, Volker Rümelin wrote:
Currently, the guest may write to the device configuration space,
whereas the virtio sound device specification in chapter 5.14.4
clearly states that the fields in the device configuration space
are driver-read-only.
Remove the set_config function from the
Hi Peter,
On 19/7/24 20:10, Philippe Mathieu-Daudé wrote:
Philippe Mathieu-Daudé (16):
hw/char/pl011: Remove unused 'readbuff' field
hw/char/pl011: Move pl011_put_fifo() earlier
hw/char/pl011: Move pl011_loopback_enabled|tx() around
hw/char/pl011: Split RX/TX path of pl011_reset_
Hi Mark,
On 4/9/24 12:40, Mark Cave-Ayland wrote:
Update the ADB mouse implementation to use QemuInputHandler instead of the
legacy qemu_add_mouse_event_handler() function.
Signed-off-by: Mark Cave-Ayland
---
hw/input/adb-mouse.c | 56
1 file cha
On 6/9/24 23:11, Mark Cave-Ayland wrote:
Philippe Mathieu-Daudé (3):
tests/unit: Strengthen FIFO8 tests
tests/unit: Expand test_fifo8_peek_buf_wrap() coverage
tests/unit: Comment FIFO8 tests
tests/unit/test-fifo.c | 209 +++--
1 file changed, 201
On 6/9/24 22:55, Mark Cave-Ayland wrote:
On 04/09/2024 12:19, Mark Cave-Ayland wrote:
On 04/09/2024 11:53, Philippe Mathieu-Daudé wrote:
On 4/9/24 12:23, Mark Cave-Ayland wrote:
Update the Sun mouse implementation to use QemuInputHandler instead
of the
legacy qemu_add_mouse_event_handler()
On 6/9/24 22:51, Mark Cave-Ayland wrote:
On 06/09/2024 14:14, Philippe Mathieu-Daudé wrote:
Hi Mark,
I'm OK to queue it but took some notes while reviewing:
https://lore.kernel.org/qemu-devel/20240906131217.78159-1-phi...@linaro.org/
If you can have a look, I'll queue both together.
Thanks
On 6/9/24 20:05, Thomas Huth wrote:
Copy the LinuxKernelTest from tests/acceptance/boot_linux_console.py
to be able to convert the related tests to the functional test framework
in the following patches.
Signed-off-by: Thomas Huth
---
tests/functional/qemu_test/__init__.py| 1 +
tests/f
On 6/9/24 20:05, Thomas Huth wrote:
We've got to do_test_advcal_2018() here now that the test resides
in a separate file. Also switch back to the original URL (since
the site did not vanish as originally expected) and update the
hashsum to use SHA256.
Signed-off-by: Thomas Huth
---
tests/avoc
On 6/9/24 20:05, Thomas Huth wrote:
Just had to update the asset checksum to use SHA256 instead of SHA1,
but apart from that it is a pretty much straightforward conversion.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
tests/avocado/boot_linux_console.py | 24 ---
On 6/9/24 20:05, Thomas Huth wrote:
We've got to do_test_advcal_2018() here now that the test resides
in a separate file. Also switch back to the original URL (since
the site did not vanish as originally expected) and update the
hashsum to use SHA256.
Signed-off-by: Thomas Huth
---
tests/avoc
On 6/9/24 20:05, Thomas Huth wrote:
Straight forward conversion, just switch to SHA256 hashsum now.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py| 21 --
tests/functional/meson.build | 4 +++
tests/functional/test_alpha_clipper.py | 38 +++
On 6/9/24 17:49, Philippe Mathieu-Daudé wrote:
From: Guenter Roeck
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit
of the limit registers are unused and always report 0.
The lower 4 bit should not be used for temperature comparisons,
so mask the unused bits before storing the lim
On 6/9/24 17:49, Philippe Mathieu-Daudé wrote:
From: Guenter Roeck
Coding style asks for no space between variable and "++". The next patch
in this series will change one of those assignments. Instead of changing
just one with that patch, change all of them for consistency.
While at it, also f
On 7/9/24 01:01, Mark Cave-Ayland wrote:
Commit e104edbb9d ("hw/mips/jazz: use qemu_find_nic_info()") contained a typo
in the NIC alias which caused initialisation of the in-built dp83932 NIC to fail
when using the normal -nic user,model=dp83932 command line.
Cc: qemu-sta...@nongnu.org # v9.0
Hi Jason,
It works well with ELF kernel, however it fails to boot with UEFI BIOS.
Maybe it is problem of UEFI BIOS, can we create UART in reverse order?
so that it can work well on both ELF kernel and UEFI BIOS.
Also for develops they usually use as earlycon with command line
-serial stdio -
From: Mark Corbin
Added implementations for 'set_mcontext' and 'get_ucontext_sigreturn'
functions for RISC-V architecture,
Both functions ensure that the CPU state and user context are properly
managed.
Signed-off-by: Mark Corbin
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Co-author
From: Mark Corbin
Implemented functions for setting up and initializing threads in the
RISC-V architecture.
The 'target_thread_set_upcall' function sets up the stack pointer,
program counter, and function argument for new threads.
The 'target_thread_init' function initializes thread registers bas
From: Mark Corbin
Added definitions for RISC-V signal handling, including structures
and constants for managing signal frames and context
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by: Warner Losh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_signal.h
From: Warner Losh
Added a generic definition for RISC-V64 target-specific details.
Implemented the 'regpairs_aligned' function,which returns 'false'
to indicate that register pairs are not aligned in the RISC-V64 ABI.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard H
Key Changes Compared to Version 4:
Minor formatting changes
Mark Corbin (15):
bsd-user: Implement RISC-V CPU initialization and main loop
bsd-user: Add RISC-V CPU execution loop and syscall handling
bsd-user: Implement RISC-V CPU register cloning and reset functions
bsd-user: Implement RIS
From: Mark Corbin
Added the 'get_mcontext' function to extract and populate
the RISC-V machine context from the CPU state.
This function is used to gather the current state of the
general-purpose registers and store it in a 'target_mcontext_'
structure.
Signed-off-by: Mark Corbin
Signed-off-by:
From: Mark Corbin
Added functions for setting up the RISC-V signal trampoline and signal
frame:
'set_sigtramp_args()': Configures the RISC-V CPU state with arguments
for the signal handler. It sets up the registers with the signal
number,pointers to the signal info and user context, the signal h
From: Warner Losh
Added configuration for RISC-V 64-bit target to the build system.
Signed-off-by: Warner Losh
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
configs/targets/riscv64-bsd-user.mak | 4
1 file changed, 4 insertions(+)
create mode 100644 configs/targets/risc
From: Mark Corbin
Added the 'do_freebsd_arch_sysarch' function to emulate the 'sysarch'
system call for the RISC-V architecture.
Currently, this function returns '-TARGET_EOPNOTSUPP' to indicate that
the operation is not supported.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed
From: Mark Corbin
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-authored-by
From: Mark Corbin
Added definitions for RISC-V VM parameters, including maximum and
default sizes for text, data, and stack, as well as address space
limits.
Implemented helper functions for retrieving and setting specific
values in the CPU state, such as stack pointer and return values.
Signed-
From: Mark Corbin
Added functions for cloning CPU registers and resetting the CPU state
for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_cpu.h | 14 ++
1 file changed, 14 insertions(+)
di
From: Mark Corbin
Introduced RISC-V specific ELF definitions and hardware capability
detection.
Additionally, a function to retrieve hardware capabilities
('get_elf_hwcap') is implemented, which returns the common bits set in
each CPU's ISA strings.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
From: Mark Corbin
Implemented the 'setup_sigtramp' function for setting up the signal
trampoline code in the RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richard Henderson
---
bsd-user/riscv/target_arch_sigtramp.h | 42 +++
1
From: Mark Corbin
Introduced definitions for the RISC-V system call interface, including
the 'target_pt_regs' structure that outlines the register storage
layout during a system call.
Added constants for hardware machine identifiers.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Co-aut
From: Mark Corbin
Added definitions for RISC-V register structures, including
general-purpose registers and floating-point registers, in
'target_arch_reg.h'. Implemented the 'target_copy_regs' function to
copy register values from the CPU state to the target register
structure, ensuring proper en
From: Mark Corbin
Included the prototype for the 'target_cpu_set_tls' function in the
'target_arch.h' header file. This function is responsible for setting
the Thread Local Storage (TLS) register for RISC-V architecture.
Signed-off-by: Mark Corbin
Signed-off-by: Ajeet Singh
Reviewed-by: Richar
From: Mark Corbin
Implemented the RISC-V CPU execution loop, including handling various
exceptions and system calls. The loop continuously executes CPU
instructions,processes exceptions, and handles system calls by invoking
FreeBSD syscall handlers.
Signed-off-by: Mark Corbin
Signed-off-by: Aje
On Sat, Sep 07, 2024 at 09:47:38AM +0800, Huacai Chen wrote:
> On Sat, Sep 7, 2024 at 9:44 AM maobibo wrote:
> >
> > Add huacai who is maintainer of Loongarch Linux kernel.
> >
> > On 2024/9/6 下午10:55, Jason A. Donenfeld wrote:
> > > Hi,
> > >
> > > It appears that as of QEMU 9.1, it's possible to
With newer clang builds (19.x), there's a warning for implicit function
declarations and it rejects linux-test.c.
glibc/musl's readdir64() declaration in dirent is guarded by
_LARGEFILE64_SOURCE, so we'll define it to fix the warning.
BUILD hexagon-linux-user guest-tests
/local/mnt/w
On 9/5/24 08:21, Alex Bennée wrote:
Pierrick Bouvier writes:
This series allows plugins to know which value is read/written during a memory
access.
For every memory access, we know copy this value before calling mem callbacks,
and those can query it using new API function:
- qemu_plugin_mem_g
On Sat, Sep 7, 2024 at 9:44 AM maobibo wrote:
>
> Add huacai who is maintainer of Loongarch Linux kernel.
>
> On 2024/9/6 下午10:55, Jason A. Donenfeld wrote:
> > Hi,
> >
> > It appears that as of QEMU 9.1, it's possible to boot LoongArch machines
> > that don't provide EFI or ACPI.
> >
> > Would yo
Add huacai who is maintainer of Loongarch Linux kernel.
On 2024/9/6 下午10:55, Jason A. Donenfeld wrote:
Hi,
It appears that as of QEMU 9.1, it's possible to boot LoongArch machines
that don't provide EFI or ACPI.
Would you consider removing the `select ACPI` and `select EFI` from the
arch Kconf
Hello,
I'm on commit bd80b59 and my host is:
$lsb_release -s
...
Description: Pop!_OS 20.04 LTS
Release: 20.04In file included from
...
I get a compile error:
...
/home/kennethadammiller/workspace/vm_escape/qemu/include/hw/xen/xen_backend.h:4,
from
/home/kennethadammiller/worksp
Commit e104edbb9d ("hw/mips/jazz: use qemu_find_nic_info()") contained a typo
in the NIC alias which caused initialisation of the in-built dp83932 NIC to fail
when using the normal -nic user,model=dp83932 command line.
Signed-off-by: Mark Cave-Ayland
---
hw/mips/jazz.c | 2 +-
1 file changed, 1
In the context of using the remote gdb with multiple
processes/inferiors (multiple cluster machine) a given breakpoint
will target an specific inferior. If needed the remote protocol will
use the packet 'H op thread-id' with op = 'g' to change focus to the
inferior we want to insert/remove the brea
In the context of using the remote gdb with multiple
processes/inferiors (multi cluster machine) a given breakpoint will
target an specific inferior. Current implementation of
tcg_insert_breakpoint and tcg_remove_breakpoint apply a given
breakpoint to all the cpus available in the system.
This is
This patch series modifies the gdbstub to address a bug running a
multi cluster machine in QEMU using TCG. The machine where the
problem was seen had several clusters of CPUs with similar
architectures and similar memory layout all working with physical
addresses. It was discovered under gdb debugg
On Wed, Jul 24, 2024 at 7:50 AM Markus Armbruster wrote:
>
> Fabiano Rosas writes:
>
> > Yichen Wang writes:
> >
> >> On Thu, Jul 11, 2024 at 2:53 PM Yichen Wang
> >> wrote:
> >>
> >>> diff --git a/migration/options.c b/migration/options.c
> >>> index 645f55003d..f839493016 100644
> >>> --- a/
On 06/09/2024 14:29, Philippe Mathieu-Daudé wrote:
Since v1:
- Correctly place patch hunks in corresponding patch
Mostly add documentation while reviewing them.
Based-on: <20240828122258.928947-1-mark.cave-ayl...@ilande.co.uk>
Philippe Mathieu-Daudé (3):
tests/unit: Strengthen FIFO8 tests
On 06/09/2024 14:29, Philippe Mathieu-Daudé wrote:
Add comments describing how the FIFO evolves during each test.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-fifo.c | 188 -
1 file changed, 187 insertions(+), 1 deletion(-)
diff --git a/
On 06/09/2024 14:29, Philippe Mathieu-Daudé wrote:
Test fifo8_peek_buf() can fill a buffer with wrapped data.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-fifo.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/tests/unit/test-fifo.c b/tests/unit/test
On 06/09/2024 14:29, Philippe Mathieu-Daudé wrote:
Replace reused bytes { 0x1, 0x2, 0x3, 0x4 } by { 0x9, 0xa, 0xb, 0xc }
to be sure a different value is overwritten.
Signed-off-by: Philippe Mathieu-Daudé
---
tests/unit/test-fifo.c | 12 ++--
1 file changed, 6 insertions(+), 6 deleti
On 04/09/2024 12:19, Mark Cave-Ayland wrote:
On 04/09/2024 11:53, Philippe Mathieu-Daudé wrote:
On 4/9/24 12:23, Mark Cave-Ayland wrote:
Update the Sun mouse implementation to use QemuInputHandler instead of the
legacy qemu_add_mouse_event_handler() function.
Note that this conversion adds e
On 06/09/2024 14:14, Philippe Mathieu-Daudé wrote:
Hi Mark,
On 28/8/24 14:22, Mark Cave-Ayland wrote:
Mark Cave-Ayland (9):
fifo8: rename fifo8_peekpop_buf() to fifo8_peekpop_bufptr()
fifo8: introduce head variable for fifo8_peekpop_bufptr()
fifo8: add skip parameter to fifo8_peekpop
On 28/08/2024 13:22, Mark Cave-Ayland wrote:
This tests the Fifo8 implementation for basic operations as well as testing for
the correct *_bufptr() including handling wraparound of the internal FIFO
buffer.
Hmmm this doesn't quite read correctly either - I think perhaps something like:
This
On 28/08/2024 13:22, Mark Cave-Ayland wrote:
This is a wrapper function around fifo8_peekpop_buf() that allows the caller to
peek into FIFO, including handling the case where there is a wraparound of the
peek into the FIFO
Looks like I missed a "the" out in the commit message above.
interna
The IMSIC state variable eistate[] is modified by CSR instructions
within a range dedicated to the local CPU and by MMIO writes from any CPU.
Access to eistate from MMIO accessors is protected by the BQL, but
read-modify-write (RMW) sequences from CSRRW do not acquire the BQL,
making the RMW sequen
Hi Mostafa,
On Fri, Sep 06, 2024 at 11:50:38AM +, Mostafa Saleh wrote:
> > <-- Help Needed --->
> > So, I'm wondering if anyone(s) might have some extra bandwidth in
> > the following months helping these two tasks, either of which can
> > be a standalone project I think.
>
> I don’t have pl
On Fri, Sep 06, 2024 at 05:49:08PM +0200, Philippe Mathieu-Daudé wrote:
> To improve readability, use the registerfields API.
> Define the register bits with FIELD(), and use the
> FIELD_EX8() and FIELD_DP8() macros. Remove the
> abbreviations in comments.
>
> Signed-off-by: Philippe Mathieu-Daudé
On Fri, Sep 06, 2024 at 05:49:09PM +0200, Philippe Mathieu-Daudé wrote:
> The next commit will clear the ONE_SHOT bit in the WRITE
> path (to keep the READ path trivial). As a preliminary step,
> pass the 'oneshot' value as argument to tmp105_alarm_update().
> No logical change intended.
>
> Signe
On Thu, Aug 29, 2024 at 05:31:17PM +0530, Shiva sagar Myana wrote:
> Add the SFDP table for the Micron Xccela mt35xu01g flash.
>
> Signed-off-by: Shiva sagar Myana
Reviewed-by: Francisco Iglesias
> ---
> V1->V2: Change subject and commit message
>
> hw/block/m25p80.c | 3 ++-
> hw/bloc
Vikram's email is bouncing, pause his maintainership until a new email is
provided.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1bc69828..ad957ca5e8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1945,7
Hi all,
I'm not in possesion of Vikram's new email address at his new job, because of
this the first patch in the series suggest's to remove Vikram as maintainer for
the Xilinx CAN models and also the CAN bus subsystem. The second patch in the
series updates my email address to the amd.com one on
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b03952f43e..a320ce759c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2701,6 +2701,7 @@ F: include/hw/rx/
CAN bus subsystem and hardware
M: Pavel Pisa
+M: Fra
Update my xilinx.com email address to my amd.com address.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ad957ca5e8..b03952f43e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1055,7 +1055,7 @@
From: Philippe Mathieu-Daudé
Straight forward conversion using the Python standard zipfile
module instead of avocado.utils package. Update the SHA1 hashes
to SHA256 hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Message-ID:
Straight forward conversion, just switch to SHA256 hashsum now.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py| 21 --
tests/functional/meson.build | 4 +++
tests/functional/test_alpha_clipper.py | 38 ++
3 files changed, 42
'meson test' has two ways to set how many tests to run in parallel:
* the command line --num-processes option
* the environment variable MESON_TESTTHREADS
If both are given, then it prefers the command line option over
the environment variable.
This is an unfortunate order of precedence, because
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
$ QEMU_TEST_ALLOW_UNTRUSTED_CODE=1 \
make check-functional-mipsel
...
▶ 4/4
test_mipsel_malta.MaltaMachineConsole.test_mips_malta32el_n
The cross-i686-tci CI job is persistently flaky with various tests
hitting timeouts. One theory for why this is happening is that we're
running too many tests in parallel and so sometimes a test gets
starved of CPU and isn't able to complete within the timeout.
Set the MESON_TESTTHREADS environme
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240826221058.75126-4-phi...@linaro.org>
[thuth: Use the LinuxKernelTest class]
Signed-off-by: Th
We've got to do_test_advcal_2018() here now that the test resides
in a separate file. Also switch back to the original URL (since
the site did not vanish as originally expected) and update the
hashsum to use SHA256.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py | 8 ---
Just had to update the asset checksum to use SHA256 instead of SHA1,
but apart from that it is a pretty much straightforward conversion.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 +
tests/avocado/boot_linux_console.py | 24 ---
tests/functional/meson
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240826221058.75126-5-phi...@linaro.org>
[thuth: Use LinuxKernelTest class]
Signed-off-by: Thomas
Copy the LinuxKernelTest from tests/acceptance/boot_linux_console.py
to be able to convert the related tests to the functional test framework
in the following patches.
Signed-off-by: Thomas Huth
---
tests/functional/qemu_test/__init__.py| 1 +
tests/functional/qemu_test/linuxkernel.py | 41
We've got to do_test_advcal_2018() here now that the test resides
in a separate file. Also switch back to the original URL (since
the site did not vanish as originally expected) and update the
hashsum to use SHA256.
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linux_console.py | 8
The CI job cross-i686-tci has been persistently flaky for what seems
like years now. Stefan Weil had a look and his conclusion was that
this happens because we run too many tests in parallel, and so
sometimes they starve each other of CPU and time out:
https://lore.kernel.org/qemu-devel/9692cfcb-ef
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240827094905.80648-5-phi...@linaro.org>
Signed-off-by: Thomas Huth
---
tests/avocado/boot_linu
Here's my suggestion how to convert the Avocado tests from
tests/avocado/boot_linux_console.py to the new functional framework:
Provide a LinuxKernelTest class in tests/functional/qemu_test/
so that the tests can be converted without too much modifications
(we just have to put them into separate fi
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240826221058.75126-3-phi...@linaro.org>
[thuth: Use LinuxKernelTest class]
Signed-off-by: Thomas
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
[thuth: Use LinuxKernelTest class for this test]
Message-ID: <20240827094905.80648-3-phi...@linaro.org>
Signed-
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to SHA256
hashes since SHA1 should not be used anymore nowadays.
Reviewed-by: Thomas Huth
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240827094905.80648-4-phi...@linaro.org>
Signed-off-by: Thomas Huth
--
From: Philippe Mathieu-Daudé
Straight forward conversion. Update the SHA1 hashes to
SHA256 hashes since SHA1 should not be used anymore nowadays.
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240827094905.80648-8-phi...@linaro.org>
[thuth: Use LinuxKernelTest class]
Signed-off-by: Thomas
Michael Tokarev writes:
> 28.08.2024 17:56, Fabiano Rosas wrote:
>> The send_cleanup() hook should free the p->iov that was allocated at
>> send_setup(). This was missed because the UADK code is conditional on
>> the presence of the accelerator, so it's not tested by default.
>>
>> Fixes: 819dd2
The enable bits in the EXT_CSD_PART_CONFIG ext_csd register do *not*
specify whether the boot partitions exist, but whether they are enabled
for booting. Existence of the boot partitions is specified by a
EXT_CSD_BOOT_MULT != 0.
Currently, in the case of boot-partition-size=1M and boot-config=0,
L
Hi Doug,
On Mon, Aug 26, 2024 at 08:49:27PM -0700, Doug Brown wrote:
> The read index should not be changed when storing a new message into the
> RX or TX FIFO. Changing it at this point will cause the reader to get
> out of sync. The wrapping of the read index is already handled by the
> pre-writ
On Mon, 2 Sept 2024 at 14:38, Jacob Abrams wrote:
>
> These changes allow the official STM32L4xx HAL UART driver to function
> properly with the b-l475e-iot01a machine.
>
> Modifying USART_CR1 TE bit should alter USART_ISR TEACK bit, and
> likewise for RE and REACK bit.
>
> USART registers may be
The Meson section has plenty of reviewers, and in order to reduce the
load on my Inbox a little bit, I'm stepping back as a reviewer here.
Signed-off-by: Thomas Huth
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0c1bc69828..c8115b00ca 100644
-
Hi Peter,
On Fri, Sep 06, 2024 at 03:36:10PM +0100, Peter Maydell wrote:
> On Tue, 27 Aug 2024 at 04:51, Doug Brown wrote:
> >
> > This series fixes several problems I ran into while trying to simulate
> > the AMD/Xilinx Versal CANFD controller in the xlnx-versal-virt machine
> > using Xilinx's v
Respin of Guenter fixes with:
- Use registerfields API
- Clear OS bit in WRITE path
Supersedes: <20240906132912.3826089-1-li...@roeck-us.net>
Guenter Roeck (2):
hw/sensor/tmp105: Coding style fixes
hw/sensor/tmp105: Lower 4 bit of limit registers are always 0
Philippe Mathieu-Daudé (3):
hw
From: Guenter Roeck
Per datasheet, "HIGH AND LOW LIMIT REGISTERS", the lower 4 bit
of the limit registers are unused and always report 0.
The lower 4 bit should not be used for temperature comparisons,
so mask the unused bits before storing the limits.
Signed-off-by: Guenter Roeck
Signed-off-by
To improve readability, use the registerfields API.
Define the register bits with FIELD(), and use the
FIELD_EX8() and FIELD_DP8() macros. Remove the
abbreviations in comments.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sensor/tmp105.c | 30 +++---
1 file changed, 19 in
The next commit will clear the ONE_SHOT bit in the WRITE
path (to keep the READ path trivial). As a preliminary step,
pass the 'oneshot' value as argument to tmp105_alarm_update().
No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/sensor/tmp105.c | 10 +-
1 file ch
Per datasheet, "ONE-SHOT (OS)", the OS bit always returns 0 when reading
the configuration register.
Clear the ONE_SHOT bit in the WRITE path. Now than the READ path is
simpler, we can also simplify tmp105_alarm_update().
Signed-off-by: Guenter Roeck
Signed-off-by: Philippe Mathieu-Daudé
---
h
Hi Guenter,
On 6/9/24 15:29, Guenter Roeck wrote:
Per datasheet, "ONE-SHOT (OS)", the OS bit always returns 0 when reading
the configuration register.
Signed-off-by: Guenter Roeck
---
hw/sensor/tmp105.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sensor/tmp105.c b
From: Guenter Roeck
Coding style asks for no space between variable and "++". The next patch
in this series will change one of those assignments. Instead of changing
just one with that patch, change all of them for consistency.
While at it, also fix other coding style problems reported by checkp
On 9/6/24 15:29, Guenter Roeck wrote:
Fix coding style issues as well as a couple of implementation bugs.
Guenter Roeck (3):
tmp105: Coding style fixes
tmp105: OS (one-shot) bit in configuration register always return
The upstream install instructions:
https://docs.gitlab.com/runner/install/linux-repository.html
Now refer to repositories and a setup script. Modernise the playbook
to use the preferred delivery method.
Signed-off-by: Alex Bennée
---
scripts/ci/setup/gitlab-runner.yml | 39 ++
On Tue, 3 Sept 2024 at 15:45, Alireza Sanaee wrote:
>
> This patch allows for easier manipulation of the cache description
> register, CCSIDR. Which is helpful for testing as well. Currently,
> numbers get hard-coded and might be prone to errors.
>
> Therefore, this patch adds a wrapper for differ
On Wed, 28 Aug 2024 at 12:16, Danny Canter wrote:
>
> This is preliminary work to split up hv_vm_create
> logic per platform so we can support creating VMs
> with > 64GB of RAM on Apple Silicon machines. This
> is done via ARM HVF's hv_vm_config_create() (and
> other APIs that modify this config t
On Wed, 28 Aug 2024 at 12:16, Danny Canter wrote:
>
> This patchsets focus is on lighting up the ability to create VMs with 64+GB
> of RAM through using some new APIs introduced in macOS 13. Due to the IPA
> sizes
> supported in macOS, the first version we can properly support this requirement
>
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