kvm_filer_msr() is only used from i386 kvm module. Make it static so that its
easy for developers to understand that its not used anywhere else.
Signed-off-by: Ani Sinha
---
target/i386/kvm/kvm.c | 4 +++-
target/i386/kvm/kvm_i386.h | 3 ---
2 files changed, 3 insertions(+), 4 deletions(-)
On 8/30/24 16:16, LIU Zhiwei wrote:
From: TANG Tiancheng
1.Address immediate value constraints in RISC-V Vector Extension 1.0 for
comparison instructions.
2.Extend comparison results from mask registers to SEW-width elements,
following recommendations in The RISC-V SPEC Volume I (Version 202
Hi Cedric,
> Subject: Re: [PATCH v2 08/11] aspeed/soc: introduce a new API to get the INTC
> orgate information
>
> Jamin,
>
> On 8/8/24 04:49, Jamin Lin wrote:
> > Currently, users can set the intc mapping table with enumerated device
> > id and device irq to get the INTC orgate input pins. How
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Follow the Svukte spec, do the memory access address checking
1. Include instruction fetches or explicit memory accesses
2. System run in effective privilege U or VU
3. Check senvcfg[UKTE] being set, or hstatus[HUKTE] being set if
instruction is HLV, HLVX, HSV and excute from U mode to VU mode
Svukte extension add HUKTE bit, bit[24] in hstatus CSR. The written
value will be masked when the svukte extension is not enabled.
When hstatus[HUKTE] bit is set, HLV/HLVX/HSV work in the U-mode should
do svukte check.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Jim Shu
---
Add "svukte" in the ISA string when svukte extension is enabled.
Signed-off-by: Fea.Wang
Reviewed-by: Frank Chang
Reviewed-by: Jim Shu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index fc3f75e826..a568194317 100644
--- a/
Refer to the draft of svukte extension from:
https://github.com/riscv/riscv-isa-manual/pull/1564
Svukte provides a means to make user-mode accesses to supervisor memory
raise page faults in constant time, mitigating attacks that attempt to
discover the supervisor software's address-space layout.
Svukte extension add UKTE bit, bit[8] in senvcfg CSR. The bit will be
supported when the svukte extension is enabled.
When senvcfg[UKTE] bit is set, the memory access from U-mode should do
the svukte check only except HLV/HLVX/HSV H-mode instructions which
depend on hstatus[HUKTE].
Signed-off-by:
On 03/09/2024 01.54, Alistair Francis wrote:
On Sat, Aug 31, 2024 at 1:35 AM Thomas Huth wrote:
Hi!
While running a lot of tests (i.e. with a very loaded machine), I noticed
that tests/avocado/riscv_opensbi.py is very flaky when the host machine is
slow. I can easily reproduce the problem
On 19/08/2024 13.31, Alistair Francis wrote:
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1].
s/charecters/characters/g
(also in the subject of the patch)
Let's update the SiFive UART to use a async sifive_uart_xmit() functio
On 19/08/2024 13.31, Alistair Francis wrote:
The current approach of using qemu_chr_fe_write() and ignoring the
return values results in dropped charecters [1]. Ideally we want to
s/charecters/characters/
report FIFO status to the guest, but the HTIF isn't a real UART, so we
don't really have
This test handles both, aarch64 and x86_64, with the same test code
(apart from some initial setup), so don't split this file by target
but add a check for self.arch in the main test function.
Signed-off-by: Thomas Huth
---
Based-on: 20240830133841.142644-1-th...@redhat.com
tests/avocado/avoca
Hi Cedric,
> Subject: Re: [PATCH v2 07/11] hw/i2c/aspeed: support high part dram offset for
> DMA 64 bits
>
> Jamin,
>
> Please adjust commit title
What do you think if I change the commit title as following.
hw/i2c/aspeed: Add support for dma_dram_offset attribute bits 33 and 32.
Thanks-Jami
Hi Cedric,
> Subject: Re: [PATCH v2 06/11] hw/i2c/aspeed: support Tx/Rx buffer 64 bits
> address
>
> Jamin,
>
> Please change commit title to
>
Thanks for review and suggestion.
Will fix them in v3 patch.
Jamin
>hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bits address
>
> So more propo
Hi Cedric,
> Subject: Re: [PATCH v2 04/11] hw/i2c/aspeed: introduce a new
> dma_dram_offset attribute in AspeedI2Cbus
>
> Jamin,
>
> In case you resend, would you mind changing the commit title and use a
> capital letter on the first word :
>
Okay, I will change all commit title to use a capit
Well, I was wrong -- it is sending a duplicate mouse packets when the mouse
wheel is rotated. The packets correctly represent the mouse buttons state.
I just now discovered that one of my Logitech mice sends continuous mouse
events when the wheel is rotated half a notch and held there. Another
Logi
On Thu, Aug 29, 2024 at 6:40 PM Andrew Jones wrote:
>
> While the spec doesn't state it, setting timecmp to UINT64_MAX is
> another way to stop a timer, as it's considered setting the next
> timer event to occur at infinity. And, even if the time CSR does
> eventually reach UINT64_MAX, the very ne
On Sat, Aug 31, 2024 at 1:35 AM Thomas Huth wrote:
>
>
> Hi!
>
> While running a lot of tests (i.e. with a very loaded machine), I noticed
> that tests/avocado/riscv_opensbi.py is very flaky when the host machine is
> slow. I can easily reproduce the problem when running a big compilation job
>
This still, but less frequently, shows the behavior of having the cursor
leap downwards occasionally. I may not be able to work on debugging it
until next week, but I'll try to see if I can figure it out sooner. The
hypothesis with the old code was that it was sending floods of mouse
messages and t
Hi Alireza,
On 2/9/24 22:32, Alireza Sanaee wrote:
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types
"Maciej S. Szmigiero" writes:
> From: "Maciej S. Szmigiero"
>
> Migration code wants to manage device data sending threads in one place.
>
> QEMU has an existing thread pool implementation, however it was limited
> to queuing AIO operations only and essentially had a 1:1 mapping between
> the cu
Update the Sun mouse implementation to use QemuInputHandler instead of the
legacy qemu_add_mouse_event_handler() function.
Note that this conversion adds extra sunmouse_* members to ESCCChannelState
but they are not added to the migration stream (similar to the Sun keyboard
members). If this were
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On 30.08.2024 22:22, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Add a basic support for receiving device state via multifd channels -
channels that are shared with RAM transfers.
To differentiate between a device state and a RAM packet the packet
header i
On 30.08.2024 20:13, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
This is necessary for multifd_send() to be able to be called
from multiple threads.
Signed-off-by: Maciej S. Szmigiero
---
migration/multifd.c | 24 ++--
1 file change
On 30.08.2024 20:55, Fabiano Rosas wrote:
"Maciej S. Szmigiero" writes:
From: "Maciej S. Szmigiero"
Since device state transfer via multifd channels requires multifd
channels with packets and is currently not compatible with multifd
compression add an appropriate query function so device can
On 2/9/24 21:55, Philippe Mathieu-Daudé wrote:
Hi Changbin,
On 30/8/24 12:53, Changbin Du via wrote:
Print errors before exit. Do not exit silently.
Signed-off-by: Changbin Du
---
v2: remove msg for arm_load_dtb.
---
hw/arm/boot.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm
Hi Changbin,
On 30/8/24 12:53, Changbin Du via wrote:
Print errors before exit. Do not exit silently.
Signed-off-by: Changbin Du
---
v2: remove msg for arm_load_dtb.
---
hw/arm/boot.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index d480a7da02cf..e15b
On 30/8/24 13:05, Daniel P. Berrangé wrote:
The meson rules were excluding the pbkdf crypto test when gnutls was the
crypto backend. It was then excluded again in #if statements in the test
file.
Rather than update these conditions, remove them all, and use the result
of the qcrypto_pbkdf_suppor
On 30/8/24 13:05, Daniel P. Berrangé wrote:
Both gnutls and gcrypt can be configured to exclude support for certain
algorithms via a runtime check against system crypto policies. Thus it
is not sufficient to have a compile time test for hash support in their
pbkdf implementations.
Signed-off-by:
On 30/8/24 13:57, Clément Léger wrote:
On 30/08/2024 13:31, Michael Tokarev wrote:
30.08.2024 14:14, Clément Léger wrote:
On some systems (MacOS for instance), sysconf(_SC_OPEN_MAX) can return
-1. In that case we should fallback to using the OPEN_MAX define.
According to "man sysconf", the OPEN
Thomas Huth writes:
> Running "make distclean" in the build tree currently fails since this
> tries to run the "distclean" target in the contrib/plugins/ folder, too,
> but the Makefile there is missing this target. Thus add 'distclean' there
> to fix this issue.
>
> And to avoid regressions with
On 9/2/24 10:52, Alex Bennée wrote:
Pierrick Bouvier writes:
Hi Xingran,
On 9/2/24 03:42, Alex Bennée wrote:
Xingran Wang writes:
Currently, the instruction count obtained by plugins using the translation
block execution callback is larger than the actual value. Adding callbacks
in cpu_re
Pierrick Bouvier writes:
> Hi Xingran,
>
> On 9/2/24 03:42, Alex Bennée wrote:
>> Xingran Wang writes:
>>
>>> Currently, the instruction count obtained by plugins using the translation
>>> block execution callback is larger than the actual value. Adding callbacks
>>> in cpu_restore_state_from_t
On 9/2/24 08:47, Thomas Huth wrote:
Running "make distclean" in the build tree currently fails since this
tries to run the "distclean" target in the contrib/plugins/ folder, too,
but the Makefile there is missing this target. Thus add 'distclean' there
to fix this issue.
And to avoid regressions
Hi Xingran,
On 9/2/24 03:42, Alex Bennée wrote:
Xingran Wang writes:
Currently, the instruction count obtained by plugins using the translation
block execution callback is larger than the actual value. Adding callbacks
in cpu_restore_state_from_tb() and cpu_io_recompile() allows plugins to
co
Running "make distclean" in the build tree currently fails since this
tries to run the "distclean" target in the contrib/plugins/ folder, too,
but the Makefile there is missing this target. Thus add 'distclean' there
to fix this issue.
And to avoid regressions with "make distclean", add this comma
Jamin,
On 8/8/24 04:49, Jamin Lin wrote:
Currently, users can set the intc mapping table with
enumerated device id and device irq to get the INTC orgate
input pins. However, some devices use the continuous bits number in the
same orgate. To reduce the enumerated device id definition,
create a ne
On Tue, Aug 13, 2024 at 04:01:02PM GMT, Roy Hopkins wrote:
Here is v5 of the set of patches to add support for IGVM files to QEMU. This is
based on commit 0f397dcfec of qemu.
This version addresses the review comments from v4 [1] plus changes required to
rebase on the master commit. As always, t
On Tue, Aug 13, 2024 at 04:01:15PM GMT, Roy Hopkins wrote:
The initialization sections in IGVM files contain configuration that
should be applied to the guest platform before it is started. This
includes guest policy and other information that can affect the security
level and the startup measure
On Tue, Aug 13, 2024 at 04:01:14PM GMT, Roy Hopkins wrote:
For confidential guests a policy can be provided that defines the
security level, debug status, expected launch measurement and other
parameters that define the configuration of the confidential platform.
This commit adds a new function
On Tue, Aug 13, 2024 at 04:01:13PM GMT, Roy Hopkins wrote:
Create an enum entry within FirmwareDevice for 'igvm' to describe that
an IGVM file can be used to map firmware into memory as an alternative
to pre-existing firmware devices.
Signed-off-by: Roy Hopkins
Acked-by: Michael S. Tsirkin
---
On Tue, Aug 13, 2024 at 04:01:09PM GMT, Roy Hopkins wrote:
The x86 segment registers are identified by the X86Seg enumeration which
includes LDTR and TR as well as the normal segment registers. The
function 'cpu_x86_load_seg_cache()' uses the enum to determine which
segment to set. However, speci
On Tue, Aug 13, 2024 at 04:01:08PM GMT, Roy Hopkins wrote:
The class function and implementations for updating launch data return
a code in case of error. In some cases an error message is generated and
in other cases, just the error return value is used.
This small refactor adds an 'Error **err
On Tue, Aug 13, 2024 at 04:01:07PM GMT, Roy Hopkins wrote:
When using an IGVM file the configuration of the system firmware is
defined by IGVM directives contained in the file. In this case the user
should not configure any pflash devices.
This commit skips initialization of the ROM mode when pf
On Tue, Aug 13, 2024 at 04:01:06PM GMT, Roy Hopkins wrote:
An IGVM file contains configuration of guest state that should be
applied during configuration of the guest, before the guest is started.
This patch allows the user to add an igvm-cfg object to an X86 machine
configuration that allows an
On Tue, Aug 13, 2024 at 04:01:05PM GMT, Roy Hopkins wrote:
Adds an IGVM loader to QEMU which processes a given IGVM file and
applies the directives within the file to the current guest
configuration.
The IGVM loader can be used to configure both confidential and
non-confidential guests. For conf
On Tue, Aug 13, 2024 at 04:01:04PM GMT, Roy Hopkins wrote:
In preparation for supporting the processing of IGVM files to configure
guests, this adds a set of functions to ConfidentialGuestSupport
allowing configuration of secure virtual machines that can be
implemented for each supported isolatio
On Tue, Aug 13, 2024 at 04:01:03PM GMT, Roy Hopkins wrote:
The IGVM library allows Independent Guest Virtual Machine files to be
parsed and processed. IGVM files are used to configure guest memory
layout, initial processor state and other configuration pertaining to
secure virtual machines.
This
On 8/8/24 04:49, Jamin Lin wrote:
Update test case to test lm75 temperature sensor.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
tests/avocado/machine_aspeed.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado/machine_aspee
These changes allow the official STM32L4xx HAL UART driver to function
properly with the b-l475e-iot01a machine.
Modifying USART_CR1 TE bit should alter USART_ISR TEACK bit, and
likewise for RE and REACK bit.
USART registers may be accessed via 16-bit instructions.
Reseting USART_CR1 UE bit shou
FCSR is a part of F extension. Print it to log if FPU option is enabled.
Signed-off-by: Maria Klauchek
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a90808a3ba..6ff6096777 100644
--- a/target/riscv/cpu.c
+++ b/targe
Jamin,
Please adjust commit title
On 8/8/24 04:49, Jamin Lin wrote:
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " which
is 64bits address.
The AST2700 support the maximum DRAM size is 8 GB.
The DRAM physical address range is from "0x
Jamin,
Please change commit title to
hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bits address
So more proposals to improve the commit log below,
On 8/8/24 04:49, Jamin Lin wrote:
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35)
And the base address of dram is "0x4 " wh
Jamin,
In case you resend, would you mind changing the commit title and use
a capital letter on the first word :
hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2Cbus
On 8/8/24 04:49, Jamin Lin wrote:
The "Current DMA Operating Address Status(0x50)" register of
I2C new mo
On Fri, 30 Aug 2024 at 16:21, Peter Maydell wrote:
>
> In vfp.decode we have the names of the VFNMA and VFNMS instructions
> the wrong way around. The architecture says that bit 6 is the 'op'
> bit, which is 1 for VFNMA and 1 for VFNMS, but we label these two
Doh. "1 for VFNMA and 0 for VFNMS"..
On 8/8/24 04:49, Jamin Lin wrote:
The "Current DMA Operating Address Status(0x50)" register of
I2C new mode has been removed in AST2700.
This register is used for debugging and it is a read only register.
To support AST2700 DMA mode, introduce a new
dma_dram_offset class attribute in AspeedI2Cbu
On 8/8/24 04:49, Jamin Lin wrote:
Introduce a new ast2700 class to support AST2700.
The I2C bus register memory regions and
I2C bus pool buffer memory regions are discontinuous
and they do not back compatible AST2600.
Add a new ast2700 i2c class init function to match the
address of I2C bus regi
On 8/8/24 04:49, Jamin Lin wrote:
It only support continuous register memory region for all I2C bus.
However, the register address of all I2c bus are discontinuous
for AST2700.
Ex: the register address of I2C bus for ast2700 as following.
0x100 - 0x17F: Device 0
0x200 - 0x27F: Device 1
0x300 - 0
On 8/8/24 04:49, Jamin Lin wrote:
It only support continuous pool buffer memory region for all I2C bus.
However, the pool buffer address of all I2c bus are discontinuous
for AST2700.
Ex: the pool buffer address of I2C bus for ast2700 as following.
0x1A0 - 0x1BF: Device 0 buffer
0x2A0 - 0x2BF: De
Elisha Hollander writes:
> But for qemu_plugin_update_ns
>
> On Mon, Sep 2, 2024, 15:38 Elisha Hollander wrote:
>
> Just checked with 9.0.2 it it still gives the error...
>
> On Wed, Aug 28, 2024, 14:05 Alex Bennée wrote:
>
> Elisha Hollander writes:
>
> > Although it gives `undefined symb
On 02/09/2024 12:34, Clément Léger wrote:
>
>
> On 02/09/2024 09:13, Tommy Wu wrote:
>> Because the RNMI interrupt trap handler address is implementation defined.
>> We add the `rnmi-interrupt-vector` and `rnmi-exception-vector` as the
>> property
>> of the harts. It’s very easy for users to
But for qemu_plugin_update_ns
On Mon, Sep 2, 2024, 15:38 Elisha Hollander
wrote:
> Just checked with 9.0.2 it it still gives the error...
>
> On Wed, Aug 28, 2024, 14:05 Alex Bennée wrote:
>
>> Elisha Hollander writes:
>>
>> > Although it gives `undefined symbol: qemu_plugin_scoreboard_free`.
Just checked with 9.0.2 it it still gives the error...
On Wed, Aug 28, 2024, 14:05 Alex Bennée wrote:
> Elisha Hollander writes:
>
> > Although it gives `undefined symbol: qemu_plugin_scoreboard_free`. But
> > probably I messed something up...
>
> Are you using an older QEMU? We should trigger
Level triggered interrupts are pending when either the interrupt line
is asserted or the interrupt was made pending by a GICD_ISPENDRn write.
Making a level triggered interrupt pending by software persists until
either the interrupt is acknowledged or cleared by writing
GICD_ICPENDRn. As long as th
On Mon, Sep 02, 2024 at 11:25:19AM +0100, Alireza Sanaee wrote:
>
> Hi Zhao,
>
> Yes, please keep me CCed.
>
> One thing that I noticed, sometimes, since you were going down the
> Intel path, some variables couldn't be NULL. But when I was gonna go
> down to ARM path, I faced some scenarios whe
On 23.08.2024 14:54, Alireza Sanaee via wrote:
Failure cases:
1) there are cases where QEMU might not have any clusters selected in the
-smp option, while user specifies caches to be shared at cluster level. In
this situations, qemu returns error.
2) There are other scenario
On Mon, 2 Sep 2024 11:25:36 +0100
Peter Maydell wrote:
> On Mon, 2 Sept 2024 at 11:07, Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Alireza,
> >
> > On 30/8/24 20:47, Alireza Sanaee via wrote:
> > > This patch allows for easier manipulation of the cache description
> > > register, CCSIDR. Which
On Fri, Aug 30, 2024 at 11:05 PM Si-Wei Liu wrote:
>
>
>
> On 8/30/2024 1:05 AM, Eugenio Perez Martin wrote:
> > On Fri, Aug 30, 2024 at 6:20 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 8/29/2024 9:53 AM, Eugenio Perez Martin wrote:
> >>> On Wed, Aug 21, 2024 at 2:56 PM Jonah Palmer
> >>> wrote:
> >
Xingran Wang writes:
> Currently, the instruction count obtained by plugins using the translation
> block execution callback is larger than the actual value. Adding callbacks
> in cpu_restore_state_from_tb() and cpu_io_recompile() allows plugins to
> correct the instruction count when exiting a t
On Mon, 2 Sept 2024 at 11:28, Alex Bennée wrote:
>
> Alireza Sanaee via writes:
>
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently
> > numbers get hard-coded and might be prone to errors.
> >
> > Therefore
On 02/09/2024 09:13, Tommy Wu wrote:
> Because the RNMI interrupt trap handler address is implementation defined.
> We add the `rnmi-interrupt-vector` and `rnmi-exception-vector` as the property
> of the harts. It’s very easy for users to set the address based on their
> expectation. This patch
Alireza Sanaee via writes:
> This patch allows for easier manipulation of the cache description
> register, CCSIDR. Which is helpful for testing as well. Currently
> numbers get hard-coded and might be prone to errors.
>
> Therefore, this patch adds wrappers for different types of CPUs
> availabl
On Mon, 2 Sept 2024 at 11:07, Philippe Mathieu-Daudé wrote:
>
> Hi Alireza,
>
> On 30/8/24 20:47, Alireza Sanaee via wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently
> > numbers get hard-coded and mi
On Sat, 31 Aug 2024 19:25:47 +0800
Zhao Liu wrote:
> Hi Alireza,
>
> Great to see your Arm side implementation!
>
> On Fri, Aug 23, 2024 at 01:54:44PM +0100, Alireza Sanaee wrote:
> > Date: Fri, 23 Aug 2024 13:54:44 +0100
> > From: Alireza Sanaee
> > Subject: [RFC PATCH 0/2] Specifying cache t
On 02/09/2024 11.48, Philippe Mathieu-Daudé wrote:
On 30/8/24 15:38, Thomas Huth wrote:
Nothing thrilling in here, it's just a straight forward conversion.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 1 +
tests/{avocado/vnc.py => functional/test_vnc.py
Haixu Cui writes:
> Hi Alex,
> Thanks a lot for your comments, please refer to my response below.
>
> On 8/28/2024 1:14 AM, Alex Bennée wrote:
>> Haixu Cui writes:
>> Apologies for the delay in getting to this.
>>
>>> This work is based on the virtio-spi spec, virtio-spi driver introduced b
Hi Alireza,
On 30/8/24 20:47, Alireza Sanaee via wrote:
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds wrappers for different typ
On 30/8/24 15:38, Thomas Huth wrote:
Nothing thrilling in here, it's just a straight forward conversion.
Signed-off-by: Thomas Huth
---
tests/functional/meson.build | 1 +
tests/{avocado/vnc.py => functional/test_vnc.py} | 12 +++-
2 files changed, 8 insertions(
On 30/8/24 15:38, Thomas Huth wrote:
Nothing thrilling in here, just straight forward conversions.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Thomas Huth
---
MAINTAINERS | 9 +--
tests/functional/meson.build | 11
.../test_pp
On Mon, 2 Sept 2024 at 09:51, Daniel P. Berrangé wrote:
>
> On Fri, Aug 30, 2024 at 02:22:50PM -0400, John Snow wrote:
> > Gave Dan a related answer. For you, my explanation is:
> >
> > - It's nice to have just one configuration for static analysis in just one
> > place
> > - It's nice to have tha
On Mon, Sep 02, 2024 at 02:03:43AM +0200, Paolo Bonzini wrote:
> GCC is reporting a NULL pointer dereference when compiling aio_wait_kick()
> with LTO.
>
> The issue is that test-nested-aio-poll.c does not call qemu_init_main_loop().
> It doesn't _need_ to because it never calls AIO_WAIT_WHILE(),
Hi Amit,
On 02/09/24 11:19, Amit Machhiwal wrote:
On 2024/07/31 11:20 AM, Aditya Gupta wrote:
<...snip...>
Git Tree for Testing
QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-v6-pseries
Has been tested with following cases:
* '-M pseries' / '-M pseries -cpu Power11'
Hi Alex,
Thanks a lot for your comments, please refer to my response below.
On 8/28/2024 1:14 AM, Alex Bennée wrote:
Haixu Cui writes:
Apologies for the delay in getting to this.
This work is based on the virtio-spi spec, virtio-spi driver introduced by
the following patch series:
- htt
On Fri, Aug 30, 2024 at 02:22:50PM -0400, John Snow wrote:
> Gave Dan a related answer. For you, my explanation is:
>
> - It's nice to have just one configuration for static analysis in just one
> place
> - It's nice to have that configuration follow python ecosystem norms
> - It's nice to use sta
On 30/8/24 15:38, Thomas Huth wrote:
The avocado test defined test functions for both, riscv32 and riscv64.
Since we can run the whole file with multiple targets in the new
framework, we can now consolidate the functions so we have to only
define one function per machine now.
However, we have to
On 30/8/24 15:38, Thomas Huth wrote:
From: Daniel P. Berrangé
The 'Asset' class is a simple module that declares a downloadable
asset that can be cached locally. Downloads are stored in the user's
home dir at ~/.cache/qemu/download, using a sha256 sum of the URL.
Signed-off-by: Daniel P. Berra
On Sun, Sep 01, 2024 at 03:01:12PM GMT, Volker Rümelin wrote:
> Currently, the guest may write to the device configuration space,
> whereas the virtio sound device specification in chapter 5.14.4
> clearly states that the fields in the device configuration space
> are driver-read-only.
>
> Remove
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 98e6940e93..7ee7b9c4ee 100644
--- a/target/riscv/cpu.c
+++ b/target/ri
Because the RNMI interrupt trap handler address is implementation defined.
We add the `rnmi-interrupt-vector` and `rnmi-exception-vector` as the property
of the harts. It’s very easy for users to set the address based on their
expectation. This patch also adds the functionality to handle the RNMI s
The Smrnmi extension adds the `MNSCRATCH`, `MNEPC`, `MNCAUSE`,
`MNSTATUS` CSRs.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 5 +++
target/riscv/cpu.h | 4 ++
target/riscv/cpu_bits.h | 11 ++
target/riscv/csr.c |
The boolean variable `ext_smrnmi` is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
Reviewed-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_
This patch adds a new instruction `mnret`. `mnret` is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang
Signed-off-by: Tommy Wu
---
target/ris
This patchset added support for Smrnmi Extension in RISC-V.
There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:
=
* mnscratch (0x740)
* mnepc (0x741)
* mncause (0x742)
*
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