Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 2024/8/2 14:45, Richard Henderson wrote: On 8/2/24 16:21, LIU Zhiwei wrote: By the way, the MXL is const now in recently updated RISC-V specification. Oh yes? Yes.  In 1.13 privileged specification about MISA CSR: "The MXL field is read-only. If misa is nonzero, the MXL field indicates

[PATCH for-9.2 v6 4/9] pcie_sriov: Check PCI Express for SR-IOV PF

SR-IOV requires PCI Express. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index ec8fc0757b92..3af0cc7d560a 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sriov.c @@ -42,6 +42,11 @@ bool

[PATCH for-9.2 v6 7/9] virtio-net: Implement SR-IOV VF

A virtio-net device can be added as a SR-IOV VF to another virtio-pci device that will be the PF. Signed-off-by: Akihiko Odaki --- hw/virtio/virtio-net-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/virtio/virtio-net-pci.c b/hw/virtio/virtio-net-pci.c index e03543a70a75..dba4987d6e

[PATCH for-9.2 v6 8/9] docs: Document composable SR-IOV device

Signed-off-by: Akihiko Odaki --- MAINTAINERS | 1 + docs/system/index.rst | 1 + docs/system/sriov.rst | 36 3 files changed, 38 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e34c2bd4cda2..72b3c6736088 100644 --- a/MAINTAINERS +++ b/M

[PATCH for-9.2 v6 1/9] hw/pci: Do not add ROM BAR for SR-IOV VF

A SR-IOV VF cannot have a ROM BAR. Co-developed-by: Yui Washizu Signed-off-by: Akihiko Odaki --- hw/pci/pci.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index d2eaf0c51dde..60b1747d60e6 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2359,6 +2359,14

[PATCH for-9.2 v6 9/9] pcie_sriov: Make a PCI device with user-created VF ARI-capable

Signed-off-by: Akihiko Odaki --- docs/system/sriov.rst | 3 ++- include/hw/pci/pcie_sriov.h | 7 +-- hw/pci/pcie_sriov.c | 12 hw/virtio/virtio-pci.c | 16 ++-- 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/docs/system/sriov.rst

[PATCH for-9.2 v6 6/9] virtio-pci: Implement SR-IOV PF

Allow user to attach SR-IOV VF to a virtio-pci PF. Signed-off-by: Akihiko Odaki --- include/hw/virtio/virtio-pci.h | 1 + hw/virtio/virtio-pci.c | 20 +++- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/

[PATCH for-9.2 v6 5/9] pcie_sriov: Allow user to create SR-IOV device

A user can create a SR-IOV device by specifying the PF with the sriov-pf property of the VFs. The VFs must be added before the PF. A user-creatable VF must have PCIDeviceClass::sriov_vf_user_creatable set. Such a VF cannot refer to the PF because it is created before the PF. A PF that user-creata

[PATCH for-9.2 v6 2/9] hw/pci: Fix SR-IOV VF number calculation

pci_config_get_bar_addr() had a division by vf_stride. vf_stride needs to be non-zero when there are multiple VFs, but the specification does not prohibit to make it zero when there is only one VF. Do not perform the division for the first VF to avoid division by zero. Signed-off-by: Akihiko Odak

[PATCH for-9.2 v6 3/9] pcie_sriov: Ensure PF and VF are mutually exclusive

A device cannot be a SR-IOV PF and a VF at the same time. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 5 + 1 file changed, 5 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index 56523ab4e833..ec8fc0757b92 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_sr

[PATCH for-9.2 v6 0/9] virtio-net: add support for SR-IOV emulation

Based-on: <20240802-reuse-v11-0-fb83bb8c1...@daynix.com> ("[PATCH for-9.2 v11 00/11] hw/pci: SR-IOV related fixes and improvements") Introduction This series is based on the RFC series submitted by Yui Washizu[1]. See also [2] for the context. This series enables SR-IOV emulation fo

Re: [PATCH v2 3/3] target/riscv: Relax fld alignment requirement

On 8/2/24 16:27, LIU Zhiwei wrote: Does this really have byte atomicity, not atomic on two aligned 32-bit loads (which would be MO_ATOM_IFALIGN_PAIR). The specification doesn't rule it. I think we can choose either way. The byte atomicity may expose more problems on alignment. Ok. r~

Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 8/2/24 16:42, LIU Zhiwei wrote: On 2024/8/2 13:47, Richard Henderson wrote: On 8/2/24 13:16, LIU Zhiwei wrote: Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei ---   target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--   1 fi

Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 8/2/24 16:21, LIU Zhiwei wrote: By the way, the MXL is const now in recently updated RISC-V specification. Oh yes? Then perhaps we should rename misa_mxl_max to misa_mxl. r~

Re: [PATCH v4 6/6] hvf: arm: Do not advance PC when raising an exception

On 2024/08/02 15:41, Michael Tokarev wrote: 20.07.2024 12:30, Akihiko Odaki wrote: This is identical with commit 30a1690f2402 ("hvf: arm: Do not advance PC when raising an exception") but for writes instead of reads. Fixes: a2260983c655 ("hvf: arm: Add support for GICv3") Signed-off-by: Akihiko

Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 2024/8/2 13:47, Richard Henderson wrote: On 8/2/24 13:16, LIU Zhiwei wrote: Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei ---   target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--   1 file changed, 2 insertions(+), 2 del

Re: [PATCH v4 6/6] hvf: arm: Do not advance PC when raising an exception

20.07.2024 12:30, Akihiko Odaki wrote: This is identical with commit 30a1690f2402 ("hvf: arm: Do not advance PC when raising an exception") but for writes instead of reads. Fixes: a2260983c655 ("hvf: arm: Add support for GICv3") Signed-off-by: Akihiko Odaki Is it -stable material (together wi

Re: [PATCH v2 1/3] target/riscv: Remove redundant insn length check for zama16b

On 2024/8/2 13:38, Richard Henderson wrote: On 8/2/24 13:16, LIU Zhiwei wrote: @@ -47,7 +47,12 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)   REQUIRE_FPU;   REQUIRE_EXT(ctx, RVD);   -    if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) { +    /* + * Zama16b app

Re: [PATCH v2 3/3] target/riscv: Relax fld alignment requirement

On 2024/8/2 13:52, Richard Henderson wrote: On 8/2/24 13:16, LIU Zhiwei wrote: According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64

Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 2024/8/2 13:47, Richard Henderson wrote: On 8/2/24 13:16, LIU Zhiwei wrote: Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei ---   target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--   1 file changed, 2 insertions(+), 2 del

Re: [RFC 0/2] Identify aliased maps in vdpa SVQ iova_tree

On 8/1/2024 1:22 AM, Eugenio Perez Martin wrote: On Thu, Aug 1, 2024 at 2:41 AM Si-Wei Liu wrote: Hi Jonah, On 7/31/2024 7:09 AM, Jonah Palmer wrote: Let me clarify, correct me if I was wrong: 1) IOVA allocator is still implemented via a tree, we just don't need to store how the IOVA is u

Re: [PATCH v2 3/3] target/riscv: Relax fld alignment requirement

On 8/2/24 13:16, LIU Zhiwei wrote: According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will

[PATCH] hw/ufs: add basic info of query response upiu

Modify to fill the opcode, idn, index, selector information of all Query Response UPIU. because attr and flag operation of query response upiu need these information too. Signed-off-by: KyoungrulKim --- hw/ufs/ufs.c | 13 + hw/ufs/ufs.h | 1 + 2 files changed, 10 insertions(+), 4 de

Re: [PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

On 8/2/24 13:16, LIU Zhiwei wrote: Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/

Re: [PATCH v2 1/3] target/riscv: Remove redundant insn length check for zama16b

On 8/2/24 13:16, LIU Zhiwei wrote: @@ -47,7 +47,12 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); -if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) { +/* + * Zama16b applies to loads and stores of no more than MXLE

[PATCH] vhost: Add VIRTIO_NET_F_RSC_EXT to vhost feature bits

VIRTIO_NET_F_RSC_EXT is implemented in the rx data path, which vhost implements, so vhost needs to support the feature if it is ever to be enabled with vhost. The feature must be disabled otherwise. Fixes: 2974e916df87 ("virtio-net: support RSC v4/v6 tcp traffic for Windows HCK") Reported-by: Jas

[PATCH for-9.2 v11 07/11] pcie_sriov: Release VFs failed to realize

Release VFs failed to realize just as we do in unregister_vfs(). Fixes: 7c0fa8dff811 ("pcie: Add support for Single Root I/O Virtualization (SR/IOV)") Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sri

[PATCH for-9.2 v11 08/11] pcie_sriov: Remove num_vfs from PCIESriovPF

num_vfs is not migrated so use PCI_SRIOV_CTRL_VFE and PCI_SRIOV_NUM_VF instead. Signed-off-by: Akihiko Odaki --- include/hw/pci/pcie_sriov.h | 1 - hw/pci/pcie_sriov.c | 28 hw/pci/trace-events | 2 +- 3 files changed, 21 insertions(+), 10 deletions

[PATCH for-9.2 v11 03/11] hw/ppc/spapr_pci: Do not reject VFs created after a PF

A PF may automatically create VFs and the PF may be function 0. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index f63182a03c41..ed4454bbf79e 100644 --- a/hw/ppc/spapr_pci.c +++

[PATCH for-9.2 v11 06/11] pcie_sriov: Reuse SR-IOV VF device instances

Disable SR-IOV VF devices by reusing code to power down PCI devices instead of removing them when the guest requests to disable VFs. This allows to realize devices and report VF realization errors at PF realization time. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 5 --- incl

[PATCH for-9.2 v11 05/11] pcie_sriov: Ensure VF function number does not overflow

pci_new() aborts when creating a VF with a function number equals to or is greater than PCI_DEVFN_MAX. Signed-off-by: Akihiko Odaki --- docs/pcie_sriov.txt | 8 +--- include/hw/pci/pcie_sriov.h | 5 +++-- hw/net/igb.c| 13 ++--- hw/nvme/ctrl.c |

[PATCH for-9.2 v11 04/11] pcie_sriov: Do not manually unrealize

A device gets automatically unrealized when being unparented. Signed-off-by: Akihiko Odaki --- hw/pci/pcie_sriov.c | 4 1 file changed, 4 deletions(-) diff --git a/hw/pci/pcie_sriov.c b/hw/pci/pcie_sriov.c index e9b23221d713..499becd5273f 100644 --- a/hw/pci/pcie_sriov.c +++ b/hw/pci/pcie_

[PATCH for-9.2 v11 01/11] hw/pci: Rename has_power to enabled

The renamed state will not only represent powering state of PFs, but also represent SR-IOV VF enablement in the future. Signed-off-by: Akihiko Odaki --- include/hw/pci/pci.h| 7 ++- include/hw/pci/pci_device.h | 2 +- hw/pci/pci.c| 14 +++--- hw/pci/pci_host

[PATCH for-9.2 v11 10/11] hw/pci: Use -1 as the default value for rombar

vfio_pci_size_rom() distinguishes whether rombar is explicitly set to 1 by checking dev->opts, bypassing the QOM property infrastructure. Use -1 as the default value for rombar to tell if the user explicitly set it to 1. The property is also converted from unsigned to signed. -1 is signed so it is

[PATCH for-9.2 v11 11/11] hw/qdev: Remove opts member

It is no longer used. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Markus Armbruster --- include/hw/qdev-core.h | 4 hw/core/qdev.c | 1 - system/qdev-monitor.c | 12 +++- 3 files changed, 7 insertions(+), 10 deletions(-) diff --git a/i

[PATCH for-9.2 v11 09/11] pcie_sriov: Register VFs after migration

pcie_sriov doesn't have code to restore its state after migration, but igb, which uses pcie_sriov, naively claimed its migration capability. Add code to register VFs after migration and fix igb migration. Fixes: 3a977deebe6b ("Intrdocue igb device emulation") Signed-off-by: Akihiko Odaki --- in

[PATCH for-9.2 v11 02/11] hw/ppc/spapr_pci: Do not create DT for disabled PCI device

Disabled means it is a disabled SR-IOV VF or it is powered off, and hidden from the guest. Signed-off-by: Akihiko Odaki --- hw/ppc/spapr_pci.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7cf9904c3546..f63182a03c41 100644 --- a/hw/ppc/spap

[PATCH for-9.2 v11 00/11] hw/pci: SR-IOV related fixes and improvements

Supersedes: <20240714-rombar-v2-0-af1504ef5...@daynix.com> ("[PATCH v2 0/4] hw/pci: Convert rom_bar into OnOffAuto") I submitted a RFC series[1] to add support for SR-IOV emulation to virtio-net-pci. During the development of the series, I fixed some trivial bugs and made improvements that I think

Re: [PULL v2 17/61] virtio-snd: check for invalid param shift operands

Am 01.08.24 um 10:22 schrieb Michael S. Tsirkin: > On Sat, Jul 27, 2024 at 08:55:10AM +0200, Volker Rümelin wrote: >>> From: Manos Pitsidianakis >>> >>> When setting the parameters of a PCM stream, we compute the bit flag >>> with the format and rate values as shift operand to check if they are >>

[PATCH for-9.1] target/i386: Fix VSIB decode

With normal SIB, index == 4 indicates no index. With VSIB, there is no exception for VR4/VR12. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2474 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 20 ++-- target/i386/tcg/decode-new.c.inc | 3 ++-

Re: [PATCH v2 4/4] virtio-net: Add support for USO features

On 2024/08/02 0:13, Peter Xu wrote: On Thu, Aug 01, 2024 at 02:05:54PM +0900, Akihiko Odaki wrote: On 2024/07/31 4:11, Peter Xu wrote: On Tue, Jul 30, 2024 at 07:46:12PM +0100, Daniel P. Berrangé wrote: On Tue, Jul 30, 2024 at 02:13:51PM -0400, Peter Xu wrote: On Mon, Jul 29, 2024 at 06:26:41

[PULL 7/8] net: update netdev stream man page with the reconnect parameter

From: Laurent Vivier "-netdev stream" supports a reconnect parameter that attempts to reconnect automatically the socket if it is disconnected. The code has been added but the man page has not been updated. Fixes: 148fbf0d58a6 ("net: stream: add a new option to automatically reconnect" Signed-of

[PULL 2/8] virtio-net: Ensure queue index fits with RSS

From: Akihiko Odaki Ensure the queue index points to a valid queue when software RSS enabled. The new calculation matches with the behavior of Linux's TAP device with the RSS eBPF program. Fixes: 4474e37a5b3a ("virtio-net: implement RX RSS processing") Reported-by: Zhibin Hu Cc: qemu-sta...@non

[PULL 8/8] net: Reinstate '-net nic, model=help' output as documented in man page

From: David Woodhouse While refactoring the NIC initialization code, I broke '-net nic,model=help' which no longer outputs a list of available NIC models. Fixes: 2cdeca04adab ("net: report list of available models according to platform") Cc: qemu-sta...@nongnu.org Signed-off-by: David Woodhouse

[PULL 4/8] net: update netdev stream/dgram man page

From: Laurent Vivier Add the description of "-netdev stream" and "-netdev dgram" in the QEMU manpage. Add some examples on how to use them. Fixes: 5166fe0ae46d ("qapi: net: add stream and dgram netdevs") Signed-off-by: Laurent Vivier Reviewed-by: Marc-André Lureau Signed-off-by: Jason Wang -

[PULL 3/8] virtio-net: Fix network stall at the host side waiting for kick

From: thomas Patch 06b12970174 ("virtio-net: fix network stall under load") added double-check to test whether the available buffer size can satisfy the request or not, in case the guest has added some buffers to the avail ring simultaneously after the first check. It will be lucky if the availab

[PULL 5/8] net: update netdev stream man page with unix socket

From: Laurent Vivier Add the description of "-netdev stream" with a unix domain socket. The code has been added but the man page has not been updated. Include an example how to use "-netdev stream" and "passt" in place of "-netdev user". ("passt" is a non privileged translation proxy between lay

[PULL 1/8] rtl8139: Fix behaviour for old kernels.

From: Hans Old linux kernel rtl8139 drivers (ex. debian 2.1) uses outb to set the rx mode for RxConfig. Unfortunatelly qemu does not support outb for RxConfig. Signed-off-by: Hans Signed-off-by: Jason Wang --- hw/net/rtl8139.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff -

[PULL 0/8] Net patches

The following changes since commit 31669121a01a14732f57c49400bc239cf9fd505f: Merge tag 'pull-target-arm-20240801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-08-02 08:18:37 +1000) are available in the Git repository at: https://github.com/jasowang/qem

[PULL 6/8] net: update netdev dgram man page with unix socket

From: Laurent Vivier Add the description of "-netdev dgram" with a unix domain socket. The code has been added but the man page has not been updated. Fixes: 784e7a253104 ("net: dgram: add unix socket") Signed-off-by: Laurent Vivier Reviewed-by: Marc-André Lureau Signed-off-by: Jason Wang ---

[PATCH v2 3/3] target/riscv: Relax fld alignment requirement

According to the risc-v specification: "FLD and FSD are only guaranteed to execute atomically if the effective address is naturally aligned and XLEN≥64." We currently implement fld as MO_ATOM_IFALIGN when XLEN < 64, which does not violate the rules. But it will hide some problems. So relax it to M

[PATCH v2 2/3] target/riscv: Add MXLEN check for F/D/Q applies to zama16b

Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q extensions. Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr

[PATCH v2 1/3] target/riscv: Remove redundant insn length check for zama16b

Compressed encodings also applies to zama16b. https://github.com/riscv/riscv-isa-manual/pull/1557 Suggested-by: Alistair Francis Signed-off-by: LIU Zhiwei --- target/riscv/insn_trans/trans_rvd.c.inc | 9 +++-- target/riscv/insn_trans/trans_rvf.c.inc | 4 ++-- target/riscv/insn_trans/trans_r

[PATCH v2 0/3] target/riscv: Remove redundant insn length check for zama16b

In this patch set, we remove the redundant insn length check for zama16b as the specification clarified that zama16b applies to compressed encodings[1]. Richard points out we should obey the MXLEN requirement for F/D/Q loads or stores, so we add this constraint for trans_fld/fsd. I notice that w

Re: [PATCH v5 00/19] Reconstruct loongson ipi driver

在 2024/7/23 下午6:19, Philippe Mathieu-Daudé 写道: On 19/7/24 15:04, Philippe Mathieu-Daudé wrote: On 19/7/24 14:56, Jiaxun Yang wrote: 在2024年7月18日七月 下午9:32，Philippe Mathieu-Daudé写道： Since v4: - Fix build failure due to rebase (Song) - Loongarch -> LoongArch (Song) - Added Song's tags Since v3:

Re: [PATCH v1] target/i386: Always set leaf 0x1f

On Wed, Jul 31, 2024 at 07:30:44PM +0530, Manish wrote: > Date: Wed, 31 Jul 2024 19:30:44 +0530 > From: Manish > Subject: Re: [PATCH v1] target/i386: Always set leaf 0x1f > > > On 30/07/24 6:39 pm, Igor Mammedov wrote: > > !---| > >

[PATCH v2 1/3] nbd: CVE-XXX: Use cookie to track generation of nbd-server

As part of the QMP command nbd-server-start, the blockdev code was creating a single global nbd_server object, and telling the qio code to accept one or more client connections to the exposed listener socket. But even though we tear down the listener socket during a subsequent QMP nbd-server-stop,

[PATCH v2 3/3] nbd: Minor style fixes

Touch up a comment with the wrong type name, and an over-long line, both noticed while working on the previous patches. Signed-off-by: Eric Blake --- nbd/server.c | 2 +- qemu-nbd.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/nbd/server.c b/nbd/server.c index 7c37d9

[PATCH v2 2/3] nbd: CVE-XXX: Close stray client sockets at server shutdown

A malicious client can attempt to connect to an NBD server, and then intentionally not progress in the handshake. This can form a resource leak for as long as the client wants, when the client does not catch our attention by failing to provide TLS credentials; although it can be bounded by max-con

[PATCH v2 for-9.1 0/3] Avoid NBD crash on nbd-server-stop

v1 was here: https://lists.gnu.org/archive/html/qemu-devel/2024-06/msg01609.html Since then, I've applied with Red Hat to get a CVE assigned (a client not using TLS should never be able to cause the destination qemu to crash during live storage migration), and will update to include that number on

Re: [PATCH v4 04/11] pnv/xive2: Add NVG and NVC to cache watch facility

On Thu Jul 25, 2024 at 7:21 AM AEST, Michael Kowal wrote: > From: Frederic Barrat > > The cache watch facility uses the same register interface to handle > entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX > specification' register tells the table type. So far, that bit-field > wa

[PATCH] target/arm: add support for 64-bit PMCCNTR in AArch32 mode

See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en Signed-off-by: Alex Richardson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c ind

Re: [PULL 0/4] target-arm queue

in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240801 for you to fetch changes up to 5e8e4f098d872818aa9a138a171200068b81c8d1: target/xtensa: Correct assert condition in handle_interrupt() (2024-08-01 10:5

[PATCH v2] target/arm: Fix BTI versus CF_PCREL

With pcrel, we cannot check the guarded page bit at translation time, as different mappings of the same physical page may or may not have the GP bit set. Instead, add a couple of helpers to check the page at runtime, after all other filters that might obviate the need for the check. The set_btype

[PATCH] target/i386: SEV: fix mismatch in vcek-disabled property name

The vcek-disabled property of the sev-snp-guest object is misspelled vcek-required (which I suppose would use the opposite polarity) in the call to object_class_property_add_bool(). Fix it. Reported-by: Zixi Chen Cc: Pankaj Gupta Signed-off-by: Paolo Bonzini --- target/i386/sev.c | 2 +- 1 fi

Re: [PATCH 0/5] docs: more conversions from txt to rst

On 8/2/24 03:01, Peter Maydell wrote: Peter Maydell (5): docs/specs/rocker.txt: Convert to rST docs/interop/nbd.txt: Convert to rST docs/interop/parallels.txt: Convert to rST docs/interop/prl-xml.txt: Convert to rST docs/interop/prl-xml.rst: Fix minor grammar nits Reviewed-by: Ri

Re: [PULL 00/19] virtio,pci,pc: fixes

On 8/1/24 20:35, Michael S. Tsirkin wrote: The following changes since commit e9d2db818ff934afb366aea566d0b33acf7bced1: Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2024-08-01 07:31:49 +1000) are available in the Git repository at: https://git.kernel.org/pub/

Re: [PATCH v3 08/24] tests/functional: add a module for handling asset download & caching

On 7/31/24 03:03, Daniel P. Berrangé wrote: +def __init__(self, url, hash): +self.url = url +self.hash = hash +self.cache_dir = Path(Path("~").expanduser(), + ".cache", "qemu", "download") +self.cache_file = Path(self.cache_dir, +

[PATCH qemu] target/arm: add support for 64-bit PMCCNTR in AArch32 mode

From: Alex Richardson See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en Signed-off-by: Alex Richardson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b

[PATCH qemu] target/arm: add support for 64-bit PMCCNTR in AArch32 mode

From: Alex Richardson See https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en Signed-off-by: Alex Richardson --- target/arm/helper.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/helper.c b

Re: [PATCH] linux-user/elfload: Fix pr_pid values in core files

On 8/2/24 06:23, Ilya Leoshkevich wrote: Analyzing qemu-produced core dumps of multi-threaded apps runs into: (gdb) info threads [...] 21 Thread 0x3ff83cc0740 (LWP 9295) warning: Couldn't find general-purpose registers in core file. in ?? () The reason is that all pr

Re: [PATCH v2 05/24] target/riscv: tracking indirect branches (fcfi) for zicfilp

On 8/2/24 03:05, Deepak Gupta wrote: On Thu, Aug 1, 2024 at 2:12 AM Richard Henderson wrote: On 8/1/24 16:59, Deepak Gupta wrote: hmm... you've suggested below to use `aarch64_tr_translate_insn` and check if it's the first instruction. and put the check there. In that case I won't need FCFI_L

[PATCH 10/13] pnv/xive: Add special handling for pool targets

From: Glenn Miles Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use some of the registers from the physical ring in the TIMA. Specifically, the NSR, PIPR and C

[PATCH 04/13] pnv/xive2: Support for "OS LGS Push" TIMA operation

From: Glenn Miles Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we j

[PATCH 01/13] pnv/xive: TIMA patch sets pre-req alignment and formatting changes

From: Michael Kowal Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets. Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'. There ar

[PATCH 05/13] ppc/xive2: Dump more NVP state with 'info pic'

From: Frederic Barrat The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group. Also, print the Reporting Cache Line address, if defined. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2_regs.h | 1 + hw/intc/xive2.c

[PATCH 08/13] ppc/xive2: Support "Pull Thread Context to Register" operation

From: Glenn Miles Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Re

[PATCH 00/13] XIVE2 changes for TIMA operations

In XIVE Gen 2 there are many operations that were not modeled and are needed for PowerVM. These changes are associated with the following Thread Interrupt Management Area subjects: - OS context - Thread context - Pulling contexts to 'cache lines' - Pool targets - Enhaced trace data for XIVE G

[PATCH 12/13] pnv/xive2: TIMA support for 8-byte OS context push for PHYP

From: Glenn Miles PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails

[PATCH 13/13] pnv/xive2: TIMA CI ops using alternative offsets or byte lengths

Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to registeradded lwz@0x

[PATCH 09/13] ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"

From: Glenn Miles Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREA

[PATCH 06/13] ppc/xive2: Dump the VP-group and crowd tables with 'info pic'

From: Frederic Barrat The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2.h | 12 ++ include/hw/ppc/xive2_regs.

[PATCH 11/13] pnv/xive: Update PIPR when updating CPPR

From: Glenn Miles Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Signed-

[PATCH 03/13] ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"

From: Frederic Barrat Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CA

[PATCH 02/13] pnv/xive2: Define OGEN field in the TIMA

From: Frederic Barrat The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive_regs.h | 1 + hw/intc/xive.c | 4 2 files changed, 5 insertions(+) diff --git a/includ

[PATCH 07/13] ppc/xive2: Allow 1-byte write of Target field in TIMA

From: Glenn Miles When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Sign

[PATCH] linux-user/elfload: Fix pr_pid values in core files

Analyzing qemu-produced core dumps of multi-threaded apps runs into: (gdb) info threads [...] 21 Thread 0x3ff83cc0740 (LWP 9295) warning: Couldn't find general-purpose registers in core file. in ?? () The reason is that all pr_pid values are the same, because the same Task

Re: [PATCH 2/2] migration/multifd: Fix multifd_send_setup cleanup when channel creation fails

Peter Xu writes: > On Thu, Aug 01, 2024 at 02:41:01PM -0300, Fabiano Rosas wrote: >> When a channel fails to create, the code currently just returns. This >> is wrong for two reasons: >> >> 1) Channel n+1 will not get to initialize it's semaphores, leading to >>an assert when terminate_threa

Re: [PATCH 1/2] migration: Fix cleanup of iochannel in file migration

On Thu, Aug 01, 2024 at 02:41:00PM -0300, Fabiano Rosas wrote: > The QIOChannelFile object already has its reference decremented by > g_autoptr. Trying to unref an extra time causes: > > ERROR:../qom/object.c:1241:object_unref: assertion failed: (obj->ref > 0) > > Fixes: a701c03dec ("migration: D

Re: [PATCH 2/2] migration/multifd: Fix multifd_send_setup cleanup when channel creation fails

On Thu, Aug 01, 2024 at 02:41:01PM -0300, Fabiano Rosas wrote: > When a channel fails to create, the code currently just returns. This > is wrong for two reasons: > > 1) Channel n+1 will not get to initialize it's semaphores, leading to >an assert when terminate_threads tries to post to it: >

Re: [PATCH 2/5] docs/interop/nbd.txt: Convert to rST

On Thu, Aug 01, 2024 at 06:01:28PM GMT, Peter Maydell wrote: > Convert nbd.txt to rST format. > > Signed-off-by: Peter Maydell > --- > MAINTAINERS| 2 +- > docs/interop/index.rst | 1 + > docs/interop/nbd.rst | 89 ++ > docs/interop/nbd.txt

[PATCH 6/6] qapi: expose all schema features to code

This removed the QapiFeatures enum and auto-generates an enum which exposes all features defined by the schema to code. The 'deprecated' and 'unstable' features still have a little bit of special handling, being force defined to be the 1st + 2nd features in the enum, regardless of whether they're

[PATCH 1/6] qapi: change 'unsigned special_features' to 'uint64_t features'

The "special_features" field / parameter holds the subset of schema features that are for internal code use. Specifically 'DEPRECATED' and 'UNSTABLE'. This special casing of internal features is going to be removed, so prepare for that by renaming to 'features'. Using a fixed size type is also bes

[PATCH 3/6] qapi: use "QAPI_FEATURE" as namespace for features

This more clearly distinguishes the feature constants from other QAPI constants. Signed-off-by: Daniel P. Berrangé --- include/qapi/util.h | 4 ++-- qapi/qapi-util.c | 4 ++-- qapi/qobject-output-visitor.c | 4 ++-- scripts/qapi/gen.py | 2 +- 4 files changed, 7

[PATCH 4/6] qapi: cope with feature names containing a '-'

When we shortly expose all feature names to code, it will be valid to include a '-', which must be translated to a '_' for the enum constants. Signed-off-by: Daniel P. Berrangé --- scripts/qapi/gen.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/qapi/gen.py b/scr

[PATCH 2/6] scripts/qapi: rename 'special_features' to 'features'

This updates the QAPI code generation to refer to 'features' instead of 'special_features', in preparation for generalizing their exposure. Signed-off-by: Daniel P. Berrangé --- scripts/qapi/commands.py | 4 ++-- scripts/qapi/gen.py | 8 scripts/qapi/types.py| 10 +-

[PATCH 5/6] qapi: apply schema prefix to QAPI feature enum constants

This allows us to include multiple QAPI schemas in the same file. Signed-off-by: Daniel P. Berrangé --- scripts/qapi/commands.py | 7 --- scripts/qapi/events.py | 3 ++- scripts/qapi/gen.py | 6 +++--- scripts/qapi/types.py| 5 +++-- scripts/qapi/visit.py| 5 +++-- 5 files cha

[PATCH 0/6] qapi: generalize special features

This series is a spin-off from https://lists.nongnu.org/archive/html/qemu-devel/2024-06/msg00807.html That series introduced a pragma allowing a schema to declare extra features that would be exposed to code. Following Markus' suggestion: https://lists.nongnu.org/archive/html/qemu-devel/202

[PATCH 0/2] Multifd fixes

Hi, a couple of multifd fixes to issues that Jim spotted while working on mapped-ram for libvirt. CI run: https://gitlab.com/farosas/qemu/-/pipelines/1397467740 Fabiano Rosas (2): migration: Fix cleanup of iochannel in file migration migration/multifd: Fix multifd_send_setup cleanup when chan

[PATCH 2/2] migration/multifd: Fix multifd_send_setup cleanup when channel creation fails

When a channel fails to create, the code currently just returns. This is wrong for two reasons: 1) Channel n+1 will not get to initialize it's semaphores, leading to an assert when terminate_threads tries to post to it: qemu-system-x86_64: ../util/qemu-thread-posix.c:92: qemu_mutex_lock_impl

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