Re: [PATCH 2/4] hw/misc/bcm2835_property: Avoid overflow in OTP access properties

On 24/7/24 14:31, Peter Maydell wrote: On Wed, 24 Jul 2024 at 08:06, Philippe Mathieu-Daudé wrote: Hi Peter, On 23/7/24 15:10, Peter Maydell wrote: Coverity points out that in our handling of the property RPI_FWREQ_SET_CUSTOMER_OTP we have a potential overflow. This happens because we read

Re: [PATCH v2 05/23] tests/functional: Convert simple avocado tests into standalone python tests

Hi Thomas, On 24/7/24 19:52, Thomas Huth wrote: These test are rather simple and don't need any modifications apart from adjusting the "from avocado_qemu" line. To ease debugging, make the files executable and add a shebang line and Python '__main__' handling, too, so that these tests can now be

Re: [PATCH v2 0/4] net: update netdev stream/dgram man page

On 04/07/2024 14:48, Laurent Vivier wrote: Add the description of "-netdev stream" and "-netdev dgram" in the QEMU manpage. Add some examples on how to use them, including a way to use "-netdev stream" and "passt" in place of "-netdev user". ("passt" is a non privileged translation proxy between

RE: [RFC PATCH] cxl: avoid duplicating report from MCE & device

Hello, everyone! > >>> 在 2024/6/22 1:51, Dan Williams 写道: > Shiyang Ruan wrote: > > Background: > > Since CXL device is a memory device, while CPU consumes a poison > page of > > CXL device, it always triggers a MCE by interrupt (INT18), no matter > > which-First path is confi

Re: [PATCH v3] target/s390x: filter deprecated properties based on model expansion type

Collin Walling writes: > On 7/24/24 3:56 AM, Markus Armbruster wrote: >> Collin Walling writes: > Let me try to explain the purpose of @deprecated-props and see if it > helps bring us closer to some semblance of a mutual understanding so we > can work together on a concise documentation for this

Re: [RFC PATCH v5 0/8] Add Rust support, implement ARM PL011

On Wed, 24 Jul 2024 13:34, Paolo Bonzini wrote: On Wed, Jul 24, 2024 at 11:58 AM Manos Pitsidianakis wrote: >In my opinion we should start with cargo workspaces as the >known-imperfect (but good enough) solution, so that it could be evolved >later. It is important that any change that deviate

Re: [RFC PATCH v5 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

On 7/17/24 23:39, Max Chou wrote: In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max

Re: [RFC PATCH v5 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

On 7/17/24 23:39, Max Chou wrote: +static inline QEMU_ALWAYS_INLINE void +vext_continus_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host, +void *vd, uint32_t evl, uint32_t reg_start, void *host, +uint32_t esz, bool is_load) +{ +#if TA

[PATCH] scripts/coccinelle: New range.cocci

This is the semantic patch from commit 7b3e371526 "cxl/mailbox: make range overlap check more readable" Signed-off-by: Yao Xingtao --- scripts/coccinelle/range.cocci | 49 ++ 1 file changed, 49 insertions(+) create mode 100644 scripts/coccinelle/range.cocci diff

Re: [PATCH] ptp: Add vDSO-style vmclock support

On Wed, Jul 24, 2024 at 06:16:37PM +0100, David Woodhouse wrote: > From: David Woodhouse > > The vmclock "device" provides a shared memory region with precision clock > information. By using shared memory, it is safe across Live Migration. > > Like the KVM PTP clock, this can convert TSC-based c

Re: [RFC PATCH v5 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

On 7/17/24 23:39, Max Chou wrote: @@ -199,7 +212,7 @@ static void vext_ldst_stride(void *vd, void *v0, target_ulong base, target_ulong stride, CPURISCVState *env, uint32_t desc, uint32_t vm, - vext_ldst_elem_fn *ldst_elem, +

Re: [PATCH] hw/acpi: Add vmclock device

On Wed, Jul 24, 2024 at 07:45:31PM +0100, David Woodhouse wrote: > On Wed, 2024-07-24 at 13:29 -0400, Michael S. Tsirkin wrote: > > > > Isn't the existing vmgenid sufficient for this disruption marker > > and if not, why? > > No, VMGENID handles snapshotting and cloning of virtual machines, but >

Re: [PATCH] ptp: Add vDSO-style vmclock support

On Wed, Jul 24, 2024 at 06:16:37PM +0100, David Woodhouse wrote: > From: David Woodhouse > > The vmclock "device" provides a shared memory region with precision clock > information. By using shared memory, it is safe across Live Migration. > > Like the KVM PTP clock, this can convert TSC-based c

Re: [PATCH v2 15/23] tests/functional: Convert the riscv_opensbi avocado test into a standalone test

On Thu, Jul 25, 2024 at 3:56 AM Thomas Huth wrote: > > The avocado test defined test functions for both, riscv32 and riscv64. > Since we can run the whole file with multiple targets in the new > framework, we can now consolidate the functions so we have to only > define one function per machine no

Re: [PATCH v5 13/13] docs/specs: add riscv-iommu

On Wed, Jul 24, 2024 at 10:56 PM Daniel Henrique Barboza wrote: > > > > On 7/19/24 6:34 AM, Alistair Francis wrote: > > On Tue, Jul 9, 2024 at 3:37 AM Daniel Henrique Barboza > > wrote: > >> > >> Add a simple guideline to use the existing RISC-V IOMMU support we just > >> added. > >> > >> This do

[PATCH v3] pci-bridge: avoid linking a single downstream port more than once

Since the downstream port is not checked, two slots can be linked to a single port. However, this can prevent the driver from detecting the device properly. It is necessary to ensure that a downstream port is not linked more than once. Links: https://lore.kernel.org/qemu-devel/oszpr01mb6453bc61d

[PATCH] intel_iommu: Fix for IQA reg read dropped DW field

From: yeeli If VT-D hardware supports scalable mode, Linux will set the IQA DW field (bit11). In qemu, the vtd_mem_write and vtd_update_iq_dw set DW field well. However, vtd_mem_read the DW field wrong because "& VTD_IQA_QS" dropped the value of DW. Replace "&VTD_IQA_QS" with "& (VTD_IQA_QS | VTD

Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

On 7/24/24 16:32, LIU Zhiwei wrote: However!  It does explicitly say "no more than MXLEN bits", which means that an RV32/ RV64 check is appropriate for FLD/FSD, since MXLEN may be less than 64. Yes.  That's true. Although I don't know why MXLEN is needed as F, D or Q don't depend on MXLEN. We ca

Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU

On 2024/7/24 23:01, Andrew Jones wrote: On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote: We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add these two CPUs for RV64 QEMU. The reason we don't expose them to RV32 QEMU is that we already have max or any cpu with the same

Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b

On 2024/7/23 13:59, Richard Henderson wrote: On 7/23/24 15:29, LIU Zhiwei wrote: The more detailed information about its meaning is in priviledged 1.13 specification. More exactly, in 3.6.4. Misaligned Atomicity Granule PMA. The specification said: "The misaligned atomicity granule PMA app

Re: [PULL 00/15] Bsd user for 9.1 patches

On 7/25/24 08:04, Warner Losh wrote: The following changes since commit 3cce8bd4d737f2ca688bbdcb92cd5cc683245bbd: Merge tag 'ui-pull-request' ofhttps://gitlab.com/marcandre.lureau/qemu into staging (2024-07-23 15:23:05 +1000) are available in the Git repository at: g...@gitlab.com:bsdim

Re: [PULL 00/11] Crypto patches

On 7/24/24 19:46, Daniel P. Berrangé wrote: The following changes since commit 6410f877f5ed535acd01bbfaa4baec379e44d0ef: Merge tag 'hw-misc-20240723' ofhttps://github.com/philmd/qemu into staging (2024-07-24 15:39:43 +1000) are available in the Git repository at: https://gitlab.com/berr

Re: [PATCH v2 00/23] Convert avocado tests to normal Python unittests

On 7/25/24 03:52, Thomas Huth wrote: The Avocado v88 that we use in QEMU is already on a life support system: It is not supported by upstream anymore, and with the latest versions of Python, it won't work anymore since it depends on the "imp" module that has been removed in Python 3.12. There ha

[PULL 15/15] bsd-user: Add target.h for aarch64.

For aarch64, it's a 64-bit API, so there's no pairing of registers for 64-bit values. Signed-off-by: Warner Losh --- bsd-user/aarch64/target.h | 20 1 file changed, 20 insertions(+) create mode 100644 bsd-user/aarch64/target.h diff --git a/bsd-user/aarch64/target.h b/bsd-u

[PULL 04/15] bsd-user:Add ARM AArch64 signal handling support

From: Stacey Son Added sigcode setup function for signal trampoline which initializes a sequence of instructions to handle signal returns and exits, copying this code to the target offset. Defined ARM AArch64 specific signal definitions including register indices and sizes, and introduced struc

[PULL 02/15] bsd-user:Add AArch64 register handling and related functions

From: Stacey Son Added header file for managing CPU register states in FreeBSD user mode. Introduced prototypes for setting and getting thread-local storage (TLS). Implemented AArch64 sysarch() system call emulation and a printing function. Added function for setting up thread upcall to add threa

[PULL 03/15] bsd-user:Add ARM AArch64 support and capabilities

Added function to access rval2 by accessing the x1 register. Defined ARM AArch64 ELF parameters including mmap and dynamic load addresses. Introduced extensive hardware capability definitions and macros for retrieving hardware capability (hwcap) flags. Implemented function to retrieve ARM AArch64

[PULL 13/15] bsd-user: Make compile for non-linux user-mode stuff

We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use them unconditionally. Restrict its use to Linux-only. "It's ugly, but it's not actually wrong." Signed-off-by: Warner Losh Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/gdbstub64.c | 4

[PULL 00/15] Bsd user for 9.1 patches

The following changes since commit 3cce8bd4d737f2ca688bbdcb92cd5cc683245bbd: Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2024-07-23 15:23:05 +1000) are available in the Git repository at: g...@gitlab.com:bsdimp/qemu.git tags/bsd-user-for-9.1-pull-re

[PULL 12/15] bsd-user: Define TARGET_SIGSTACK_ALIGN and use it to round stack

Most (all?) targets require stacks to be properly aligned. Rather than a series of ifdefs in bsd-user/signal.h, instead use a manditory #define for all architectures. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/aarch64/target_arch_signal.h | 2 ++ bsd-user/arm/target_

[PULL 10/15] bsd-user: Hard wire aarch64 to be 4k pages only

Only support 4k pages for aarch64 binaries. The variable page size stuff isn't working just yet, so put in this lessor-of-evils kludge until that is complete. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- target/arm/cpu-param.h | 4 1 file changed, 4 insertions(+) diff --g

[PULL 08/15] bsd-user:Add AArch64 improvements and signal handling functions

From: Stacey Son Added get_ucontext_sigreturn function to check processor state ensuring current execution mode is EL0 and no flags indicating interrupts or exceptions are set. Updated AArch64 code to use CF directly without reading/writing the entire processor state, improving efficiency. Chan

[PULL 01/15] bsd-user:Add CPU initialization and management functions

From: Stacey Son Added function to initialize ARM CPU and check if it supports 64-bit mode. Implemented CPU loop function to handle exceptions and emulate execution of instructions. Added function to clone CPU state to create a new thread. Included AArch64 specific CPU functions for bsd-user to

[PULL 05/15] bsd-user:Add get_mcontext function for ARM AArch64

From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans Reviewed-by: Richard Henderson Message-Id: <20240707191

[PULL 07/15] bsd-user:Add set_mcontext function for ARM AArch64

From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers. Note:FP is unfinished upstream but will be a separate commit coming soon. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Messag

[PULL 06/15] bsd-user:Add setup_sigframe_arch function for ARM AArch64

The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Reviewed-by: Richard Henderson Message-Id: <20240707191128.10509-7-itac...@freebsd.org> Signed-off-by: Warner Losh --- bsd-user/a

[PULL 14/15] bsd-user: Add aarch64 build to tree

Add the aarch64 bsd-user fragments needed to build the new aarch64 code. Signed-off-by: Warner Losh Reviewed-by: Richard Henderson --- configs/targets/aarch64-bsd-user.mak | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 configs/targets/aarch64-bsd-user.mak diff --git a/configs/tar

[PULL 11/15] bsd-user: Sync fork_start/fork_end with linux-user

From: Jessica Clarke This reorders some of the calls, deduplicates code between branches and, most importantly, fixes a double end_exclusive call in the parent that will cause exclusive_context_count to go negative. Signed-off-by: Jessica Clarke Pull-Request: https://github.com/qemu-bsd-user/qe

[PULL 09/15] bsd-user: Simplify the implementation of execve

From: Doug Rabson This removes the logic which prepends the emulator to each call to execve and fexecve. This is not necessary with the existing imgact_binmisc support and it avoids the need to install the emulator binary into jail environments when using 'binmiscctl --pre-open'. Signed-off-by:

Re: [PATCH] gitlab-ci: Use -fno-sanitize=function in the clang-user job

On 7/24/24 20:52, Daniel P. Berrangé wrote: On Wed, Jul 24, 2024 at 09:25:42AM +1000, Richard Henderson wrote: With -fsanitize=undefined, which implies -fsanitize=function, clang will add a "type signature" before functions. It accesses funcptr-8 and funcptr-4 to do so. The generated TCG prolog

Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device

On 7/18/24 4:06 AM, Jason Chien wrote: Hi Daniel, On 2024/7/9 上午 01:34, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

On 7/25/24 05:00, Daniel Henrique Barboza wrote: I'm not sure about which generic functions we're supposed to use in replace of get_field/set_field, at least as far as bitops.h goes. extract64/deposit64 has a different API (it uses start bit + length, not a mask) and it would require a lot of RIS

[PATCH v4 11/11] pnv/xive2: Dump more END state with 'info pic'

From: Frederic Barrat Additional END state 'info pic' information as added. The 'ignore', 'crowd' and 'precluded escalation control' bits of an Event Notification Descriptor are all used when delivering an interrupt targeting a VP-group or crowd. Signed-off-by: Frederic Barrat Signed-off-by: M

[PATCH v4 08/11] pnv/xive2: Fail VST entry address computation if table has no VSD

From: Frederic Barrat Fail VST entry address computation if firmware doesn't define a descriptor for one of the Virtualization Structure Tables (VST), there's no point in trying to compute the address of its entry. Abort the operation and log an error. Signed-off-by: Frederic Barrat Signed-off

[PATCH v4 05/11] pnv/xive2: Configure Virtualization Structure Tables through the PC

From: Frederic Barrat Both the virtualization layer (VC) and presentation layer (PC) need to be configured to access the VSTs. Since the information is redundant, the xive model combines both into one set of tables and only the definitions going through the VC are kept. The definitions through th

[PATCH v4 10/11] pnv/xive2: Refine TIMA 'info pic' output

From: Frederic Barrat In XIVE Gen 2 there were some minor changes to the TIMA header that were updated when printed. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- hw/intc/xive.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/intc/xive.c b

[PATCH v4 06/11] pnv/xive2: Enable VST NVG and NVC index compression

From: Frederic Barrat Enable NVG and NVC VST tables for index compression which indicates the number of bits the address is shifted to the right for the table accesses. The compression values are defined as: - No compression 0001 - 1 bit shift 0010 - 2 bit shift 1000 - 8

[PATCH v4 00/11] XIVE changes for Cache Watch, VSTs, STT and info pic

From: Michael Kowal These changes provide enhanced support of the External Interrupt Virtualization Engine. The changes are focused on the following areas: - Cache Watch, Cache Flush and Sync Injection - Virtual Structure Tables - Set Translation Table - 'info pic' command data that is dumpe

[PATCH v4 01/11] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support

From: Frederic Barrat XIVE offers a 'cache watch facility', which allows software to read/update a potentially cached table entry with no software lock. There's one such facility in the Virtualization Controller (VC) to update the ESB and END entries and one in the Presentation Controller (PC) to

[PATCH v4 09/11] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c

From: Frederic Barrat Moving xive2_nvp_pic_print_info() to align with the other "pic_print_info" functions. Signed-off-by: Frederic Barrat Signed-off-by: Michael Kowal --- include/hw/ppc/xive2_regs.h | 2 ++ hw/intc/pnv_xive2.c | 27 --- hw/intc/xive2.c

[PATCH v4 07/11] pnv/xive2: Set Translation Table for the NVC port space

From: Frederic Barrat Set Translation Table for the NVC port space is missing. The xive model doesn't take into account the remapping of IO operations via the Set Translation Table but firmware is allowed to define it for the Notify Virtual Crowd (NVC), like it's already done for the other VST t

[PATCH v4 04/11] pnv/xive2: Add NVG and NVC to cache watch facility

From: Frederic Barrat The cache watch facility uses the same register interface to handle entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX specification' register tells the table type. So far, that bit-field was not read and the code assumed a read/write to the NVP table. This

[PATCH v4 03/11] pnv/xive: Support cache flush and queue sync inject with notifications

From: Nicholas Piggin Adds support for writing a completion notification byte in memory whenever a cache flush or queue sync inject operation is requested by software. QEMU does not cache any of the XIVE data that is in memory and therefore it simply writes the completion notification byte at th

[PATCH v4 02/11] pnv/xive2: Structure/define alignment changes

From: Michael Kowal Made changes to some structure and define elements to ease review in next patchset. Signed-off-by: Michael Kowal Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/in

Re: [PULL 00/14] Bsd user for 9.1 patches

On Wed, Jul 24, 2024 at 2:55 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 7/24/24 04:07, Warner Losh wrote: > > The following changes since commit > 3cce8bd4d737f2ca688bbdcb92cd5cc683245bbd: > > > >Merge tag 'ui-pull-request' ofhttps:// > gitlab.com/marcandre.lureau/qemu in

[PATCH v7 3/6] tests/tcg: add mechanism to run specific tests with plugins

Only multiarch tests are run with plugins, and we want to be able to run per-arch test with plugins too. Tested-by: Xingtao Yao Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- tests/tcg/Makefile.target | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tes

[PATCH v7 5/6] tests/plugin/mem: add option to print memory accesses

By using "print-accesses=true" option, mem plugin will now print every value accessed, with associated size, type (store vs load), symbol, instruction address and phys/virt address accessed. Reviewed-by: Richard Henderson Reviewed-by: Xingtao Yao Signed-off-by: Pierrick Bouvier --- tests/plugi

[PATCH v7 1/6] plugins: save value during memory accesses

Different code paths handle memory accesses: - tcg generated code - load/store helpers - atomic helpers This value is saved in cpu->neg.plugin_mem_value_{high,low}. Values are written only for accessed word size (upper bits are not set). Atomic operations are doing read/write at the same time, so

[PATCH v7 4/6] tests/tcg: allow to check output of plugins

A specific plugin test can now read and check a plugin output, to ensure it contains expected values. Tested-by: Xingtao Yao Reviewed-by: Richard Henderson Signed-off-by: Pierrick Bouvier --- tests/tcg/Makefile.target | 9 + 1 file changed, 9 insertions(+) diff --git a/tests/tcg/Makef

[PATCH v7 0/6] plugins: access values during a memory read/write

This series allows plugins to know which value is read/written during a memory access. For every memory access, we know copy this value before calling mem callbacks, and those can query it using new API function: - qemu_plugin_mem_get_value Mem plugin was extended to print accesses, and a new tes

[PATCH v7 6/6] tests/tcg/multiarch: add test for plugin memory access

Add an explicit test to check expected memory values are read/written. 8,16,32 load/store are tested for all arch. 64,128 load/store are tested for aarch64/x64. atomic operations (8,16,32,64) are tested for x64 only. By default, atomic accesses are non atomic if a single cpu is running, so we forc

[PATCH v7 2/6] plugins: extend API to get latest memory value accessed

This value can be accessed only during a memory callback, using new qemu_plugin_mem_get_value function. Returned value can be extended when QEMU will support accesses wider than 128 bits. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1719 Resolves: https://gitlab.com/qemu-project/qemu/-

Re: [PATCH v3] target/s390x: filter deprecated properties based on model expansion type

On 7/24/24 3:56 AM, Markus Armbruster wrote: > Collin Walling writes: > >> On 7/20/24 1:33 AM, Markus Armbruster wrote: >>> Collin Walling writes: >>> Currently, there is no way to execute the query-cpu-model-expansion command to retrieve a comprehenisve list of deprecated properties,

Re: [PATCH v3 0/2] Consolidate create-sync and create-fence

Hey Marc-André, On 7/24/2024 3:37 AM, Marc-André Lureau wrote: Hi On Wed, Jul 24, 2024 at 2:05 AM > wrote: From: Dongwon Kim mailto:dongwon@intel.com>> Sync object itself is never used as is so can be removed from QemuDmaBuf struct. So now sync i

Re: [PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

On 7/22/24 8:33 PM, Atish Kumar Patra wrote: On Sat, Jul 20, 2024 at 8:19 AM Peter Maydell wrote: On Thu, 18 Jul 2024 at 03:15, Alistair Francis wrote: From: Atish Patra The timer is setup function is invoked in both hpmcounter write and mcountinhibit write path. If the OF bit set, the

Re: [PATCH] hw/acpi: Add vmclock device

On Wed, 2024-07-24 at 13:29 -0400, Michael S. Tsirkin wrote: > > Isn't the existing vmgenid sufficient for this disruption marker > and if not, why? No, VMGENID handles snapshotting and cloning of virtual machines, but it explicitly *doesn't* change on live migration. smime.p7s Description: S/M

Re: [PATCH v6 7/8] target/riscv: Add any32 and max32 CPU for RV64 QEMU

On Sat, 20 Jul 2024 at 00:18, LIU Zhiwei wrote: > > We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add > these two CPUs for RV64 QEMU. > > The reason we don't expose them to RV32 QEMU is that we already have > max or any cpu with the same configuration. Another reason is that > we

[PATCH v2 22/23] tests/functional: Convert the rx_gdbsim avocado test into a standalone test

Provide a "gzip_uncompress" function based on the standard "gzip" module to avoid the usage of avocado.utils here. Signed-off-by: Thomas Huth --- Note: Make sure to apply this fix first before running this test: https://lore.kernel.org/qemu-devel/20240724045659.160684-1-richard.hender...@linar

[PATCH v2 03/23] tests/Makefile.include: Increase the level of indentation in the help text

The next patch is going to add some entries that need more space between the command and the help text, so let's increase the indentation here first. Signed-off-by: Thomas Huth --- tests/Makefile.include | 30 +++--- 1 file changed, 15 insertions(+), 15 deletions(-) diff

[PATCH v2 18/23] tests/functional: Convert the ppc_amiga avocado test into a standalone test

Use the Python standard zipfile module instead of avocado.utils for extracting the ZIP file that we download here, and use the standard subprocess module for running the "tail" command. Signed-off-by: Thomas Huth --- tests/functional/meson.build | 1 + .../test_ppc_amiga.py}

[PATCH v2 09/23] tests/functional: Add a function for extracting files from an archive

Some Avocado-based tests use the "archive" module from avocado.utils to extract files from an archive. To be able to use these tests without Avocado, we have to provide our own function for extracting files. Fortunately, there is already the tarfile module that will provide us with this functionali

[PATCH v2 17/23] tests/functional: Convert most ppc avocado tests into standalone tests

Nothing thrilling in here, just straight forward conversions. Signed-off-by: Thomas Huth --- MAINTAINERS | 8 ++-- tests/functional/meson.build | 10 + .../test_ppc64_powernv.py}| 45 +-- .../test_ppc64_p

[PATCH v2 23/23] gitlab-ci: Add "check-functional" to the build tests

Now that we converted many tests from the "check-avocado" test suite to the "check-functional" test suite, we should make sure that these also get tested in the CI. Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- TODO: We should also make sure of cachine the downloaded assets her

[PATCH v2 12/23] tests/functional: Convert the s390x avocado tests into standalone tests

These tests use archive.lzma_uncompress() from the Avocado utils, so provide a small helper function for this, based on the standard lzma module from Python instead. And while we're at it, replace the MD5 hashes in the topology test with proper SHA256 hashes, since MD5 should not be used anymore n

[PATCH v2 16/23] tests/functional: Convert the virtio_gpu avocado test into a standalone test

Nothing thrilling in here, it's just a straight forward conversion. Signed-off-by: Thomas Huth --- tests/functional/meson.build | 1 + .../test_virtio_gpu.py} | 34 --- 2 files changed, 16 insertions(+), 19 deletions(-) rename tests/{avoca

[PATCH v2 19/23] tests/functional: Convert the ppc_hv avocado test into a standalone test

Note: The original Avocado test seems currently to be broken, it hangs when the guest is trying to install additional packages. So mark it as broken for now until it gets fixed. Signed-off-by: Thomas Huth --- .../test_ppc64_hv.py} | 36 --- 1 file changed,

[PATCH v2 10/23] tests/functional: Convert some avocado tests that needed avocado.utils.archive

Instead of using the "archive" module from avocado.utils, switch these tests to use the new wrapper function that is based on the "tarfile" module instead. Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- MAINTAINERS | 6 ++--- tests/functional/m

[PATCH v2 15/23] tests/functional: Convert the riscv_opensbi avocado test into a standalone test

The avocado test defined test functions for both, riscv32 and riscv64. Since we can run the whole file with multiple targets in the new framework, we can now consolidate the functions so we have to only define one function per machine now. Signed-off-by: Thomas Huth --- tests/avocado/riscv_opens

[PATCH v2 20/23] tests/functional: Convert the m68k nextcube test with tesseract

The code that handles running of tesseract needs to be tweaked a little bit to be able to run without the functions from avocado.utils, and while we're at it, drop some legacy stuff that was still there due to Tesseract 3 support that we already dropped a while ago. Signed-off-by: Thomas Huth ---

[PATCH v2 13/23] tests/functional: Convert the x86_cpu_model_versions test

Nothing thrilling in here, it's just a straight forward conversion. Signed-off-by: Thomas Huth --- tests/functional/meson.build | 1 + .../test_x86_cpu_model_versions.py} | 63 ++- 2 files changed, 20 insertions(+), 44 deletions(-) rename tests/{avoca

[PATCH v2 21/23] tests/functional: Convert the acpi-bits test into a standalone test

Mostly a straight-forward conversion. Looks like we can simply drop the avocado datadrainer stuff when not using the avocado framework anymore. Signed-off-by: Thomas Huth --- .../acpi-bits/bits-config/bits-cfg.txt| 0 .../acpi-bits/bits-tests/smbios.py2 | 0 .../acpi-bits/bit

[PATCH v2 07/23] tests/functional: Implement fetch_asset() method for downloading assets

In the new python test framework, we cannot use the fetch_asset() function from Avocado anymore, so we have to provide our own implementation now instead. Thus add such a function based on the urllib python module for this purpose. Signed-off-by: Thomas Huth --- tests/functional/qemu_test/__init

[PATCH v2 14/23] tests/functional: Convert the microblaze avocado tests into standalone tests

The machine_microblaze.py file contained two tests, one for each endianess. Since we only support one QEMU target binary per file in the new functional test environment, we have to split this file up into two files now. Signed-off-by: Thomas Huth --- MAINTAINERS

[PATCH v2 11/23] tests/functional: Set up logging

Create log files for each test separately, one file that contains the basic logging and one that contains the console output. Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- tests/functional/qemu_test/__init__.py | 26 +- 1 file changed, 25 insertions(+),

[PATCH v2 08/23] tests/functional: Convert some tests that download files via fetch_asset()

Now that we've got a working fetch_asset() function, we can convert some Avocado tests that use this function for downloading their required files. Reviewed-by: Daniel P. Berrangé Signed-off-by: Thomas Huth --- MAINTAINERS | 12 +++ tests/functional/meson.b

[PATCH v2 05/23] tests/functional: Convert simple avocado tests into standalone python tests

These test are rather simple and don't need any modifications apart from adjusting the "from avocado_qemu" line. To ease debugging, make the files executable and add a shebang line and Python '__main__' handling, too, so that these tests can now be run by executing them directly. Reviewed-by: Dani

[PATCH v2 06/23] tests/functional: Convert avocado tests that just need a small adjustment

These simple tests can be converted to stand-alone tests quite easily, e.g. by just setting the machine to 'none' now manually or by adding "-cpu" command line parameters, since we don't support the corresponding avocado tags in the new python test framework. Reviewed-by: Daniel P. Berrangé Signe

[PATCH v2 02/23] tests/functional: Add base classes for the upcoming pytest-based tests

The file is mostly a copy of the tests/avocado/avocado_qemu/__init__.py file with some adjustments to get rid of the Avocado dependencies (i.e. we also have to drop the LinuxSSHMixIn and LinuxTest for now). The emulator binary and build directory are now passed via environment variables that will

[PATCH v2 01/23] python: Install pycotap in our venv if necessary

The upcoming functional tests will require pycotap for providing TAP output from the python-based tests. Since we want to be able to run some of the tests offline by default, too, let's install it along with meson in our venv if necessary (it's size is only 5 kB, so adding the wheel here should not

[PATCH v2 00/23] Convert avocado tests to normal Python unittests

The Avocado v88 that we use in QEMU is already on a life support system: It is not supported by upstream anymore, and with the latest versions of Python, it won't work anymore since it depends on the "imp" module that has been removed in Python 3.12. There have been several attempts to update the

[PATCH v2 04/23] tests/functional: Prepare the meson build system for the functional tests

Provide a meson.build file for the upcoming python-based functional tests, and add some wrapper glue targets to the tests/Makefile.include file. We are going to use two "speed" modes for the functional tests: The "quick" tests can be run at any time (i.e. also during "make check"), while the "thoro

Re: [PATCH v4 13/17] backends/confidential-guest-support: Add set_guest_policy() function

On Wed, Jul 03, 2024 at 12:05:51PM +0100, Roy Hopkins wrote: > For confidential guests a policy can be provided that defines the > security level, debug status, expected launch measurement and other > parameters that define the configuration of the confidential platform. > > This commit adds a new

Re: [PATCH] hw/acpi: Add vmclock device

On Wed, Jul 24, 2024 at 06:22:42PM +0100, David Woodhouse wrote: > From: David Woodhouse > > The vmclock device addresses the problem of live migration with > precision clocks. The tolerances of a hardware counter (e.g. TSC) are > typically around ±50PPM. A guest will use NTP/PTP/PPS to disciplin

Re: [PATCH v4 12/17] docs/interop/firmware.json: Add igvm to FirmwareDevice

On Wed, Jul 03, 2024 at 12:05:50PM +0100, Roy Hopkins wrote: > Create an enum entry within FirmwareDevice for 'igvm' to describe that > an IGVM file can be used to map firmware into memory as an alternative > to pre-existing firmware devices. > > Signed-off-by: Roy Hopkins > --- > docs/interop/f

Re: [PATCH v4 11/17] docs/system: Add documentation on support for IGVM

On Wed, Jul 03, 2024 at 12:05:49PM +0100, Roy Hopkins wrote: > IGVM support has been implemented for Confidential Guests that support > AMD SEV and AMD SEV-ES. Add some documentation that gives some > background on the IGVM format and how to use it to configure a > confidential guest. > > Signed-o

[PATCH] hw/acpi: Add vmclock device

From: David Woodhouse The vmclock device addresses the problem of live migration with precision clocks. The tolerances of a hardware counter (e.g. TSC) are typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that counter against an external source of 'real' time, and track the pre

Re: [PATCH v4 07/17] sev: Update launch_update_data functions to use Error handling

On Wed, Jul 03, 2024 at 12:05:45PM +0100, Roy Hopkins wrote: > The class function and implementations for updating launch data return > a code in case of error. In some cases an error message is generated and > in other cases, just the error return value is used. > > This small refactor adds an 'E

Re: [PATCH v4 06/17] sev: Fix error handling in sev_encrypt_flash()

On Wed, Jul 03, 2024 at 12:05:44PM +0100, Roy Hopkins wrote: > The function sev_encrypt_flash() checks to see if the return value of > launch_update_data() < 0, but the function returns a non-zero (and not > necessarily negative) result on error. This means that some errors in > updating launch dat

[PATCH] ptp: Add vDSO-style vmclock support

From: David Woodhouse The vmclock "device" provides a shared memory region with precision clock information. By using shared memory, it is safe across Live Migration. Like the KVM PTP clock, this can convert TSC-based cross timestamps into KVM clock values. Unlike the KVM PTP clock, it does so o

Re: [PATCH v4 05/17] i386/pc_sysfw: Ensure sysfw flash configuration does not conflict with IGVM

On Wed, Jul 03, 2024 at 12:05:43PM +0100, Roy Hopkins wrote: > When using an IGVM file the configuration of the system firmware is > defined by IGVM directives contained in the file. In this case the user > should not configure any pflash devices. > > This commit skips initialization of the ROM mo

  1   2   >