On 23/7/24 18:25, Peter Maydell wrote:
Coverity points out that in do_interrupt64() in the "to inner
privilege" codepath we set "ss = 0", but because we also set
"new_stack = 1" there, later in the function we will always override
that value of ss with "ss = 0 | dpl".
Remove the unnecessary init
On 24/7/24 03:07, Richard Henderson wrote:
Add the --noexecstack assembler command-line option to avoid:
/usr/bin/ld: warning: boot.o: missing .note.GNU-stack section implies
executable stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in a
future version of the l
Hi Nick,
On 23/07/24 10:52, Nicholas Piggin wrote:
<...snip...>
+PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05
+#define POWERPC_POWER10_PCC_PCR_SUPPORTED \
+POWERPC_POWER9_PCC_PCR_SUPPORTED | PCR_COMPAT_3_10
+#define POWERPC_POWER9_PCC_LPCR_MASK
> So you found it by checking the debugfs output, and it looks to miss
> the DW bit. is it? Put a clearer commit message would be helpful.
Yes, it is. So, "dropped the value of DW field" is indeed a bug?
> Please address Michael's comment, add a "Fixes: xxx" tag and resend.
OK, I will.
On 2024/7/23 13:59, Richard Henderson wrote:
On 7/23/24 15:29, LIU Zhiwei wrote:
The more detailed information about its meaning is in priviledged
1.13 specification. More exactly, in 3.6.4. Misaligned Atomicity
Granule PMA.
The specification said:
"The misaligned atomicity granule PMA app
On 24/07/2024 06.56, Richard Henderson wrote:
Using int32_t meant that the address was sign-extended to uint64_t
when passing to translator_ld*, triggering an assert.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2453
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 3 ++
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 17/17] tests/qtest: Add intel-iommu test
>
>
>
>On 18/07/2024 10:16, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unless this
>email comes from a known sender and you kno
On 24/07/2024 08:07, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>> Subject: Re: [PATCH v1 14/17] intel_
On 24/07/2024 01.25, Richard Henderson wrote:
With -fsanitize=undefined, which implies -fsanitize=function,
clang will add a "type signature" before functions.
It accesses funcptr-8 and funcptr-4 to do so.
The generated TCG prologue is directly on a page boundary,
so these accesses segfault.
Si
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 14/17] intel_iommu: piotlb invalidation should
>notify unmap
>
>
>
>On 24/07/2024 07:45, CLEMENT MATHIEU--DRIF wrote:
>> Maybe I'm missing something but why do we invalidate device IOTLB
>> upon piotlb receipt of a
On 24/07/2024 07:45, CLEMENT MATHIEU--DRIF wrote:
> Maybe I'm missing something but why do we invalidate device IOTLB
> upon piotlb receipt of a regular IOTLB inv desc?
> I don't get why we don't wait for a device IOTLB inv desc?
I thought you were planning to remove that after the last rfc versi
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> Add the framework to test the intel-iommu device.
>
> Currently only tested cap/ecap bits correctnes
Maybe I'm missing something but why do we invalidate device IOTLB
upon piotlb receipt of a regular IOTLB inv desc?
I don't get why we don't wait for a device IOTLB inv desc?
On 18/07/2024 10:16, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this
>
https://github.com/legoater/qemu/ tags/pull-vfio-20240723-1
for you to fetch changes up to 30b9167785177ac43d11b881fe321918124aeb88:
vfio/common: Allow disabling device dirty page tracking (2024-07-23 17:14:53
+0200)
Changes in v2:
- Rebased
- Fixed bogus email in "vfio/iom
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-
>selective PASID-based iotlb invalidation
>
>
>
>On 24/07/2024 04:59, Duan, Zhenzhong wrote:
>> Caution: External email. Do not open attachments or click links, unle
On 24/07/2024 04:59, Duan, Zhenzhong wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
>> -Original Message-
>> From: CLEMENT MATHIEU--DRIF
>> Subject: Re: [PATCH v1 04/17] intel_
Using int32_t meant that the address was sign-extended to uint64_t
when passing to translator_ld*, triggering an assert.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2453
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
05.07.2024 14:39, Jonathan Cameron via wrote:
From: Zhao Liu
QEMU crashes (Segmentation fault) when getting cxl-fmw property via
qmp:
(QEMU) qom-get path=machine property=cxl-fmw
This issue is caused by accessing wrong callback (opaque) type in
machine_get_cfmw().
cxl_machine_init() sets the
22.07.2024 12:52, songziming wrote:
If I use `-serial stdio` on Windows, after QEMU exits, the terminal
could not handle arrow keys and tab any more. Because stdio backend
on Windows sets console mode to virtual terminal input when starts,
but does not restore the old mode when finalize.
This sm
23.07.2024 13:56, Michael S. Tsirkin wrote:
From: Clément Mathieu--Drif
The constant must be unsigned, otherwise the two's complement
overrides the other fields when a PASID is present.
Fixes: 1b2b12376c8a ("intel-iommu: PASID support")
Signed-off-by: Clément Mathieu--Drif
Reviewed-by: Yi Liu
Hi Aditya,
On 7/23/24 20:43, Aditya Gupta wrote:
Hi Harsh,
Is it okay if I do, the changes in your patch ?
Sure, feel free to update as suggested and add your sob mentioning the
summary of updates.
Thanks
Harsh
Thanks,
Aditya Gupta
On 23/07/24 10:52, Nicholas Piggin wrote:
On Thu
Hi Don.
In addition to the other issues, this really needs to be broken up into many
more patches.
Every patch should do *one* thing:
- Code motion
- Introduce an API
- Introduce target-specific support for an API
- Use an API to implement a monitor command
- etc
Patch 3, 'Add an "i
On 7/23/24 11:05, Don Porter wrote:
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d946161717..c70d31433d 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -605,10 +605,11 @@ extern bool mttcg_enabled;
/**
* cpu_paging_enabled:
* @cpu: The CPU whose state
On 7/23/24 11:05, Don Porter wrote:
Signed-off-by: Don Porter
---
target/i386/kvm/vmcs12.h | 213 +++
1 file changed, 213 insertions(+)
create mode 100644 target/i386/kvm/vmcs12.h
I don't think you actually need this.
I'll comment on that vs patch 3.
On 7/23/24 11:05, Don Porter wrote:
Signed-off-by: Don Porter
---
include/hw/core/sysemu-cpu-ops.h | 6 +
target/i386/cpu.h| 5 ++--
target/i386/helper.c | 36 +++
target/i386/tcg/helper-tcg.h | 32 +++
On Fri, Jul 12, 2024 at 1:32 PM ~liuxu wrote:
>
> From: lxx <1733205...@qq.com>
>
> This patch adds support for the Zilsd and Zcmlsd extension,
> which is documented at
> https://github.com/riscv/riscv-zilsd/releases/tag/v0.9.0
>
> Co-developed-by: SUN Dongya
> Co-developed-by: LIU Xu
> Co-deve
On Wed, 24 Jul 2024 02:24:31 +0900,
Peter Maydell wrote:
>
> In update_itlb_use() the variables or_mask and and_mask are uint8_t,
> which means that in expressions like "and_mask << 24" the usual C
> arithmetic conversions will result in the shift being done as a
> signed int type, and so we will
On 7/24/24 11:58, Song Gao wrote:
When the lddir level is 4 and the base is a HugePage, we may try to put value 4
into a field in the TLBENTRY that is only 2 bits wide.
Fixes: Coverity CID 1547717
Fixes: 9c70db9a43388 ("target/loongarch: Fix tlb huge page loading issue")
Signed-off-by: Song Gao
>-Original Message-
>From: CLEMENT MATHIEU--DRIF
>Subject: Re: [PATCH v1 04/17] intel_iommu: Flush stage-2 cache in PADID-
>selective PASID-based iotlb invalidation
>
>
>
>On 18/07/2024 10:16, Zhenzhong Duan wrote:
>> Caution: External email. Do not open attachments or click links, unles
On 7/24/24 00:15, Paolo Bonzini wrote:
The following changes since commit a7ddb48bd1363c8bcdf42776d320289c42191f01:
Merge tag 'pull-aspeed-20240721' ofhttps://github.com/legoater/qemu into
staging (2024-07-22 07:52:05 +1000)
are available in the Git repository at:
https://gitlab.com/bon
On Sat, Jul 20, 2024 at 9:15 AM LIU Zhiwei wrote:
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado tuxrun test in tests/avocado.
>
> v6:
> U
Added loongarch UEFI BIOS support to compiled scripts.
UEFI code images require 16M alignment, flash images require
16M alignment, under the loongarch architecture.This is agreed
upon when the firmware is loaded in QEMU under Loongarch.
The naming of UEFI under loongarch refers to the x86 and
On Sun, Jul 21, 2024 at 5:26 PM Alvin Chang via wrote:
>
> According to RISC-V Debug specification, the optional textra32 and textra64
> trigger CSRs can be used to configure additional matching conditions for the
> triggers.
>
> This series support to write MHVALUE and MHSELECT fields into textra
When the lddir level is 4 and the base is a HugePage, we may try to put value 4
into a field in the TLBENTRY that is only 2 bits wide.
Fixes: Coverity CID 1547717
Fixes: 9c70db9a43388 ("target/loongarch: Fix tlb huge page loading issue")
Signed-off-by: Song Gao
---
target/loongarch/tcg/tlb_helpe
Dear Maintainers and Paolo,
I hope this message finds you well. I am writing to inquire about the
status of
the patch I submitted a month ago. Could you please provide any updates or
addtional comments regarding its review?
Thank you for your time and assistance.
Best regards,
Ewan
On 6/25/2
* Don Porter (por...@cs.unc.edu) wrote:
> Signed-off-by: Don Porter
> ---
> target/i386/kvm/vmcs12.h | 213 +++
> 1 file changed, 213 insertions(+)
> create mode 100644 target/i386/kvm/vmcs12.h
>
> diff --git a/target/i386/kvm/vmcs12.h b/target/i386/kvm/vmcs1
On Wed, Jul 24, 2024 at 08:25:12AM +0800, Xiaoyao Li wrote:
> Date: Wed, 24 Jul 2024 08:25:12 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH] target/i386: Always set leaf 0x1f
>
> On 7/23/2024 10:26 PM, Zhao Liu wrote:
> > (+Xiaoyao, whose TDX work may also be related with this.)
>
> I have a si
On 7/23/24 20:55, Michael S. Tsirkin wrote:
changes from v1:
dropped two patches:
hw/pci: Do not add ROM BAR for SR-IOV VF
virtio: Always reset vhost devices
at author's request
Akiko, I think the on/off rework is a bit risky so close
to the release. So pls rework you
Add the --noexecstack assembler command-line option to avoid:
/usr/bin/ld: warning: boot.o: missing .note.GNU-stack section implies
executable stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in a
future version of the linker
which is enabled by default with current
Recent updates to debian cross-compilers have enabled some
new warnings by default, which encourage good behaviour for
userland binaries.
Neither are applicable for our system mode kernel images,
but we do have a few userland tests that are affected.
The --noexecstack assembler flag takes care of
Recent debian cross-linker for loongarch issues
ld: warning: hello has a LOAD segment with RWX permissions
This is partially related to tests/tcg/loongarch64/system/kernel.ld,
but is not fixed by explicitly adding a single LOAD PHDR.
Disable the warning, since it does not apply to kernel images
在 2024/7/23 下午11:47, Peter Maydell 写道:
On Wed, 20 Mar 2024 at 02:40, Song Gao wrote:
From: Xianglai Li
When we use qemu tcg simulation, the page size of bios is 4KB.
When using the level 2 super huge page (page size is 1G) to create the page
table,
it is found that the content of the corresp
On 7/23/2024 10:26 PM, Zhao Liu wrote:
(+Xiaoyao, whose TDX work may also be related with this.)
I have a similar patch for TDX because TDX requires CPUID leaf 0x1f to
configure topology as a must.
(I haven't post to QEMU community yet. I'm not sure how people want to
proceed, refine this p
On 7/24/24 03:24, Peter Maydell wrote:
In update_itlb_use() the variables or_mask and and_mask are uint8_t,
which means that in expressions like "and_mask << 24" the usual C
arithmetic conversions will result in the shift being done as a
signed int type, and so we will shift into the sign bit. Fo
On 7/24/24 02:25, Peter Maydell wrote:
Coverity points out that in do_interrupt64() in the "to inner
privilege" codepath we set "ss = 0", but because we also set
"new_stack = 1" there, later in the function we will always override
that value of ss with "ss = 0 | dpl".
Remove the unnecessary init
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ac2dce734d80..1731dc461376 100644
--- a/target/riscv/cpu.c
From: Kaiwen Xue
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 8 +++-
target/riscv/machine.c | 1 +
3 files
Sscofpmf has been supported on virt machine for a long time. It is
required to enable profiling on virt machines. Let's enable it
by default for ease of usage.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/
From: Kaiwen Xue
This adds the indirect access registers required by sscsrind/smcsrind
and the operations on them. Note that xiselect and xireg are used for
both AIA and sxcsrind, and the behavior of accessing them depends on
whether each extension is enabled and the value stored in xiselect.
Co
From: Kaiwen Xue
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/csr.c | 165 -
1 file
From: Kaiwen Xue
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen Xue
Co-developed-by: Atish Patra
Signed-o
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Signed-off-by: Atish Patra
---
target/riscv/tcg/tcg-cpu.c | 28 ++--
1 fil
In addition to the implied rule, a preferred rule will be useful
where an ISA extension may require a list of ISA extension to be
enabled to use all the features defined in that extension. All
these extensions may not be implied in the ISA.
This patch just introduces a new preferred rule which all
On Wed, Jun 5, 2024 at 4:49 AM Jason Chien wrote:
>
> The predicate functions should contain the access control by the
> state-enable CSRs, which is not presented in this patch. Do you mind
> that I take over the indirect CSR access control part? The Signed-off-by
> will be kept.
>
> Atish Patra 於
The current infrastructure for implied ISA extension enabling can
be used for other cases where a particular ISA is dependant on
multiple other ISA extension to enable all the features.
Rename the implied rule functions/data structures to accomodate that.
Signed-off-by: Atish Patra
---
target/r
This series adds the counter delegation extension support. The counter
delegation ISA extension(Smcdeleg/Ssccfg) actually depends on multiple ISA
extensions.
1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitat
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.
Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei
Enable the corresponding bits in [m|h]stateen and enable corresponding
checks in the CS
Counter delegation/configuration extension requires the following
extensions to be enabled.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
3. Smstateen - Indirect CSR extensions depend on it.
4. Sscofpmf - To enable counter overflow feature
From: Kaiwen Xue
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra
Signed-off-by: Kaiwen Xue
Signed-off-by: Atish Patra
---
target/riscv/csr
From: Kaiwen Xue
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 4 insertions(+)
diff
On 7/24/24 01:10, Peter Maydell wrote:
Coverity points out that in helper_eq_b() we have an int32_t 'msk'
and we end up shifting into its sign bit. This is OK for QEMU because
we use -fwrapv to give this well defined semantics, but when you look
at what this function is doing it's doing bit opera
With -fsanitize=undefined, which implies -fsanitize=function,
clang will add a "type signature" before functions.
It accesses funcptr-8 and funcptr-4 to do so.
The generated TCG prologue is directly on a page boundary,
so these accesses segfault.
Signed-off-by: Richard Henderson
---
Does anyone
On 7/23/24 17:02, Konstantin Kostiuk wrote:
The following changes since commit 23fa74974d8c96bc95cbecc0d4e2d90f984939f6:
Merge tag 'pull-target-arm-20240718'
ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-07-19
07:02:17 +1000)
are available in the Git repository at:
On 7/23/24 23:21, ~danikhan632 wrote:
From: Daniyal Khan
---
target/arm/tcg/sme_helper.c| 122 +
target/arm/tcg/translate-sme.c | 37 +-
2 files changed, 115 insertions(+), 44 deletions(-)
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tc
From: Dongwon Kim
Sync object is not used so removing it from QemuDmaBuf struct
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Vivek Kasireddy
Signed-off-by: Dongwon Kim
---
include/ui/dmabuf.h | 2 --
ui/dmabuf.c | 14 --
2 files changed, 16 deletions(-)
diff --git a/inc
From: Dongwon Kim
Sync object itself is never used as is so can be removed
from QemuDmaBuf struct. So now sync is only temporarily needed
when creating fence for the object which means what was done in
egl_dmabuf_create_sync can now be a part of egl_dmabuf_create_fence
function. And egl_dmabuf_cr
From: Dongwon Kim
There is no reason to split those two operations so combining
two functions - egl_dmabuf_create_sync and egl_dmabuf_create_fence.
v2: egl_dmabuf_create_fence -> egl_dmabuf_create_fence_fd
(Marc-André Lureau )
v3: create fence only if current QemuDmaBuf->fence_fd = -1
t
On 7/23/24 13:59, Philippe Mathieu-Daudé wrote:
On 23/7/24 22:54, Pierrick Bouvier wrote:
Reflect recent changes on API (inline ops) and new plugins.
Signed-off-by: Pierrick Bouvier
---
docs/devel/tcg-plugins.rst | 101 +++--
1 file changed, 63 insertions(+
On Tue, Jul 23, 2024 at 05:50:24PM -0300, Fabiano Rosas wrote:
> The natural thing would be to put the hooks inside the data
> type. Something like this:
>
> struct MultiFDRecvData {
> MultiFDMethods *ops; <---
> void *opaque;
> size_t size;
> /* for preadv */
> off_t file_off
On 23/7/24 22:54, Pierrick Bouvier wrote:
Reflect recent changes on API (inline ops) and new plugins.
Signed-off-by: Pierrick Bouvier
---
docs/devel/tcg-plugins.rst | 101 +++--
1 file changed, 63 insertions(+), 38 deletions(-)
$QEMU $OTHER_QEMU_ARGS \
On 23/7/24 19:24, Peter Maydell wrote:
In update_itlb_use() the variables or_mask and and_mask are uint8_t,
which means that in expressions like "and_mask << 24" the usual C
arithmetic conversions will result in the shift being done as a
signed int type, and so we will shift into the sign bit. Fo
Reflect recent changes on API (inline ops) and new plugins.
Signed-off-by: Pierrick Bouvier
---
docs/devel/tcg-plugins.rst | 101 +++--
1 file changed, 63 insertions(+), 38 deletions(-)
diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst
index 95
Peter Xu writes:
> On Tue, Jul 23, 2024 at 02:48:48PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Mon, Jul 22, 2024 at 06:20:28PM -0300, Fabiano Rosas wrote:
>> >> Peter Xu writes:
>> >>
>> >> > On Mon, Jul 22, 2024 at 05:21:48PM -0300, Fabiano Rosas wrote:
>> >> >> Peter Xu w
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Mark Cave-Ayland
Message-Id: <20240722160745.67904-3-phi...@linaro.org>
---
include/qemu/fifo8.h | 22 ++
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/include/qemu/fifo8.h b/in
Add the fifo8_drop() helper for clarity.
It is a simple wrapper over fifo8_pop_buf().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Mark Cave-Ayland
Message-Id: <20240722160745.67904-8-phi...@linaro.org>
---
include/qemu/fifo8.h | 9 +
hw/scsi/esp.c
From: Yao Xingtao
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel P. Berrangé
Message-ID: <20240722040742.11513-12-yaoxt.
Extract fifo8_pop_buf() from hw/scsi/esp.c and expose
it as part of the API. This function takes
care of non-contiguous (wrapped) FIFO buffer (which is an
implementation detail).
Suggested-by: Mark Cave-Ayland
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Pierrick Bouvier
Reviewed-by: Mar
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Tested-by: Jiaxun Yang
Message-Id: <20240718133312.10324-20-phi...@linaro.org>
---
docs/about/emulation.rst | 2 +-
hw/rtc/ls7a_rtc.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
d
Rather than using address_space_rw(..., 0 or 1),
use the simpler DMA memory API which expand to
the same code. This allows removing a cast on
the 'buf' variable which is really const. Since
'buf' is only used in the CMD_READ_BUFFER case,
we can reduce its scope.
Signed-off-by: Philippe Mathieu-Dau
Avoid open-coding fifo8_reset() in fifo8_create().
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Pierrick Bouvier
Message-Id: <20240722160745.67904-4-phi...@linaro.org>
---
util/fifo8.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
di
Reviewed-by: Markus Armbruster
Reviewed-by: Konstantin Kostiuk
Signed-off-by: Philippe Mathieu-Daudé
Message-ID: <20240717140025.66397-1-phi...@linaro.org>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d5ff6c2498e..8c048782a6d 100644
--- a/M
From: Yao Xingtao
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
Reviewed-by: Marc-André Lureau
Message-ID: <20240722040742.11513-13-yaoxt.f...@fujitsu.com>
Signed-off-by: Philippe Mathieu-Daudé
---
dump/dump.c
From: Yao Xingtao
The type of kernel_entry, kernel_low and kernel_high is uint64_t, cast
the pointer of this type to uint64_t* is useless.
Signed-off-by: Yao Xingtao
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240722091728.4334-2-yaoxt.f...@fujitsu.com>
Signe
From: Zhao Liu
While working on a series of CPU/cache topology work, I became
interested in the machine core component and would like to help to
review more related patches.
Signed-off-by: Zhao Liu
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240722164412.1163414-1-zhao1@intel.com>
S
From: Yao Xingtao
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240722040742.11513-9-yaoxt.f...@fujitsu.com>
Signed-off-by: Philippe Mathieu-Daudé
---
target/
Since fifo8_pop_buf() return a const buffer (which points
directly into the FIFO backing store). Rename it using the
'bufptr' suffix to better reflect that it is a pointer to
the internal buffer that is being returned. This will help
differentiate with methods *copying* the FIFO data.
Signed-off-b
From: Yao Xingtao
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: David Hildenbrand
Message-ID: <20240722040742.11513-10-yaoxt.f
qemu_chr_fe_add_watch() and qemu_chr_fe_write[_all]()
return -1 on error. Mention it in the documentation.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Pierrick Bouvier
Message-Id: <20240722160745.67904-2-phi...@linaro.org>
---
include/chardev/char-fe.h | 3
This API is specific to TCG (already handled by hardware
accelerators), so restrict it with #ifdef'ry. Remove
unnecessary stubs.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20240529155918.6221-1-phi...@linaro.org>
---
include/exec/exec-all.h | 7 ++-
a
From: Zhao Liu
According to the comment in qapi/error.h, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts th
From: Thomas Weißschuh
Since commit 3c5f6114d9ff ("qapi: remove "Example" doc section")
the "Example" section is not valid anymore.
It has been replaced by the "qmp-example" directive.
This was not detected earlier as firmware.json was not validated.
As this validation is about to be added, adap
From: Yao Xingtao
use ranges_overlap() instead of open-coding the overlap check to improve
the readability of the code.
Signed-off-by: Yao Xingtao
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Message-ID: <20240722040742.11513-5-yaoxt.f...@fujitsu.com>
Signed-off-by: P
Since fifo8_peek_buf() return a const buffer (which points
directly into the FIFO backing store). Rename it using the
'bufptr' suffix to better reflect that it is a pointer to
the internal buffer that is being returned. This will help
differentiate with methods *copying* the FIFO data.
Signed-off-
On 23/7/24 20:18, Philippe Mathieu-Daudé wrote:
Rather than using address_space_rw(..., 0 or 1),
use the simpler DMA memory API which expand to
the same code. This allows removing a cast on
the 'buf' variable which is really const. Since
'buf' is only used in the CMD_READ_BUFFER case,
we can redu
From: Thomas Weißschuh
Only a small subset of all blockdev drivers make sense for firmware
images. Introduce and use a new enum to represent this.
This also reduces the dependency on firmware.json from the global qapi
definitions.
Claim "Since: 3.0" for the new enum, because that's correct for
From: Bibo Mao
Loongson IPI is only available in little-endian,
so use that to access the guest memory (in case
we run on a big-endian host).
Cc: qemu-sta...@nongnu.org
Signed-off-by: Bibo Mao
Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support")
[PMD: Extracted from bigger co
From: Yao Xingtao
Just like range_overlaps_range(), use the returned bool value
to check whether 2 given ranges overlap.
Signed-off-by: Yao Xingtao
Reviewed-by: Philippe Mathieu-Daudé
Message-ID: <20240722040742.11513-2-yaoxt.f...@fujitsu.com>
Signed-off-by: Philippe Mathieu-Daudé
---
includ
Once initialised, QOM objects can be realized and
unrealized multiple times before being finalized.
Resources allocated in REALIZE must be deallocated
in an equivalent UNREALIZE handler.
Free the CPU array in loongson_ipi_unrealize()
instead of loongson_ipi_finalize().
Cc: qemu-sta...@nongnu.org
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Song Gao
Reviewed-by: Richard Henderson
Reviewed-by: Jiaxun Yang
Tested-by:
From: BALATON Zoltan
The last register of this device is at offset 0x14 occupying 8 bits so
to cover it the mmio region needs to be 0x15 bytes long. Also correct
the name of the field storing this register value to match the
register name.
Signed-off-by: BALATON Zoltan
Fixes: 7abb479c7a ("PPC:
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