[PATCH v1 14/15] aspeed: fix coding style

Fix coding style issues from checkpatch.pl Test command: ./scripts/checkpatch.pl --no-tree -f hw/arm/aspeed.c Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 21 ++--- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 53a4f665d

[PATCH v1 12/15] aspeed/soc: introduce a new API to get the INTC orgate information

Currently, users can set the intc mapping table with enumerated device id and device irq to get the INTC orgate input pins. However, some devices use the continuous bits number in the same orgate. To reduce the enumerated device id definition, create a new API to get the INTC orgate index and sourc

[PATCH v1 06/15] hw/i2c/aspeed: introduce a new bus pool buffer attribute in AspeedI2Cbus

According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. Besides, using a share pool buffer only support pool buffer memory regions are continuous for all I2C bus. To make this model more readable and

[PATCH v1 07/15] hw/i2c/aspeed: support discontinuous poll buffer memory region of I2C bus

It only support continuous pool buffer memory region for all I2C bus. However, the pool buffer address of all I2c bus are discontinuous for AST2700. Ex: the pool buffer address of I2C bus for ast2700 as following. 0x1A0 - 0x1BF: Device 0 buffer 0x2A0 - 0x2BF: Device 1 buffer 0x3A0 - 0x3BF: Device

[PATCH v1 08/15] hw/i2c/aspeed: introduce a new dma_dram_offset attribute in AspeedI2Cbus

The "Current DMA Operating Address Status(0x50)" register of I2C new mode has been removed in AST2700. This register is used for debugging and it is a read only register. To support AST2700 DMA mode, introduce a new dma_dram_offset class attribute in AspeedI2Cbus to save the current DMA operating

[PATCH v1 10/15] hw/i2c/aspeed: support Tx/Rx buffer 64 bits address

ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. It have "Master DMA Mode Tx Buffer Base Address[39:32](0x60)" and "Master DMA Mode Rx Buffer Base Address[39:32](0x64)" to save the high part physical address of Tx/R

[PATCH v1 11/15] hw/i2c/aspeed: support high part dram offset for DMA 64 bits

ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 " which is 64bits address. The AST2700 support the maximum DRAM size is 8 GB. The DRAM physical address range is from "0x4__" to "0x5__". The DRAM offset range is from "0x0_000

[PATCH v1 13/15] aspeed/soc: support I2C for AST2700

Add I2C model for AST2700 I2C support. The I2C controller registers base address is start at 0x14C0_F000 and its address space is 0x2000. The AST2700 I2C controller has one source INTC per bus. I2C buses interrupt are connected to GICINT130_INTC from bit 0 to bit 15. I2C bus 0 is connected to GICI

[PATCH v1 15/15] aspeed: add tmp105 in i2c bus 0 for AST2700

ASPEED SDK add lm75 in i2c bus 0 for AST2700. LM75 is compatible with TMP105 driver. Introduce a new i2c init function and add tmp105 device model in i2c bus 0. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/

[PATCH v1 05/15] hw/i2c/aspeed: rename the I2C class pool attribute to share_pool

According to the datasheet of ASPEED SOCs, each I2C bus has their own pool buffer since AST2500. Only AST2400 utilized a pool buffer share to all I2C bus. And firmware required to set the offset of pool buffer by writing "Function Control Register(I2CD 00)" To make this model more readable, will

[PATCH v1 09/15] hw/i2c/aspeed: Add AST2700 support

Introduce a new ast2700 class to support AST2700. The I2C bus register memory regions and I2C bus pool buffer memory regions are discontinuous and they do not back compatible AST2600. Add a new ast2700 i2c class init function to match the address of I2C bus register and pool buffer from the datash

[PATCH v1 01/15] aspeed/adc: Add AST2700 support

AST2700 and AST2600 ADC controllers are identical. Introduce ast2700 class and set 2 engines. Signed-off-by: Jamin Lin --- hw/adc/aspeed_adc.c | 16 include/hw/adc/aspeed_adc.h | 1 + 2 files changed, 17 insertions(+) diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_ad

[PATCH v1 04/15] hw/i2c/aspeed: support discontinuous register memory region of I2C bus

It only support continuous register memory region for all I2C bus. However, the register address of all I2c bus are discontinuous for AST2700. Ex: the register address of I2C bus for ast2700 as following. 0x100 - 0x17F: Device 0 0x200 - 0x27F: Device 1 0x300 - 0x37F: Device 2 0x400 - 0x47F: Device

[PATCH v1 03/15] hw/i2c/aspeed: support to set the different memory size

According to the datasheet of ASPEED SOCs, an I2C controller owns 8KB of register space for AST2700, owns 4KB of register space for AST2600, AST2500 and AST2400, and owns 64KB of register space for AST1030. It set the memory region size 4KB by default and it does not compatible register space for

[PATCH v1 00/15] support ADC and I2C for AST2700

v1: 1. support ADC for AST2700 2. support I2C for AST2700 Jamin Lin (15): aspeed/adc: Add AST2700 support aspeed/soc: support ADC for AST2700 hw/i2c/aspeed: support to set the different memory size hw/i2c/aspeed: support discontinuous register memory region of I2C bus hw/i2c/aspeed: ren

[PATCH v1 02/15] aspeed/soc: support ADC for AST2700

Add ADC model for AST2700 ADC support. The ADC controller registers base address is start at 0x14C0_ and its address space is 0x1000. The ADC controller interrupt is connected to GICINT130_INTC group at bit 16. The GIC IRQ is 130. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 12 +++

Re: [PATCH v3] chardev: add path option for pty backend

Looks like this one fell through the cracks. Octavian Purdila writes: > Add path option to the pty char backend which will create a symbolic > link to the given path that points to the allocated PTY. > > This avoids having to make QMP or HMP monitor queries to find out what > the new PTY device

Re: [RFC 3/5] i386/kvm: Support event with select&umask format in KVM PMU filter

On 7/10/2024 12:51 PM, Zhao Liu wrote: > The select&umask is the common way for x86 to identify the PMU event, > so support this way as the "x86-default" format in kvm-pmu-filter > object. > > Signed-off-by: Zhao Liu > --- > accel/kvm/kvm-pmu.c | 62

Re: [RFC 0/5] accel/kvm: Support KVM PMU filter

On 7/10/2024 12:51 PM, Zhao Liu wrote: > Hi QEMU maintainers, arm and PMU folks, > > I picked up Shaoqing's previous work [1] on the KVM PMU filter for arm, > and now is trying to support this feature for x86 with a JSON-compatible > API. > > While arm and x86 use different KVM ioctls to configur

Re: [PATCH v5 08/13] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

On Tue, Jul 9, 2024 at 3:38 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The RISC-V IOMMU spec predicts that the IOMMU can use translation caches > to hold entries from the DDT. This includes implementation for all cache > commands that are marked as 'not implemented'. > > There

Re: [PATCH v5 05/13] hw/riscv: add riscv-iommu-pci reference device

On Tue, Jul 9, 2024 at 3:38 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The RISC-V IOMMU can be modelled as a PCIe device following the > guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU > as a PCIe device". > > Signed-off-by: Tomasz Jeznach > Signed-off

Re: [PATCH v5 03/13] hw/riscv: add RISC-V IOMMU base emulation

On Tue, Jul 9, 2024 at 3:37 AM Daniel Henrique Barboza wrote: > > From: Tomasz Jeznach > > The RISC-V IOMMU specification is now ratified as-per the RISC-V > international process. The latest frozen specifcation can be found at: > > https://github.com/riscv-non-isa/riscv-iommu/releases/download/v

Re: [PATCH v2 6/9] qapi: convert "Example" sections without titles

John Snow writes: > On Wed, Jul 17, 2024, 3:44 AM Markus Armbruster wrote: > >> John Snow writes: >> >> > Use the no-option form of ".. qmp-example::" to convert any Examples >> > that do not have any form of caption or explanation whatsoever. Note >> > that in a few cases, example sections are

[PULL 29/30] hw/riscv/virt.c: re-insert and deprecate 'riscv, delegate'

From: Daniel Henrique Barboza Commit b1f1e9dcfa renamed 'riscv,delegate' to 'riscv,delegation' since it is the correct name as per dt-bindings, and the absence of the correct name will result in validation fails when dumping the dtb and using dt-validate. But this change has a side-effect: every

[PULL 15/30] target/riscv: Combine set_mode and set_virt functions.

From: Rajnesh Kanwal Combining riscv_cpu_set_virt_enabled() and riscv_cpu_set_mode() functions. This is to make complete mode change information available through a single function. This allows to easily differentiate between HS->VS, VS->HS and VS->VS transitions when executing state update code

[PULL 27/30] target/riscv: Expose the Smcntrpmf config

From: Atish Patra Create a new config for Smcntrpmf extension so that it can be enabled/ disabled from the qemu commandline. Signed-off-by: Atish Patra Acked-by: Alistair Francis Message-ID: <20240711-smcntrpmf_v7-v8-13-b7c38ae7b...@rivosinc.com> Signed-off-by: Alistair Francis --- target/ri

[PULL 06/30] target/riscv: Move gen_amo before implement Zabha

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Message-ID: <20240709113652.1239-7-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c| 21 + target/riscv/insn_trans/trans_rva.c.inc | 21 -

[PULL 26/30] target/riscv: Do not setup pmu timer if OF is disabled

From: Atish Patra The timer is setup function is invoked in both hpmcounter write and mcountinhibit write path. If the OF bit set, the LCOFI interrupt is disabled. There is no benefitting in setting up the qemu timer until LCOFI is cleared to indicate that interrupts can be fired again. Reviewed

[PULL 23/30] target/riscv: Enforce WARL behavior for scounteren/hcounteren

From: Atish Patra scounteren/hcountern are also WARL registers similar to mcountern. Only set the bits for the available counters during the write to preserve the WARL behavior. Signed-off-by: Atish Patra Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240711

[PULL 14/30] target/riscv/kvm: update KVM regs to Linux 6.10-rc5

From: Daniel Henrique Barboza Two new regs added: ztso and zacas. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240709085431.455541-1-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis --- target/riscv/kvm/kvm-cpu.c | 2 ++ 1 file changed, 2 inse

[PULL 28/30] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

From: Yu-Ming Chang Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and wi

[PULL 07/30] target/riscv: Add AMO instructions for Zabha

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Message-ID: <20240709113652.1239-8-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_cfg.h | 1 + target/riscv/insn32.decode | 20 +++ target/riscv/t

[PULL 12/30] target/riscv: Validate the mode in write_vstvec

From: Jiayi Li Base on the riscv-privileged spec, vstvec substitutes for the usual stvec. Therefore, the encoding of the MODE should also be restricted to 0 and 1. Signed-off-by: Jiayi Li Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei Message-ID: <20240701022553.1982-1-liji...@eswincom

Re: [PATCH v3 04/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()

On 2024/7/18 上午5:46, Philippe Mathieu-Daudé wrote: From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --

[PULL 24/30] target/riscv: Start counters from both mhpmcounter and mcountinhibit

From: Rajnesh Kanwal Currently we start timer counter from write_mhpmcounter path only without checking for mcountinhibit bit. This changes adds mcountinhibit check and also programs the counter from write_mcountinhibit as well. When a counter is stopped using mcountinhibit we simply update the

[PULL 09/30] target/riscv: Add amocas.[b|h] for Zabha

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240709113652.1239-10-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/insn32.decode | 2 ++ target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++

[PULL 25/30] target/riscv: More accurately model priv mode filtering.

From: Rajnesh Kanwal In case of programmable counters configured to count inst/cycles we often end-up with counter not incrementing at all from kernel's perspective. For example: - Kernel configures hpm3 to count instructions and sets hpmcounter to -1 and all modes except U mode are inhibi

[PULL 04/30] disas/riscv: Support zcmop disassemble

From: LIU Zhiwei Although in QEMU disassemble, we usually lift compressed instruction to an normal format when display the instruction name. For C.MOP.n, it is more reasonable to directly display its compressed name, because its behavior can be redefined by later extension. Signed-off-by: LIU Zh

[PULL 03/30] target/riscv: Add zcmop extension

From: LIU Zhiwei Zcmop defines eight 16-bit MOP instructions named C.MOP.n, where n is an odd integer between 1 and 15, inclusive. C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions are defined

[PULL 05/30] target/riscv: Support Zama16b extension

From: LIU Zhiwei Zama16b is the property that misaligned load/stores/atomics within a naturally aligned 16-byte region are atomic. According to the specification, Zama16b applies only to AMOs, loads and stores defined in the base ISAs, and loads and stores of no more than XLEN bits defined in th

[PULL 30/30] roms/opensbi: Update to v1.5

From: Daniel Henrique Barboza Update OpenSBI and the pre-built opensbi32 and opensbi64 images to v1.5. The following commits were included in v1.5: 455de67 include: Bump-up version to 1.5 23b7bad lib: sbi: check incoming dbtr shmem address 0e45b63 docs: Fix wrong filename caae2f7 lib: sbi: fwft

[PULL 21/30] target/riscv: Implement privilege mode filtering for cycle/instret

From: Atish Patra Privilege mode filtering can also be emulated for cycle/instret by tracking host_ticks/icount during each privilege mode switch. This patch implements that for both cycle/instret and mhpmcounters. The first one requires Smcntrpmf while the other one requires Sscofpmf to be enabl

[PULL 18/30] target/riscv: Add cycle & instret privilege mode filtering definitions

From: Kaiwen Xue This adds the definitions for ISA extension smcntrpmf. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-ID: <20240711-smcntrpmf_v7-v8-4-b7c38ae7b...@rivosinc.com> Signed-off-by: Alistair Francis

[PULL 22/30] target/riscv: Save counter values during countinhibit update

From: Atish Patra Currently, if a counter monitoring cycle/instret is stopped via mcountinhibit we just update the state while the value is saved during the next read. This is not accurate as the read may happen many cycles after the counter is stopped. Ideally, the read should return the value s

[PULL 16/30] target/riscv: Fix the predicate functions for mhpmeventhX CSRs

From: Atish Patra mhpmeventhX CSRs are available for RV32. The predicate function should check that first before checking sscofpmf extension. Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support") Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: A

[PULL 20/30] target/riscv: Only set INH fields if priv mode is available

From: Atish Patra Currently, the INH fields are set in mhpmevent uncoditionally without checking if a particular priv mode is supported or not. Suggested-by: Alistair Francis Signed-off-by: Atish Patra Acked-by: Alistair Francis Message-ID: <20240711-smcntrpmf_v7-v8-6-b7c38ae7b...@rivosinc.co

[PULL 17/30] target/riscv: Add cycle & instret privilege mode filtering properties

From: Kaiwen Xue This adds the properties for ISA extension smcntrpmf. Patches implementing it will follow. Signed-off-by: Kaiwen Xue Reviewed-by: Daniel Henrique Barboza Signed-off-by: Atish Patra Reviewed-by: Alistair Francis Message-ID: <20240711-smcntrpmf_v7-v8-3-b7c38ae7b...@rivosinc.co

[PULL 13/30] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford Acked-by: Alistair Francis Message-ID: <20240705165316.127494-1-rbradf...@rivosinc.com> Signed-off-by: Alistair Francis --- disa

[PULL 01/30] target/riscv: Add zimop extension

From: LIU Zhiwei Zimop extension defines an encoding space for 40 MOPs.The Zimop extension defines 32 MOP instructions named MOP.R.n, where n is an integer between 0 and 31, inclusive. The Zimop extension additionally defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 and

[PULL 10/30] target/riscv: Expose zabha extension as a cpu property

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-ID: <20240709113652.1239-11-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[PULL 08/30] target/riscv: Move gen_cmpxchg before adding amocas.[b|h]

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Message-ID: <20240709113652.1239-9-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- target/riscv/translate.c| 13 + target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -

[PULL 02/30] disas/riscv: Support zimop disassemble

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Deepak Gupta Message-ID: <20240709113652.1239-3-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 98 +++ 1 file changed, 98 inse

[PULL 19/30] target/riscv: Add cycle & instret privilege mode filtering support

From: Kaiwen Xue QEMU only calculates dummy cycles and instructions, so there is no actual means to stop the icount in QEMU. Hence this patch merely adds the functionality of accessing the cfg registers, and cause no actual effects on the counting of cycle and instret counters. Signed-off-by: At

[PULL 11/30] disas/riscv: Support zabha disassemble

From: LIU Zhiwei Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Message-ID: <20240709113652.1239-12-zhiwei_...@linux.alibaba.com> Signed-off-by: Alistair Francis --- disas/riscv.c | 60 +++ 1 file changed, 60 insertions(+) diff --git a/di

[PULL 00/30] riscv-to-apply queue

The following changes since commit 58ee924b97d1c0898555647a31820c5a20d55a73: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-07-17 15:40:28 +1000) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240718-

RE: [PATCH v2] pci-bridge: avoid linking a single downstream port more than once

> -Original Message- > From: Michael S. Tsirkin > Sent: Wednesday, July 17, 2024 8:04 PM > To: Yao, Xingtao/姚 幸涛 > Cc: marcel.apfelb...@gmail.com; qemu-devel@nongnu.org; > jonathan.came...@huawei.com > Subject: Re: [PATCH v2] pci-bridge: avoid linking a single downstream port > more >

RE: [PATCH v2] pci-bridge: avoid linking a single downstream port more than once

> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Wednesday, July 17, 2024 6:18 PM > To: Yao, Xingtao/姚 幸涛 ; m...@redhat.com; > marcel.apfelb...@gmail.com > Cc: qemu-devel@nongnu.org; jonathan.came...@huawei.com > Subject: Re: [PATCH v2] pci-bridge: avoid linking a single downs

Re: [PULL 00/20] i386, bugfix changes for QEMU 9.1 soft freeze

On 7/17/24 15:03, Paolo Bonzini wrote: The following changes since commit 959269e910944c03bc13f300d65bf08b060d5d0f: Merge tag 'python-pull-request' ofhttps://gitlab.com/jsnow/qemu into staging (2024-07-16 06:45:23 +1000) are available in the Git repository at: https://gitlab.com/bonzini

Re: [PATCH ats_vtd v5 20/22] pci: add a pci-level API for ATS

On 24-07-11 19:00:58, CLEMENT MATHIEU--DRIF wrote: > > > On 11/07/2024 10:04, Minwoo Im wrote: > > Caution: External email. Do not open attachments or click links, unless > > this email comes from a known sender and you know the content is safe. > > > > > > On 24-07-10 05:17:42, CLEMENT MATHIEU-

[PATCH v3 13/17] hw/intc/loongson_ipi: Move common code to loongson_ipi_common.c

From: Bibo Mao Move the common code from loongson_ipi.c to loongson_ipi_common.c, call parent_realize() instead of loongson_ipi_common_realize() in loongson_ipi_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé

[PATCH v3 16/17] hw/intc/loongson_ipi: Restrict to MIPS

From: Bibo Mao Now than LoongArch target can use the TYPE_LOONGARCH_IPI model, restrict TYPE_LOONGSON_IPI to MIPS. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongson_ipi.c | 14 -- 1 file

[PATCH v3 17/17] hw/intc/loongson_ipi: Remove unused headers

Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongson_ipi.c | 9 - 1 file changed, 9 deletions(-) diff --git a/hw/intc/loongson_ipi.c b/hw/intc/loongson_ipi.c index 61375d89ff..6dd08aa9cb 100644 --- a/hw/intc/loongson_ipi.c +++ b/hw/intc/loongson_ipi.c @@ -6,18 +6,9 @@ */ #incl

[PATCH v3 04/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_realize()

From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_realize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongson_ipi.c | 25 ++---

[PATCH v3 12/17] hw/intc/loongson_ipi: Expose loongson_ipi_core_read/write helpers

From: Bibo Mao In order to access loongson_ipi_core_read/write helpers from loongson_ipi_common.c in the next commit, make their prototype declaration public. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- includ

[PATCH v3 11/17] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::cpu_by_arch_id handler

From: Bibo Mao Allow Loongson IPI implementations to have their own cpu_by_arch_id() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi_common.h | 1 + hw/intc/loongson_ipi.c

[PATCH v3 01/17] hw/intc/loongson_ipi: Access memory in little endian

From: Bibo Mao Loongson IPI is only available in little-endian, so use that to access the guest memory (in case we run on a big-endian host). Signed-off-by: Bibo Mao Fixes: f6783e3438 ("hw/loongarch: Add LoongArch ipi interrupt support") [PMD: Extracted from bigger commit, added commit descript

[PATCH v3 15/17] hw/loongarch/virt: Replace loongson IPI with loongarch IPI

From: Bibo Mao Loongarch IPI inherits from class LoongsonIPICommonClass, and it only contains Loongarch 3A5000 virt machine specific interfaces, rather than mix different machine implementations together. Signed-off-by: Bibo Mao [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé --- include

[PATCH v3 10/17] hw/intc/loongson_ipi: Add LoongsonIPICommonClass::get_iocsr_as handler

From: Bibo Mao Allow Loongson IPI implementations to have their own get_iocsr_as() handler. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi_common.h | 2 ++ hw/intc/loongson_ipi.c

[PATCH v3 08/17] hw/intc/loongson_ipi: Move IPICore structure to loongson_ipi_common.h

From: Bibo Mao Move the IPICore structure and corresponding common fields of LoongsonIPICommonState to "hw/intc/loongson_ipi_common.h". Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.

[PATCH v3 14/17] hw/intc/loongarch_ipi: Add loongarch IPI support

From: Bibo Mao Loongarch IPI is added here, it inherits from class TYPE_LOONGSON_IPI_COMMON, and two interfaces get_iocsr_as() and cpu_by_arch_id() are added for Loongarch 3A5000 machine. It can be used when ipi is emulated in userspace with KVM mode. Signed-off-by: Bibo Mao [PMD: Rebased and s

[PATCH v3 09/17] hw/intc/loongson_ipi: Pass LoongsonIPICommonState to send_ipi_data()

From: Bibo Mao In order to get LoongsonIPICommonClass in send_ipi_data() in the next commit, propagate LoongsonIPICommonState. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongson_ipi.c | 19 ++

[PATCH v3 07/17] hw/intc/loongson_ipi: Move IPICore::mmio_mem to LoongsonIPIState

From: Bibo Mao It is easier to manage one array of MMIO MR rather than one per vCPU. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.h | 2 +- hw/intc/loongson_ipi.c | 9 ++

[PATCH v3 05/17] hw/intc/loongson_ipi: Add TYPE_LOONGSON_IPI_COMMON stub

From: Bibo Mao Introduce LOONGSON_IPI_COMMON stubs, QDev parent of LOONGSON_IPI. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.h| 13 +++-- include/hw/intc/loongson_i

[PATCH v3 06/17] hw/intc/loongson_ipi: Move common definitions to loongson_ipi_common.h

From: Bibo Mao Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.h| 18 -- include/hw/intc/loongson_ipi_common.h | 19 +++ 2 files changed, 19 inse

[PATCH v3 02/17] hw/intc/loongson_ipi: Rename LoongsonIPI -> LoongsonIPIState

From: Bibo Mao We'll have to add LoongsonIPIClass in few commits, so rename LoongsonIPI as LoongsonIPIState for clarity. Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/loongson_ipi.h | 6 +++---

[PATCH v3 03/17] hw/intc/loongson_ipi: Extract loongson_ipi_common_finalize()

From: Bibo Mao In preparation to extract common IPI code in few commits, extract loongson_ipi_common_finalize(). Signed-off-by: Bibo Mao [PMD: Extracted from bigger commit, added commit description] Signed-off-by: Philippe Mathieu-Daudé --- hw/intc/loongson_ipi.c | 7 ++- 1 file changed,

[PATCH v3 00/17] Reconstruct loongson ipi driver

Hi, this is a respin of Bibo v2 [*] splitting the patches in atomic/trivial changes as I was taking notes reviewing it. I suppose I shoudn't have done that way and asked Bibo to do it, but I felt responsible for merging Jiaxun series and soft freeze is urging. Patch descriptions are expected to b

Re: [PATCH v2 0/4] Reconstruct loongson ipi driver

On 17/7/24 13:53, Jiaxun Yang wrote: 在2024年7月17日七月 下午5:22，maobibo写道： On 2024/7/16 下午2:40, Philippe Mathieu-Daudé wrote: On 16/7/24 03:29, maobibo wrote: On 2024/7/16 上午9:04, maobibo wrote: On 2024/7/15 下午11:17, Philippe Mathieu-Daudé wrote: On 4/7/24 05:37, Bibo Mao wrote: Now loongso

Re: [RFC PATCH 6/7] migration/multifd: Move payload storage out of the channel parameters

On Wed, Jul 17, 2024 at 11:07:17PM +0200, Maciej S. Szmigiero wrote: > On 17.07.2024 21:00, Peter Xu wrote: > > On Tue, Jul 16, 2024 at 10:10:25PM +0200, Maciej S. Szmigiero wrote: > > > > > > > The comment I removed is slightly misleading to me too, because > > > > > > > right now > > > > > > > a

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

On Wed, Jul 17, 2024 at 11:07:43PM +0200, Maciej S. Szmigiero wrote: > > Don't wait on me. I think I can make the changes Peter suggested without > > affecting too much the interfaces used by this series. If it comes to > > it, I can rebase this series "under" Maciej's. > > So to be clear, I shoul

Re: [RFC PATCH] hw/core/cpu.h: try and document CPU_FOREACH[_SAFE]

Alex Bennée writes: > There is some confusion about when you should use one over the other. > Lets try and address that by adding some kdoc comments. > > Suggested-by: Paolo Bonzini > Signed-off-by: Alex Bennée ping? > --- > include/hw/core/cpu.h | 19 ++- > 1 file changed, 1

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

On 17.07.2024 22:19, Fabiano Rosas wrote: Peter Xu writes: On Tue, Jul 16, 2024 at 10:10:12PM +0200, Maciej S. Szmigiero wrote: On 27.06.2024 16:56, Peter Xu wrote: On Thu, Jun 27, 2024 at 11:14:28AM +0200, Maciej S. Szmigiero wrote: On 26.06.2024 18:23, Peter Xu wrote: On Wed, Jun 26, 202

Re: [RFC PATCH 6/7] migration/multifd: Move payload storage out of the channel parameters

On 17.07.2024 21:00, Peter Xu wrote: On Tue, Jul 16, 2024 at 10:10:25PM +0200, Maciej S. Szmigiero wrote: The comment I removed is slightly misleading to me too, because right now active_slot contains the data hasn't yet been delivered to multifd, so we're "putting it back to free list" not beca

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

Peter Xu writes: > On Tue, Jul 16, 2024 at 10:10:12PM +0200, Maciej S. Szmigiero wrote: >> On 27.06.2024 16:56, Peter Xu wrote: >> > On Thu, Jun 27, 2024 at 11:14:28AM +0200, Maciej S. Szmigiero wrote: >> > > On 26.06.2024 18:23, Peter Xu wrote: >> > > > On Wed, Jun 26, 2024 at 05:47:34PM +0200,

Re: [PATCH v2 6/9] qapi: convert "Example" sections without titles

On Wed, Jul 17, 2024, 3:44 AM Markus Armbruster wrote: > John Snow writes: > > > Use the no-option form of ".. qmp-example::" to convert any Examples > > that do not have any form of caption or explanation whatsoever. Note > > that in a few cases, example sections are split into two or more > >

Re: [PATCH v2 0/9] qapi: convert example sections to qmp-example rST directives

On Wed, Jul 17, 2024, 6:47 AM Markus Armbruster wrote: > John Snow writes: > > > This patchset focuses on converting example sections to rST directives > > using a new `.. qmp-example::` directive. > > Queued, thanks! > Yay! >

[PATCH] docs: fix the html docs search function

Fix the search function in Sphinx generated html docs when built with Sphinx >= 6.0.0. Quote from the Sphinx blog at https://blog.readthedocs.com/sphinx6-upgrade Sphinx 6 is out and has important breaking changes Bundled jQuery is removed. The JavaScript asset is easily added back using the new

Re: [PATCH v5 08/13] migration/multifd: Add new migration option for multifd DSA offloading.

Fabiano Rosas writes: > Yichen Wang writes: > >> On Thu, Jul 11, 2024 at 2:53 PM Yichen Wang >> wrote: >> >>> diff --git a/migration/options.c b/migration/options.c >>> index 645f55003d..f839493016 100644 >>> --- a/migration/options.c >>> +++ b/migration/options.c >>> @@ -29,6 +29,7 @@ >>> #i

Re: [PATCH V2 01/11] machine: alloc-anon option

On Tue, Jul 16, 2024 at 11:19:55AM +0200, Igor Mammedov wrote: > On Sun, 30 Jun 2024 12:40:24 -0700 > Steve Sistare wrote: > > > Allocate anonymous memory using mmap MAP_ANON or memfd_create depending > > on the value of the anon-alloc machine property. This affects > > memory-backend-ram object

Re: [PATCH v5 00/18] SMMUv3 nested translation support

On Wed, 17 Jul 2024 at 18:44, Eric Auger wrote: > > Hi Peter, Richard, > > On 7/17/24 17:09, Jean-Philippe Brucker wrote: > > On Mon, Jul 15, 2024 at 08:45:00AM +, Mostafa Saleh wrote: > >> Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs > >> but not nested instances. > >> T

Re: [RFC PATCH 6/7] migration/multifd: Move payload storage out of the channel parameters

On Tue, Jul 16, 2024 at 10:10:25PM +0200, Maciej S. Szmigiero wrote: > > > > > The comment I removed is slightly misleading to me too, because right > > > > > now > > > > > active_slot contains the data hasn't yet been delivered to multifd, so > > > > > we're "putting it back to free list" not bec

Re: [PATCH V2 04/11] migration: stop vm earlier for cpr

Steve Sistare writes: > Stop the vm earlier for cpr, to guarantee consistent device state when > CPR state is saved. > > Signed-off-by: Steve Sistare > --- > migration/migration.c | 22 +- > 1 file changed, 13 insertions(+), 9 deletions(-) > > diff --git a/migration/migratio

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

On Tue, Jul 16, 2024 at 10:10:12PM +0200, Maciej S. Szmigiero wrote: > On 27.06.2024 16:56, Peter Xu wrote: > > On Thu, Jun 27, 2024 at 11:14:28AM +0200, Maciej S. Szmigiero wrote: > > > On 26.06.2024 18:23, Peter Xu wrote: > > > > On Wed, Jun 26, 2024 at 05:47:34PM +0200, Maciej S. Szmigiero wrote

Re: [PATCH V2 02/11] migration: cpr-state

Steve Sistare writes: > CPR must save state that is needed after QEMU is restarted, when devices > are realized. Thus the extra state cannot be saved in the migration stream, > as objects must already exist before that stream can be loaded. Instead, > define auxilliary state structures and vmst

Re: [PATCH V2 03/11] migration: save cpr mode

Steve Sistare writes: > Save the mode in CPR state, so the user does not need to explicitly specify > it for the target. Modify migrate_mode() so it returns the incoming mode on > the target. > > Signed-off-by: Steve Sistare > --- > include/migration/cpr.h | 7 +++ > migration/cpr.c

Re: [PATCH v4 0/8] semihosting: Restrict to TCG

Philippe Mathieu-Daudé writes: > v4: Address Paolo's comment > v3: Address Anton's comment > v2: Address Paolo's comment > > Semihosting currently uses the TCG probe_access API, > so it is pointless to have it in the binary when TCG > isn't. > > It could be implemented for other accelerators, but

Re: [PATCH] plugins/execlog.c: correct dump of registers values

Frédéric Pétrot writes: > Register values are dumped as 'sz' chunks of two nibbles in the execlog > plugin, sz was 1 too big. > > Signed-off-by: Frédéric Pétrot > Queued to plugins/next, thanks. -- Alex Bennée Virtualisation Tech Lead @ Linaro

Re: [PATCH v5 00/18] SMMUv3 nested translation support

Hi Peter, Richard, On 7/17/24 17:09, Jean-Philippe Brucker wrote: > On Mon, Jul 15, 2024 at 08:45:00AM +, Mostafa Saleh wrote: >> Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs >> but not nested instances. >> This patch series adds support for nested translation in SMMUv3,

[PATCH 3/4] ui/vdagent: notify clipboard peers of serial reset

From: Marc-André Lureau Since we reset the serial counters, peers should also be reset to be sync. Signed-off-by: Marc-André Lureau --- ui/clipboard.c | 2 ++ ui/vdagent.c| 2 ++ ui/trace-events | 1 + 3 files changed, 5 insertions(+) diff --git a/ui/clipboard.c b/ui/clipboard.c index 42

[PATCH 0/4] ui: fixes for dbus clipboard hanling

From: Marc-André Lureau Hi, -display dbus clipboard is broken after a client reconnection. The two main issues are capabilities not renegotiated (and thus guest agent not fully functional), and qemu clipboard serial not correctly reset. Marc-André Lureau (4): ui: add more tracing for dbus u

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