[PATCH v2 6/8] aspeed: Add boot-from-eMMC HW strapping bit to rainier-bmc machine

From: Cédric Le Goater This value is taken from a running Rainier machine. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Tested-by: Andrew Jeffery --- hw/arm/aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index bc4

[PATCH v2 8/8] aspeed: Introduce a 'boot-emmc' machine option

From: Cédric Le Goater The default behavior of some Aspeed machines is to boot from the eMMC device, like the rainier-bmc. Others like ast2600-evb could also boot from eMMC if the HW strapping boot-from-eMMC bit was set. Add a property to set or unset this bit. This is useful to test boot images.

[PATCH v2 3/8] aspeed/scu: Add boot-from-eMMC HW strapping bit for AST2600 SoC

From: Cédric Le Goater Bit SCU500[2] of the AST2600 controls the boot device of the SoC. Future changes will configure this bit to boot from eMMC disk images specially built for this purpose. Signed-off-by: Joel Stanley Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Tested-by: A

[PATCH v2 7/8] aspeed: Introduce a 'hw_strap1' machine attribute

From: Cédric Le Goater To change default behavior of a machine and boot from eMMC, future changes will add a machine option to let the user configure the boot-from-eMMC HW strapping bit. Add a new machine attribute first. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Tested-by: A

[PATCH v2 4/8] aspeed: Introduce a AspeedSoCClass 'boot_from_emmc' handler

From: Cédric Le Goater Report support on the AST2600 SoC if the boot-from-eMMC HW strapping bit is set at the board level. AST2700 also has support but it is not yet ready in QEMU and others SoCs do not have support, so return false always for these. Signed-off-by: Cédric Le Goater Reviewed-by:

[PATCH v2 5/8] aspeed: Tune eMMC device properties to reflect HW strapping

From: Cédric Le Goater When the boot-from-eMMC HW strapping bit is set, use the 'boot-config' property to set the boot config register to boot from the first boot area partition of the eMMC device. Also set the boot partition size of the device. Signed-off-by: Cédric Le Goater Reviewed-by: Andr

[PATCH v2 2/8] aspeed: Load eMMC first boot area as a boot rom

From: Cédric Le Goater The first boot area partition (64K) of the eMMC device should contain an initial boot loader (u-boot SPL). Load it as a ROM only if an eMMC device is available to boot from but no flash device is. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Tested-by: And

[PATCH v2 1/8] aspeed: Change type of eMMC device

From: Cédric Le Goater The QEMU device model representing the eMMC device of the machine is currently created with type SD_CARD. Change the type to EMMC now that it is available. Signed-off-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Tested-by: Andrew Jeffery Reviewed-by: Philippe Mathie

[PATCH v2 0/8] aspeed: Add boot from eMMC support (AST2600)

Hello, This series enables boot from eMMC on the rainier-bmc machine, which is the default behavior and also on the AST2600 EVB using a machine option to change the default. First 6 patches adjust the machine setup and HW strapping to boot from eMMC, the last 2 are for the AST2600 EVB and are opt

[ANNOUNCE] QEMU 7.2.13 Stable released

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hi everyone, The QEMU v7.2.13 stable release is now available. You can grab the tarball from our download page here: https://www.qemu.org/download/#source https://download.qemu.org/qemu-7.2.13.tar.xz https://download.qemu.org/qemu-7.2.13.ta

Re: [RFC PATCH 0/8] Convert avocado tests to normal Python unittests

On 16/07/2024 18.45, John Snow wrote: On Thu, Jul 11, 2024, 7:55 AM Thomas Huth > wrote: ... - I haven't looked into logging yet ... this still needs some work   so that you could e.g. inspect the console output of the guests   somewhere FWIW: This is now

Re: [PATCH] doc/net/l2tpv3: Update boolean fields' description to avoid short-form use

Hi Jason, Just a kind ping. Does this update satisfy you? Since the original example generates the warning. Thanks, Zhao On Mon, Jul 08, 2024 at 05:26:30PM +0800, Zhao Liu wrote: > Date: Mon, 8 Jul 2024 17:26:30 +0800 > From: Zhao Liu > Subject: [PATCH] doc/net/l2tpv3: Update boolean fields' de

[PATCH 11/17] target/arm: Fix whitespace near gen_srshr64_i64

Signed-off-by: Richard Henderson --- target/arm/tcg/gengvec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/gengvec.c b/target/arm/tcg/gengvec.c index 47ac2634ce..b6c0d86bad 100644 --- a/target/arm/tcg/gengvec.c +++ b/target/arm/tcg/gengvec.c @@ -304,7 +304,7

[PATCH 16/17] target/arm: Convert SSHLL, USHLL to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 84 -- target/arm/tcg/a64.decode | 3 ++ 2 files changed, 43 insertions(+), 44 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 627d4311bb..2

[PATCH 17/17] target/arm: Push tcg_rnd into handle_shri_with_rndacc

We always pass the same value for round; compute it within common code. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 32 ++-- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/transl

[PATCH 08/17] target/arm: Convert FMOVI (scalar, immediate) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 74 -- target/arm/tcg/a64.decode | 4 ++ 2 files changed, 30 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 2964279c00..6

[PATCH 13/17] target/arm: Convet handle_vec_simd_shli to decodetree

This includes SHL and SLI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 40 +- target/arm/tcg/a64.decode | 6 + 2 files changed, 16 insertions(+), 30 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran

[PATCH 15/17] target/arm: Use {,s}extract in handle_vec_simd_wshli

Combine the right shift with the extension via the tcg extract operations. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d0ad6c90

[PATCH 05/17] target/arm: Simplify do_reduction_op

Use simple shift and add instead of ctpop, ctz, shift and mask. Unlike SVE, there is no predicate to disable elements. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 40 +++--- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/targ

[PATCH 06/17] target/arm: Convert ADDV, *ADDLV, *MAXV, *MINV to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 140 - target/arm/tcg/a64.decode | 12 +++ 2 files changed, 61 insertions(+), 91 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6d2e1a2d80.

[PATCH 10/17] target/arm: Introduce gen_gvec_sshr, gen_gvec_ushr

Handle the two special cases within these new functions instead of higher in the call stack. Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 5 + target/arm/tcg/gengvec.c| 19 +++ target/arm/tcg/translate-a64.c | 16 +--- target/ar

[PATCH 12/17] target/arm: Convert handle_vec_simd_shri to decodetree

This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 109 +++-- target/arm/tcg/a64.decode | 27 +++- 2 files changed, 74 insertions(+), 62 deletions(-) diff --git a/targ

[PATCH 14/17] target/arm: Clear high SVE elements in handle_vec_simd_wshli

AdvSIMD instructions are supposed to zero bits beyond 128. Affects SSHLL, USHLL, SSHLL2, USHLL2. Cc: qemu-sta...@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/tran

[PATCH 00/17] target/arm: AdvSIMD decodetree conversion, part 4

Flush before the queue gets too big. Also, there's a bug fix in patch 14. r~ Richard Henderson (17): target/arm: Use tcg_gen_extract2_i64 for EXT target/arm: Convert EXT to decodetree target/arm: Convert TBL, TBX to decodetree target/arm: Convert UZP, TRN, ZIP to decodetree target/arm:

[PATCH 03/17] target/arm: Convert TBL, TBX to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 47 ++ target/arm/tcg/a64.decode | 4 +++ 2 files changed, 18 insertions(+), 33 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6ca24d9842..

[PATCH 09/17] target/arm: Convert MOVI, FMOV, ORR, BIC (vector immediate) to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 117 ++--- target/arm/tcg/a64.decode | 9 +++ 2 files changed, 59 insertions(+), 67 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 6582816e4e.

[PATCH 02/17] target/arm: Convert EXT to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 121 + target/arm/tcg/a64.decode | 5 ++ 2 files changed, 53 insertions(+), 73 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e4c8a20f39..

[PATCH 07/17] target/arm: Convert FMAXNMV, FMINNMV, FMAXV, FMINV to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 176 ++--- target/arm/tcg/a64.decode | 14 +++ 2 files changed, 67 insertions(+), 123 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 055ba4695e

[PATCH 04/17] target/arm: Convert UZP, TRN, ZIP to decodetree

Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 158 ++--- target/arm/tcg/a64.decode | 9 ++ 2 files changed, 77 insertions(+), 90 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7e3bde93fe..

[PATCH 01/17] target/arm: Use tcg_gen_extract2_i64 for EXT

The extract2 tcg op performs the same operation as the do_ext64 function. Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 23 +++ 1 file changed, 3 insertions(+), 20 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64

Re: [PATCH] intel_iommu: Use the latest fault reasons defined by spec

On Wed, Jul 17, 2024 at 03:30:03AM +, Duan, Zhenzhong wrote: > Hi Michael, Jason, > > Based on Yi's analysis, is keeping current VERSION value acceptable for you? I think it's fine. > Look forward to your comments, currently this open blocks us from sending the > next version. > > Thanks >

[PATCH v2 2/3] target/arm: Use FPST_F16 for SME FMOPA (widening)

This operation has float16 inputs and thus must use the FZ16 control not the FZ control. Cc: qemu-sta...@nongnu.org Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)") Reported-by: Daniyal Khan Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2374 Signed-off-by: Richard He

[PATCH v2 1/3] target/arm: Use float_status copy in sme_fmopa_s

From: Daniyal Khan We made a copy above because the fp exception flags are not propagated back to the FPST register, but then failed to use the copy. Cc: qemu-sta...@nongnu.org Fixes: 558e956c719 ("target/arm: Implement FMOPA, FMOPS (non-widening)") Signed-off-by: Daniyal Khan [rth: Split from

[PATCH v2 3/3] tests/tcg/aarch64: Add test cases for SME FMOPA (widening)

From: Daniyal Khan Signed-off-by: Daniyal Khan Message-Id: 172090222034.13953.1688870870882292209...@git.sr.ht [rth: Split test from a larger patch, tidy assembly] Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- tests/tcg/aarch64/sme-fmopa-1.c | 63

[PATCH v2 0/3] target/arm: Fixes for SME FMOPA (#2373)

Changes for v2: - Apply r-b. - Add license headers to two test cases. r~ Daniyal Khan (2): target/arm: Use float_status copy in sme_fmopa_s tests/tcg/aarch64: Add test cases for SME FMOPA (widening) Richard Henderson (1): target/arm: Use FPST_F16 for SME FMOPA (widening) target/arm/t

Re: [PULL 00/11] SD/MMC patches for 2024-07-16

https://github.com/philmd/qemu.git tags/sdmmc-20240716 for you to fetch changes up to c8cb19876d3e29bffd7ffd87586ff451f97f5f46: hw/sd/sdcard: Support boot area in emmc image (2024-07-16 20:30:15 +0200) Ignored checkpatch error: WARNING: line over 80 characters #109: FILE: hw/sd/sd.c:500:

Re: [PULL 00/13] Misc HW/UI patches for 2024-07-16

https://github.com/philmd/qemu.git tags/hw-misc-20240716 for you to fetch changes up to 644a52778a90581dbda909f38b9eaf71501fd9cd: system/physmem: use return value of ram_block_discard_require() as errno (2024-07-16 20:04:08 +0200) Ignored checkpatch error: WARNING: line over 80 characters

[PULL 04/20] disas: Fix build against Capstone v6

From: Gustavo Romero Capstone v6 made major changes, such as renaming for AArch64, which broke programs using the old headers, like QEMU. However, Capstone v6 provides the CAPSTONE_AARCH64_COMPAT_HEADER compatibility definition allowing to build against v6 with the old definitions, so fix the QEM

[PULL 08/20] docs: Update description of 'user=username' for '-run-with'

From: Boqiao Fu The description of '-runas' and '-run-with' didn't explain that QEMU will use setuid/setgid to implement the option, so the user might get confused if using 'elevateprivileges=deny' as well. Since '-runas' is going to be deprecated and replaced by '-run-with' in the coming qemu9.

[PULL 02/20] Revert "qemu-char: do not operate on sources from finalize callbacks"

From: Sergey Dyasli This reverts commit 2b316774f60291f57ca9ecb6a9f0712c532cae34. After 038b4217884c ("Revert "chardev: use a child source for qio input source"") we've been observing the "iwp->src == NULL" assertion triggering periodically during the initial capabilities querying by libvirtd. O

[PULL 16/20] target/i386/tcg: Introduce x86_mmu_index_{kernel_,}pl

From: Richard Henderson Disconnect mmu index computation from the current pl as stored in env->hflags. Signed-off-by: Richard Henderson Link: https://lore.kernel.org/r/20240617161210.4639-2-richard.hender...@linaro.org Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 11 ++- targ

[PULL 10/20] hpet: fix HPET_TN_SETVAL for high 32-bits of the comparator

Commit 3787324101b ("hpet: Fix emulation of HPET_TN_SETVAL (Jan Kiszka)", 2009-04-17) applied the fix only to the low 32-bits of the comparator, but it should be done for the high bits as well. Otherwise, the high 32-bits of the comparator cannot be written and they remain fixed to 0x. Co

[PULL 15/20] target/i386/tcg: Reorg push/pop within seg_helper.c

From: Richard Henderson Interrupts and call gates should use accesses with the DPL as the privilege level. While computing the applicable MMU index is easy, the harder thing is how to plumb it in the code. One possibility could be to add a single argument to the PUSH* macros for the privilege l

[PULL 03/20] cpu: Free queued CPU work

From: Akihiko Odaki Running qemu-system-aarch64 -M virt -nographic and terminating it will result in a LeakSanitizer error due to remaining queued CPU work so free it. Signed-off-by: Akihiko Odaki Link: https://lore.kernel.org/r/20240714-cpu-v1-1-19c2f8de2...@daynix.com Signed-off-by: Paolo Bon

[PULL 13/20] target/i386/tcg: Allow IRET from user mode to user mode with SMAP

This fixes a bug wherein i386/tcg assumed an interrupt return using the IRET instruction was always returning from kernel mode to either kernel mode or user mode. This assumption is violated when IRET is used as a clever way to restore thread state, as for example in the dotnet runtime. There, IRET

[PULL 07/20] qemu/timer: Add host ticks function for LoongArch

From: Song Gao Signed-off-by: Song Gao Link: https://lore.kernel.org/r/20240716031500.4193498-1-gaos...@loongson.cn Signed-off-by: Paolo Bonzini --- include/qemu/timer.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/qemu/timer.h b/include/qemu/timer.h index 5ce83c79112..

[PULL 11/20] target/i386/tcg: fix POP to memory in long mode

In long mode, POP to memory will write a full 64-bit value. However, the call to gen_writeback() in gen_POP will use MO_32 because the decoding table is incorrect. The bug was latent until commit aea49fbb01a ("target/i386: use gen_writeback() within gen_POP()", 2024-06-08), and then became visibl

[PULL 12/20] target/i386/tcg: Remove SEG_ADDL

From: Richard Henderson This truncation is now handled by MMU_*32_IDX. The introduction of MMU_*32_IDX in fact applied correct 32-bit wraparound to 16-bit accesses with a high segment base (e.g. big real mode or vm86 mode), which did not use SEG_ADDL. Signed-off-by: Richard Henderson Link: h

[PULL 18/20] target/i386/tcg: check for correct busy state before switching to a new task

This step is listed in the Intel manual: "Checks that the new task is available (call, jump, exception, or interrupt) or busy (IRET return)". The AMD manual lists the same operation under the "Preventing recursion" paragraph of "12.3.4 Nesting Tasks", though it is not clear if the processor checks

[PULL 20/20] target/i386/tcg: save current task state before loading new one

This is how the steps are ordered in the manual. EFLAGS.NT is overwritten after the fact in the saved image. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/seg_helper.c | 85 +++- 1 file changed, 45 insertions(+), 40 deletions(-)

[PULL 01/20] i386/sev: Don't allow automatic fallback to legacy KVM_SEV*_INIT

From: Michael Roth Currently if the 'legacy-vm-type' property of the sev-guest object is 'on', QEMU will attempt to use the newer KVM_SEV_INIT2 kernel interface in conjunction with the newer KVM_X86_SEV_VM and KVM_X86_SEV_ES_VM KVM VM types. This can lead to measurement changes if, for instance,

[PULL 17/20] target/i386/tcg: Compute MMU index once

Add the MMU index to the StackAccess struct, so that it can be cached or (in the next patch) computed from information that is not in CPUX86State. Co-developed-by: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/seg_helper.c | 35

[PULL 06/20] scsi: fix regression and honor bootindex again for legacy drives

From: Fiona Ebner Commit 3089637461 ("scsi: Don't ignore most usb-storage properties") removed the call to object_property_set_int() and thus the 'set' method for the bootindex property was also not called anymore. Here that method is device_set_bootindex() (as configured by scsi_dev_instance_ini

[PULL 14/20] target/i386/tcg: use PUSHL/PUSHW for error code

Do not pre-decrement esp, let the macros subtract the appropriate operand size. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini --- target/i386/tcg/seg_helper.c | 16 +++- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/target/i386/tcg/seg_helper.c b/target

[PULL 09/20] hpet: fix clamping of period

When writing a new period, the clamping should use a maximum value rather tyhan a bit mask. Also, when writing the high bits new_val is shifted right by 32, so the maximum allowed period should also be shifted right. Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 6 -- 1 file changed, 4

[PULL 19/20] target/i386/tcg: use X86Access for TSS access

This takes care of probing the vaddr range in advance, and is also faster because it avoids repeated TLB lookups. It also matches the Intel manual better, as it says "Checks that the current (old) TSS, new TSS, and all segment descriptors used in the task switch are paged into system memory"; note

[PULL 00/20] i386, bugfix changes for QEMU 9.1 soft freeze

The following changes since commit 959269e910944c03bc13f300d65bf08b060d5d0f: Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into staging (2024-07-16 06:45:23 +1000) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fe

[PULL 05/20] hw/scsi/lsi53c895a: bump instruction limit in scripts processing to fix regression

From: Fiona Ebner Commit 9876359990 ("hw/scsi/lsi53c895a: add timer to scripts processing") reduced the maximum allowed instruction count by a factor of 100 all the way down to 100. This causes the "Check Point R81.20 Gaia" appliance [0] to fail to boot after fully finishing the installation via

Re: [PATCH] intel_iommu: Use the latest fault reasons defined by spec

On Wed, Jul 17, 2024 at 11:30 AM Duan, Zhenzhong wrote: > > Hi Michael, Jason, > > Based on Yi's analysis, is keeping current VERSION value acceptable for you? Fine with me. > Look forward to your comments, currently this open blocks us from sending the > next version. > > Thanks > Zhenzhong T

[RFC 3/4] hw/loongarch: Add KVM pch pic device support

Added pch_pic interrupt controller for kvm emulation. The main process is to send the command word for creating an pch_pic device to the kernel, Delivers the pch pic interrupt controller configuration register base address to the kernel. When the VM is saved, the ioctl obtains the pch_pic interrupt

[RFC 2/4] hw/loongarch: Add KVM extioi device support

Added extioi interrupt controller for kvm emulation. The main process is to send the command word for creating an extioi device to the kernel. When the VM is saved, the ioctl obtains the related data of the extioi interrupt controller in the kernel and saves it. When the VM is recovered, the saved

[RFC 0/4] Added Interrupt controller emulation for loongarch kvm

Before this, the interrupt controller simulation has been completed in the user mode program. In order to reduce the loss caused by frequent switching of the virtual machine monitor from kernel mode to user mode when the guest accesses the interrupt controller, we add the interrupt controller simul

[RFC 4/4] hw/loongarch: Add KVM pch msi device support

Added pch_msi interrupt controller handling during kernel emulation of irq chip. Signed-off-by: Xianglai Li --- Cc: Paolo Bonzini Cc: Song Gao Cc: Huacai Chen Cc: Jiaxun Yang Cc: "Michael S. Tsirkin" Cc: Cornelia Huck Cc: k...@vger.kernel.org Cc: Bibo Mao hw/intc/loongarch_pch_ms

[RFC 1/4] hw/loongarch: Add KVM IPI device support

Added ipi interrupt controller for kvm emulation. The main process is to send the command word for creating an ipi device to the kernel. When the VM is saved, the ioctl obtains the ipi interrupt controller data in the kernel and saves it. When the VM is recovered, the saved data is sent to the kern

RE: [PATCH] intel_iommu: Use the latest fault reasons defined by spec

Hi Michael, Jason, Based on Yi's analysis, is keeping current VERSION value acceptable for you? Look forward to your comments, currently this open blocks us from sending the next version. Thanks Zhenzhong >-Original Message- >From: Liu, Yi L >Subject: Re: [PATCH] intel_iommu: Use the l

RE: [PATCH 3/6] virtio-iommu: Free [host_]resv_ranges on unset_iommu_devices

>-Original Message- >From: Eric Auger >Subject: [PATCH 3/6] virtio-iommu: Free [host_]resv_ranges on >unset_iommu_devices > >We are currently missing the deallocation of the [host_]resv_regions >in case of hot unplug. Also to make things more simple let's rule >out the case where multip

RE: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain creation

>-Original Message- >From: Joao Martins >Subject: Re: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain >creation > >On 16/07/2024 17:44, Joao Martins wrote: >> On 16/07/2024 17:04, Eric Auger wrote: >>> Hi Joao, >>> >>> On 7/12/24 13:46, Joao Martins wrote: There's generally two

Re: [PATCH] target/i386: do not crash if microvm guest uses SGX CPUID leaves

Hi Paolo, On Tue, Jul 16, 2024 at 06:55:30PM +0200, Paolo Bonzini wrote: > Date: Tue, 16 Jul 2024 18:55:30 +0200 > From: Paolo Bonzini > Subject: [PATCH] target/i386: do not crash if microvm guest uses SGX CPUID > leaves > X-Mailer: git-send-email 2.45.2 > > sgx_epc_get_section assumes a PC pla

RE: [PATCH v4 11/12] vfio/migration: Don't block migration device dirty tracking is unsupported

>-Original Message- >From: Joao Martins >Subject: [PATCH v4 11/12] vfio/migration: Don't block migration device dirty >tracking is unsupported > >By default VFIO migration is set to auto, which will support live >migration if the migration capability is set *and* also dirty page >tracki

RE: [PATCH v4 09/12] vfio/iommufd: Implement VFIOIOMMUClass::set_dirty_tracking support

>-Original Message- >From: Joao Martins >Subject: [PATCH v4 09/12] vfio/iommufd: Implement >VFIOIOMMUClass::set_dirty_tracking support > >ioctl(iommufd, IOMMU_HWPT_SET_DIRTY_TRACKING, arg) is the UAPI that >enables or disables dirty page tracking. It is used if the hwpt >has been create

RE: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain creation

>-Original Message- >From: Joao Martins >Subject: [PATCH v4 05/12] vfio/iommufd: Introduce auto domain creation > >There's generally two modes of operation for IOMMUFD: > >* The simple user API which intends to perform relatively simple things >with IOMMUs e.g. DPDK. It generally create

[PATCH v2 5/9] docs/sphinx: add CSS styling for qmp-example directive

From: Harmonie Snow Add CSS styling for qmp-example directives to increase readability and consistently style all example blocks. Signed-off-by: Harmonie Snow Signed-off-by: John Snow Acked-by: Markus Armbruster --- docs/sphinx-static/theme_overrides.css | 49 ++ 1 fi

[PATCH v2 2/9] docs/qapidoc: factor out do_parse()

Factor out the compatibility parser helper into a base class, so it can be shared by other directives. Signed-off-by: John Snow Reviewed-by: Markus Armbruster --- docs/sphinx/qapidoc.py | 32 +++- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/docs/s

[PATCH v2 0/9] qapi: convert example sections to qmp-example rST directives

This patchset focuses on converting example sections to rST directives using a new `.. qmp-example::` directive. V2: - Rebased on origin/master; converted one more example - Fixed (most?) minor nits from last review - Didn't address lack of newline in text mode or enhanced lexer (yet) Changes

[PATCH v2 7/9] qapi: convert "Example" sections with titles

When an Example section has a brief explanation, convert it to a qmp-example:: section using the :title: option. Rule of thumb: If the title can fit on a single line and requires no rST markup, it's a good candidate for using the :title: option of qmp-example. In this patch, trailing punctuation

[PATCH v2 9/9] qapi: remove "Example" doc section

Fully eliminate the "Example" sections in QAPI doc blocks now that they have all been converted to arbitrary rST syntax using the ".. qmp-example::" directive. Update tests to match. Migrating to the new syntax --- The old "Example:" or "Examples:" section syntax is now ca

[PATCH v2 8/9] qapi: convert "Example" sections with longer prose

These examples require longer explanations or have explanations that require markup to look reasonable when rendered and so use the longer form of the ".. qmp-example::" directive. By using the :annotated: option, the content in the example block is assumed *not* to be a code block literal and is

[PATCH v2 6/9] qapi: convert "Example" sections without titles

Use the no-option form of ".. qmp-example::" to convert any Examples that do not have any form of caption or explanation whatsoever. Note that in a few cases, example sections are split into two or more separate example blocks. This is only done stylistically to create a delineation between two or

[PATCH v2 1/9] [DO-NOT-MERGE]: Add some ad-hoc linting helpers.

These aren't ready for upstream inclusion, because they do not properly manage version dependencies, execution environment and so on. These are just the tools I use in my Own Special Environment :tm: for testing and debugging. They've been tested only on Fedora 38 for right now, which means: Pyth

[PATCH v2 3/9] docs/qapidoc: create qmp-example directive

This is a directive that creates a syntactic sugar for creating "Example" boxes very similar to the ones already used in the bitmaps.rst document, please see e.g. https://www.qemu.org/docs/master/interop/bitmaps.html#creation-block-dirty-bitmap-add In its simplest form, when a custom title is not

[PATCH v2 4/9] docs/qapidoc: add QMP highlighting to annotated qmp-example blocks

For any code literal blocks inside of a qmp-example directive, apply and enforce the QMP lexer/highlighter to those blocks. This way, you won't need to write: ``` .. qmp-example:: :annotated: Blah blah .. code-block:: QMP -> { "lorem": "ipsum" } ``` But instead, simply: ``` ..

RE: [PATCH v4 07/12] vfio/{iommufd,container}: Initialize HostIOMMUDeviceCaps during attach_device()

>-Original Message- >From: Joao Martins >Subject: [PATCH v4 07/12] vfio/{iommufd,container}: Initialize >HostIOMMUDeviceCaps during attach_device() > >Fetch IOMMU hw raw caps behind the device and thus move the >HostIOMMUDevice::realize() to be done during the attach of the device. It >a

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Wed, Jul 17, 2024 at 9:29 AM Jason Wang wrote: > On Wed, Jul 17, 2024 at 9:24 AM Yong Huang wrote: > > > > > > > > On Fri, Jul 12, 2024 at 10:01 AM Jason Wang wrote: > >> > >> On Wed, Jul 10, 2024 at 5:05 PM Yong Huang > wrote: > >> > > >> > > >> > > >> > On Wed, Jul 10, 2024 at 3:36 PM Jas

RE: [PATCH v4 04/12] vfio/iommufd: Return errno in iommufd_cdev_attach_ioas_hwpt()

>-Original Message- >From: Joao Martins >Subject: [PATCH v4 04/12] vfio/iommufd: Return errno in >iommufd_cdev_attach_ioas_hwpt() > >In preparation to implement auto domains have the attach function >return the errno it got during domain attach instead of a bool. > >-EINVAL is tracked t

RE: [PATCH v4 02/12] vfio/iommufd: Don't initialize nor set a HOST_IOMMU_DEVICE with mdev

Hello Joao, >-Original Message- >From: Joao Martins >Subject: [PATCH v4 02/12] vfio/iommufd: Don't initialize nor set a >HOST_IOMMU_DEVICE with mdev > >mdevs aren't "physical" devices and when asking for backing IOMMU info, it >fails the entire provisioning of the guest. Fix that by skipp

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Wed, Jul 17, 2024 at 9:24 AM Yong Huang wrote: > > > > On Fri, Jul 12, 2024 at 10:01 AM Jason Wang wrote: >> >> On Wed, Jul 10, 2024 at 5:05 PM Yong Huang wrote: >> > >> > >> > >> > On Wed, Jul 10, 2024 at 3:36 PM Jason Wang wrote: >> >> >> >> On Wed, Jul 10, 2024 at 2:26 PM Yong Huang wrot

Re: [PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

On Fri, Jul 12, 2024 at 10:01 AM Jason Wang wrote: > On Wed, Jul 10, 2024 at 5:05 PM Yong Huang wrote: > > > > > > > > On Wed, Jul 10, 2024 at 3:36 PM Jason Wang wrote: > >> > >> On Wed, Jul 10, 2024 at 2:26 PM Yong Huang > wrote: > >> > > >> > > >> > > >> > On Wed, Jul 10, 2024 at 11:44 AM Ja

Re: [RFC v2] virtio-net: check the mac address for vdpa device

On Tue, Jul 16, 2024 at 2:09 PM Cindy Lu wrote: > > On Tue, 16 Jul 2024 at 13:37, Jason Wang wrote: > > > > On Tue, Jul 16, 2024 at 9:14 AM Cindy Lu wrote: > > > > > > When using a VDPA device, it is important to ensure that the MAC address > > > in the hardware matches the MAC address from the

Re: [PATCH v5 08/13] migration/multifd: Add new migration option for multifd DSA offloading.

Yichen Wang writes: > On Thu, Jul 11, 2024 at 2:53 PM Yichen Wang wrote: > >> diff --git a/migration/options.c b/migration/options.c >> index 645f55003d..f839493016 100644 >> --- a/migration/options.c >> +++ b/migration/options.c >> @@ -29,6 +29,7 @@ >> #include "ram.h" >> #include "options.h"

Re: [PATCH 0/2] Postcopy migration and vhost-user errors

On Tue, Jul 16, 2024 at 03:44:54PM +0530, Prasad Pandit wrote: > Hello Peter, > > On Mon, 15 Jul 2024 at 19:10, Peter Xu wrote: > > IMHO it's better we debug and fix all the issues before merging this one, > > otherwise we may overlook something. > > * Well we don't know where the issue is, not

Re: [RFC PATCH] gdbstub: Re-factor gdb command extensions

On 7/17/24 02:55, Alex Bennée wrote: Are you expecting the same GdbCmdParseEntry object to be registered multiple times? Can we fix that at a higher level? Its basically a hack to deal with the fact everything is tied to the CPUObject so we register everything multiple times. We could do a if

Re: [PATCH v5 00/13] WIP: Use Intel DSA accelerator to offload zero page checking in multifd live migration.

Yichen Wang writes: > v5 > * Rebase on top of 39a032cea23e522268519d89bb738974bc43b6f6. > * Rename struct definitions with typedef and CamelCase names; > * Add build and runtime checks about DSA accelerator; > * Address all comments from v4 reviews about typos, licenses, comments, > error reporti

Re: [PATCH 1/8] aspeed: Change type of eMMC device

On 4/7/24 07:36, Cédric Le Goater wrote: From: Cédric Le Goater The QEMU device representing the eMMC device of machine is currently created with type SD_CARD. Change the type to EMMC now that it is available. Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 9 + 1 file change

Re: [PATCH v2] target/loongarch/gdbstub: Add vector registers support

On 11/7/24 04:44, Song Gao wrote: GDB already support LoongArch vector extension[1], QEMU gdb adds LoongArch vector registers support, so that users can use 'info all-registers' to get all vector registers values. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f383a3d5

Re: [PATCH v3 00/27] qemu-img: refersh options and --help handling, cleanups

A friendly ping? 24.04.2024 11:50, Michael Tokarev wrote: Quite big patchset trying to implement normal, readable qemu-img --help (and qemu-img COMMAND --help) output with readable descriptions, and adding many long options in the process. In the end I stopped using qemu-img-opts.hx in qemu-img

Re: [PATCH 4/5] qapi/sockets: Move deprecation note out of SocketAddress doc comment

On 11/7/24 13:22, Markus Armbruster wrote: Doc comments are reference documentation for users of QMP. SocketAddress's doc comment contains a deprecation note advising developers to use SocketAddress for new code. Irrelevant for users of QMP. Move the note out of the doc comment. Signed-off-by:

Re: [PATCH 3/5] qapi/machine: Clarify query-uuid value when none has been specified

On 16/7/24 20:12, Markus Armbruster wrote: John Snow writes: On Thu, Jul 11, 2024, 7:22 AM Markus Armbruster wrote: When no UUID has been specified, query-uuid returns {"UUID": "----"} The doc comment calls this "a null UUID", which I find less than cl

Re: [PATCH v3 9/9] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c

On 7/16/24 21:56, Michael Kowal wrote: From: Frederic Barrat Moving xive2_nvp_pic_print_info() align with the other "pic_print_info" functions and allows us to call functions internal to xive2.c. ok but I don't see the difference in the patch. Am I missing something ? In XIVE Gen 2 there w

Re: [PATCH v3 4/9] pnv/xive2: Add NVG and NVC to cache watch facility

On 7/16/24 21:56, Michael Kowal wrote: From: Frederic Barrat The cache watch facility uses the same register interface to handle entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX specification' register tells the table type. So far, that bit-field was not read and the code assu

Re: [PATCH v3 1/9] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support

On 7/16/24 21:56, Michael Kowal wrote: From: Frederic Barrat XIVE offers a 'cache watch facility', which allows software to read/update a potentially cached table entry with no software lock. There's one such facility in the Virtualization Controller (VC) to update the ESB and END entries and o

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