Hello,
This change introduced a regression on s390x. I could have spotted it
earlier. Sorry about that. Here is the scenario,
QEMU now creates automatically the PCI device objects representing the
VFs when the PF device is realized in pcie_sriov_pf_init(). This is
good to report errors early but
From: Richard Henderson
Disconnect mmu index computation from the current pl
as stored in env->hflags.
Signed-off-by: Richard Henderson
Link:
https://lore.kernel.org/r/20240617161210.4639-2-richard.hender...@linaro.org
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 11 ++-
targ
Add the MMU index to the StackAccess struct, so that it can be cached
or (in the next patch) computed from information that is not in
CPUX86State.
Co-developed-by: Richard Henderson
Signed-off-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 35
This includes bugfixes:
- allowing IRET from user mode to user mode with SMAP (do not use implicit
kernel accesses, which break if the stack is in userspace)
- use DPL-level accesses for interrupts and call gates
- various fixes for task switching
And two related cleanups: computing MMU index
This fixes a bug wherein i386/tcg assumed an interrupt return using
the IRET instruction was always returning from kernel mode to either
kernel mode or user mode. This assumption is violated when IRET is used
as a clever way to restore thread state, as for example in the dotnet
runtime. There, IRET
From: Richard Henderson
This truncation is now handled by MMU_*32_IDX. The introduction of
MMU_*32_IDX in fact applied correct 32-bit wraparound to 16-bit accesses
with a high segment base (e.g. big real mode or vm86 mode), which did
not use SEG_ADDL.
Signed-off-by: Richard Henderson
Link:
h
This is how the steps are ordered in the manual. EFLAGS.NT is
overwritten after the fact in the saved image.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 85 +++-
1 file changed, 45 insertions(+), 40 deletions(-)
diff --git a/target/i386/tcg/s
From: Richard Henderson
Interrupts and call gates should use accesses with the DPL as
the privilege level. While computing the applicable MMU index
is easy, the harder thing is how to plumb it in the code.
One possibility could be to add a single argument to the PUSH* macros
for the privilege l
This takes care of probing the vaddr range in advance, and is also faster
because it avoids repeated TLB lookups. It also matches the Intel manual
better, as it says "Checks that the current (old) TSS, new TSS, and all
segment descriptors used in the task switch are paged into system memory";
note
Do not pre-decrement esp, let the macros subtract the appropriate
operand size.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 497
This fixes a bug wherein i386/tcg assumed an interrupt return using
the CALL or JMP instructions were always going from kernel or user mode to
kernel mode, when using a call gate. This assumption is violated if
the call gate has a DPL that is greater than 0.
In addition, the stack accesses should
This step is listed in the Intel manual: "Checks that the new task is available
(call, jump, exception, or interrupt) or busy (IRET return)".
The AMD manual lists the same operation under the "Preventing recursion"
paragraph of "12.3.4 Nesting Tasks", though it is not clear if the processor
checks
On Wed, Jul 10, 2024 at 11:44 AM Jason Wang wrote:
> On Tue, Jul 9, 2024 at 10:56 AM Yong Huang wrote:
> >
> >
> >
> > On Tue, Jul 9, 2024 at 10:41 AM Jason Wang wrote:
> >>
> >> On Mon, Jul 8, 2024 at 1:17 PM Yong Huang
> wrote:
> >> >
> >> >
> >> >
> >> > On Mon, Jul 8, 2024 at 11:21 AM Jaso
On Wed, Jul 10, 2024 at 05:15:18AM +0200, David Hildenbrand wrote:
> On 04.07.24 23:30, Michael S. Tsirkin wrote:
> > Currently, if VIRTIO_BALLOON_F_FREE_PAGE_HINT is off but
> > VIRTIO_BALLOON_F_REPORTING is on, then the reporting vq
> > gets number 3 while spec says it's number 4.
> > It happens
On 2024/7/10 下午12:00, Jiaxun Yang wrote:
在2024年7月9日七月 下午8:04，maobibo写道：
Hi Philippe/Jiaxun,
Could you do me a favor giving a review about this patch?
Hi Bibo,
I’m currently traveling, will test and review next week.
I’m not really convinced to give a R-b but I’m fine with a T-b.
That
John Snow writes:
> On Tue, Jul 9, 2024 at 6:52 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Fully eliminate the "Example" sections in QAPI doc blocks now that they
>> > have all been converted to arbitrary rST syntax using the
>> > ".. qmp-example::" directive. Update tests to ma
On 09/07/2024 23:17, Minwoo Im wrote:
> Caution: External email. Do not open attachments or click links, unless this
> email comes from a known sender and you know the content is safe.
>
>
> On 24-07-09 11:58:53, CLEMENT MATHIEU--DRIF wrote:
>>
>> On 09/07/2024 12:15, Minwoo Im wrote:
>>> Cautio
On 7/9/24 11:32 PM, Philippe Mathieu-Daudé wrote:
On 5/7/24 17:52, Philippe Mathieu-Daudé wrote:
On 5/7/24 15:28, Philippe Mathieu-Daudé wrote:
On 5/7/24 07:38, Cédric Le Goater wrote:
On 7/5/24 5:41 AM, Andrew Jeffery wrote:
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
From: C
The function ufs_is_mcq_reg() and ufs_is_mcq_op_reg() only evaluated
the range of the mcq_reg and mcq_op_reg offset, which is defined as
a constant. Therefore, it was possible for them to return true
even though the ufs device is configured to not support the mcq.
This could cause ufs_mmio_read()/u
On 7/9/24 11:39 PM, Philippe Mathieu-Daudé wrote:
On 9/7/24 17:58, Cédric Le Goater wrote:
On 7/9/24 5:25 PM, Philippe Mathieu-Daudé wrote:
Since v42:
- Stick to spec v4.3 (re-simplified EXT_CSD register & migrate)
- Fill CID register
- Few changes to CSD register
- Implement 'boot-mode' reset
John Snow writes:
> On Tue, Jul 9, 2024 at 6:34 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > From: Harmonie Snow
>> >
>> > Add CSS styling for qmp-example directives to increase readability and
>> > consistently style all example blocks.
>> >
>> > Signed-off-by: Harmonie Snow
>>
KVM_SET_PMU_EVENT_FILTER of x86 KVM supports masked events mode, which
accepts masked entry format event to flexibly represent a group of PMU
events.
Support masked entry format in kvm-pmu-filter object and handle this in
i386 kvm codes.
Signed-off-by: Zhao Liu
---
accel/kvm/kvm-pmu.c | 91 ++
The select&umask is the common way for x86 to identify the PMU event,
so support this way as the "x86-default" format in kvm-pmu-filter
object.
Signed-off-by: Zhao Liu
---
accel/kvm/kvm-pmu.c | 62
include/sysemu/kvm-pmu.h | 13 +
qapi/kvm.js
Filter PMU events with raw format in i386 code.
For i386, raw format indicates that the PMU event code is already
encoded according to the KVM ioctl requirements, and can be delivered
directly to KVM without additional encoding work.
Signed-off-by: Zhao Liu
---
include/sysemu/kvm_int.h | 2
Introduce the kvm-pmu-filter object and support the PMU event with raw
format.
The raw format, as a native PMU event code representation, can be used
for several architectures.
Considering that PMU event related fields are commonly used in
hexadecimal, define KVMPMURawEventVariant, KVMPMUFilterEv
KVM_SET_PMU_EVENT_FILTER of x86 KVM allows user to configure x86 fixed
function counters by a bitmap.
Add the support of x86-fixed-counter in kvm-pmu-filter object and handle
this in i386 kvm codes.
Signed-off-by: Zhao Liu
---
accel/kvm/kvm-pmu.c | 71 ++
Hi QEMU maintainers, arm and PMU folks,
I picked up Shaoqing's previous work [1] on the KVM PMU filter for arm,
and now is trying to support this feature for x86 with a JSON-compatible
API.
While arm and x86 use different KVM ioctls to configure the PMU filter,
considering they all have similar i
On Thu, Jul 04, 2024 at 11:53:33AM +0200, Paolo Bonzini wrote:
> On Thu, Jul 4, 2024 at 11:39 AM Daniel P. Berrangé
> wrote:
> > > The debug_swap parameter simply could not be enabled in the old API
> > > without breaking measurements. The new API *is the fix* to allow using
> > > it (though QEMU
Currently if the 'legacy-vm-type' property of the sev-guest object is
'on', QEMU will attempt to use the newer KVM_SEV_INIT2 kernel
interface in conjunction with the newer KVM_X86_SEV_VM and
KVM_X86_SEV_ES_VM KVM VM types.
This can lead to measurement changes if, for instance, an SEV guest was
cre
On Wed, Jul 10, 2024 at 1:30 PM Richard Henderson
wrote:
>
> The current pairing of tlb_vaddr_to_host with extra is either
> inefficient (user-only, with page_check_range) or incorrect
> (system, with probe_pages).
>
> For proper non-fault behaviour, use probe_access_flags with
> its nonfault para
在2024年7月9日七月 下午8:04，maobibo写道：
> Hi Philippe/Jiaxun,
>
> Could you do me a favor giving a review about this patch?
Hi Bibo,
I’m currently traveling, will test and review next week.
I’m not really convinced to give a R-b but I’m fine with a T-b.
Thanks
>
> Regards
> Bibo Mao
>
> On 2024/7/4
On Tue, Jul 9, 2024 at 10:56 AM Yong Huang wrote:
>
>
>
> On Tue, Jul 9, 2024 at 10:41 AM Jason Wang wrote:
>>
>> On Mon, Jul 8, 2024 at 1:17 PM Yong Huang wrote:
>> >
>> >
>> >
>> > On Mon, Jul 8, 2024 at 11:21 AM Jason Wang wrote:
>> >>
>> >> On Sat, Jul 6, 2024 at 4:30 AM Hyman Huang wrote:
Mark the reserve_addr check unlikely. Use tlb_vaddr_to_host
instead of probe_write, relying on the memset itself to test
for page writability. Use set/clear_helper_retaddr so that
we can properly unwind on segfault.
With this, a trivial loop around guest memset will spend
nearly 50% of runtime w
Use of these in helpers goes hand-in-hand with tlb_vaddr_to_host
and other probing functions.
Signed-off-by: Richard Henderson
---
accel/tcg/user-retaddr.h | 28
include/exec/cpu_ldst.h | 34 ++
accel/tcg/cpu-exec.c | 3 ---
acce
Avoid a race condition with munmap in another thread.
Use around blocks that exclusively use "host_fn".
Keep the blocks as small as possible, but without setting
and clearing for every operation on one page.
Signed-off-by: Richard Henderson
---
target/arm/tcg/sme_helper.c | 16
In a completely artifical memset benchmark object_dynamic_cast_assert
dominates the profile, even above guest address resolution and
the underlying host memset.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ar
Merge the two and pass the mmu_idx directly from translation.
Swap the argument order in dcbz_common to avoid extra swaps.
Signed-off-by: Richard Henderson
---
target/ppc/helper.h | 3 +--
target/ppc/mem_helper.c | 14 --
target/ppc/translate.c | 4 ++--
3 files changed, 7 ins
Supercedes: 20240702234155.2106399-1-richard.hender...@linaro.org
("[PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS")
Supercedes: 20240702234659.2106870-1-richard.hender...@linaro.org
("[PATCH 0/4] target/ppc: Cleanups for dcbz")
After looking at the first dc zva patch set again, I ca
Eliminate the ifdef by using a predicate that is
always true with CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 6cdb
The current pairing of tlb_vaddr_to_host with extra is either
inefficient (user-only, with page_check_range) or incorrect
(system, with probe_pages).
For proper non-fault behaviour, use probe_access_flags with
its nonfault parameter set to true.
Signed-off-by: Richard Henderson
---
target/riscv
From: BALATON Zoltan
Instead of passing a bool and select a value within dcbz_common() let
the callers pass in the right value to avoid this conditional
statement. On PPC dcbz is often used to zero memory and some code uses
it a lot. This change improves the run time of a test case that copies
me
Avoid a race condition with munmap in another thread.
For access_memset and access_memmove, manage the value
within the helper. For uses of access_{get,set}_byte,
manage the value across the for loops.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 43 +
Use these in helper_dc_dva and the FEAT_MOPS routines to
avoid a race condition with munmap in another thread.
Signed-off-by: Richard Henderson
---
target/arm/tcg/helper-a64.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/arm/tcg/helper-a64.c b/target
The 970 logic does not apply to dcbzep, which is an e500 insn.
Signed-off-by: Richard Henderson
---
target/ppc/mem_helper.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 361fd72226..506
Invert the conditional, indent the block, and use the macro
that expands to true for user-only.
Signed-off-by: Richard Henderson
---
target/s390x/tcg/mem_helper.c | 54 +--
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/target/s390x/tcg/mem_helper
We can determine at translation time whether the insn is or
is not dbczl. We must retain a runtime check against the
HID5 register, but we can move that to a separate function
that never affects other ppc models.
Signed-off-by: Richard Henderson
---
target/ppc/helper.h | 7 +--
target/
On 04.07.24 23:30, Michael S. Tsirkin wrote:
Currently, if VIRTIO_BALLOON_F_FREE_PAGE_HINT is off but
VIRTIO_BALLOON_F_REPORTING is on, then the reporting vq
gets number 3 while spec says it's number 4.
It happens to work because the linux virtio pci driver
is *also* out of spec.
To fix:
1. add
在 2024/7/10 上午10:43, Feiyang Chen 写道:
ping
https://lore.kernel.org/qemu-devel/20240628033357.50027-1-chris.chenfeiy...@gmail.com/
Hi,
I'll be pushing the LoongArch patches this week.
Thanks.
Song Gao
h
On Fri, Jun 28, 2024 at 1:34 PM Feiyang Chen
wrote:
Since srai.w is a valid instruction
>-Original Message-
>From: Joao Martins
>Subject: Re: [PATCH v3 01/10] vfio/iommufd: Don't fail to realize on
>IOMMU_GET_HW_INFO failure
>
>On 09/07/2024 12:45, Joao Martins wrote:
>> On 09/07/2024 09:56, Joao Martins wrote:
>>> On 09/07/2024 04:43, Duan, Zhenzhong wrote:
Hi Joao,
>
ping
https://lore.kernel.org/qemu-devel/20240628033357.50027-1-chris.chenfeiy...@gmail.com/
On Fri, Jun 28, 2024 at 1:34 PM Feiyang Chen
wrote:
>
> Since srai.w is a valid instruction on la32, remove the avail_64 check
> and simplify trans_srai_w().
>
> Fixes: c0c0461e3a06 ("target/loongarch: Ad
Hi Nicolin,
>-Original Message-
>From: Nicolin Chen
>Subject: Re: [PATCH RFCv1 02/10] hw/arm/virt: Add iommufd link to virt-
>machine
>
>On Tue, Jul 09, 2024 at 07:06:50PM +0200, Eric Auger wrote:
>> On 7/9/24 18:59, Nicolin Chen wrote:
>> > Hi Eric,
>> >
>> > Thanks for the comments!
>>
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Acked-by: Alistair Francis
---
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 17 -
1 f
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h | 5 -
1
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/ta
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zh
From: 甲一
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
# make check-avocado
AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avoca
On 2024/7/10 9:31, Alistair Francis wrote:
On Mon, Jul 8, 2024 at 11:22 PM LIU Zhiwei wrote:
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot r
On Tue, Jul 9, 2024 at 9:41 PM LIU Zhiwei wrote:
>
> I once used a wrong major opcode for zimop. It should use 0x73 as major
> opcode.
> This was detected after I got a toolchain with zimop support. Before that, I
> tested
> this implementation with hardwire code instruction instead of assemble
On Mon, Jul 8, 2024 at 11:21 PM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> Ensure mcause high bit is correctly set by using 32-bit width for RV32
> mode and 64-bit width for RV64 mode.
>
> Signed-off-by: TANG Tiancheng
> Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
Alistair
> -
On Mon, Jul 8, 2024 at 11:22 PM LIU Zhiwei wrote:
>
> From: TANG Tiancheng
>
> To regularly test booting Linux with rv32 on QEMU RV64,
> we have added a test to boot_linux_console.py to retrieve
> cpuinfo and verify if it shows 'rv32' when using RV64 to
> boot rv32 CPUs.
>
> Signed-off-by: TANG T
On Thu, Jul 4, 2024 at 2:03 PM Alvin Chang via wrote:
>
> According to RISC-V Debug specification, the optional textra32 and
> textra64 trigger CSRs can be used to configure additional matching
> conditions for the triggers. For example, if the textra.MHSELECT field
> is set to 4 (mcontext), this
On Thu, Jul 4, 2024 at 2:03 PM Alvin Chang via wrote:
>
> This commit allows program to write textra trigger CSR for type 2, 3, 6
> triggers. In this preliminary patch, the textra.MHVALUE and the
> textra.MHSELECT fields are allowed to be configured. Other fields, such
> as textra.SBYTEMASK, textr
On Mon, Jul 8, 2024 at 9:50 PM Sunil V L wrote:
>
> The expected ACPI AML files are moved now under ${arch}/{machine} path.
> Hence, there is no need to search in old path which didn't have ${arch}.
> Remove the code which searches for the expected AML files under old path
> as well.
>
> Suggested
On Tue, Jul 9, 2024 at 6:55 PM Daniel Henrique Barboza
wrote:
>
> Two new regs added: ztso and zacas.
>
> Signed-off-by: Daniel Henrique Barboza
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/targe
On Tue, Jul 9, 2024 at 6:55 PM Daniel Henrique Barboza
wrote:
>
> Two new regs added: ztso and zacas.
>
> Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/k
On 7/9/24 09:26, Philippe Mathieu-Daudé wrote:
On 9/7/24 17:41, Richard Henderson wrote:
Hi guys,
I have reinstalled my development box to ubuntu 24 (because the Rust support is better
than my previous install; ho hum). I thought I had tested everything in a VM before
committing, but I misse
On Tue, Jul 9, 2024 at 6:52 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Fully eliminate the "Example" sections in QAPI doc blocks now that they
> > have all been converted to arbitrary rST syntax using the
> > ".. qmp-example::" directive. Update tests to match.
> >
> > Migrating to th
On Tue, Jul 9, 2024 at 7:35 AM Markus Armbruster wrote:
> John Snow writes:
>
> > These examples require longer explanations or have explanations that
> > require markup to look reasonable when rendered and so use the longer
> > form of the ".. qmp-example::" directive.
> >
> > By using the :ann
On Tue, Jul 9, 2024 at 6:34 AM Markus Armbruster wrote:
> John Snow writes:
>
> > From: Harmonie Snow
> >
> > Add CSS styling for qmp-example directives to increase readability and
> > consistently style all example blocks.
> >
> > Signed-off-by: Harmonie Snow
> > Signed-off-by: John Snow
>
>
On Tue, Jul 9, 2024 at 6:33 AM Markus Armbruster wrote:
> John Snow writes:
>
> > For any code literal blocks inside of a qmp-example directive, apply and
> > enforce the QMP lexer/highlighter to those blocks.
> >
> > This way, you won't need to write:
> >
> > ```
> > .. qmp-example::
> >:an
On 9/7/24 17:58, Cédric Le Goater wrote:
On 7/9/24 5:25 PM, Philippe Mathieu-Daudé wrote:
Since v42:
- Stick to spec v4.3 (re-simplified EXT_CSD register & migrate)
- Fill CID register
- Few changes to CSD register
- Implement 'boot-mode' reset timing
- Add 'boot-size' property
Change required
On 9/7/24 17:43, Cédric Le Goater wrote:
On 7/9/24 5:25 PM, Philippe Mathieu-Daudé wrote:
- Set some keys to not defined / implemented:
. EXT_CSD_HPI_FEATURES
. EXT_CSD_BKOPS_SUPPORT
. EXT_CSD_SEC_FEATURE_SUPPORT
. EXT_CSD_ERASE_TIMEOUT_MULT
. EXT_CSD_PART_SWITCH_TIME
. EXT_CSD
On 5/7/24 17:52, Philippe Mathieu-Daudé wrote:
On 5/7/24 15:28, Philippe Mathieu-Daudé wrote:
On 5/7/24 07:38, Cédric Le Goater wrote:
On 7/5/24 5:41 AM, Andrew Jeffery wrote:
On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote:
From: Cédric Le Goater
When the boot-from-eMMC HW strapp
On 24-07-09 11:58:53, CLEMENT MATHIEU--DRIF wrote:
>
>
> On 09/07/2024 12:15, Minwoo Im wrote:
> > Caution: External email. Do not open attachments or click links, unless
> > this email comes from a known sender and you know the content is safe.
> >
> >
> > On 24-07-02 05:52:45, CLEMENT MATHIEU-
On Tue, Jul 09, 2024 at 05:38:54PM -0300, Fabiano Rosas wrote:
> Philippe Mathieu-Daudé writes:
>
> > "General command" (GEN_CMD, CMD56) is described as:
> >
> > GEN_CMD is the same as the single block read or write
> > commands (CMD24 or CMD17). The difference is that [...]
> > the data bl
Finish CPR for vfio-pci MSI/MSI-X devices by preserving eventfd's and
vector state.
Signed-off-by: Steve Sistare
---
hw/vfio/pci.c | 117 +-
1 file changed, 116 insertions(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index
If there are multiple containers and unmap-all fails for some container, we
need to remap vaddr for the other containers for which unmap-all succeeded.
Recover by walking all address ranges of all containers to restore the vaddr
for each. Do so by invoking the vfio listener callback, and passing a
Enable vfio-pci devices to be saved and restored across a cpr-exec of qemu.
At vfio creation time, save the value of vfio container, group, and device
descriptors in CPR state.
In the container pre_save handler, suspend the use of virtual addresses
in DMA mappings with VFIO_DMA_UNMAP_FLAG_VADDR,
Export msix_is_pending for use by cpr. No functional change.
Signed-off-by: Steve Sistare
Acked-by: Michael S. Tsirkin
---
hw/pci/msix.c | 2 +-
include/hw/pci/msix.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/pci/msix.c b/hw/pci/msix.c
index 487e498..17ef2
Refactor vector use into a helper vfio_vector_init.
Add vfio_notifier_init and vfio_notifier_cleanup for named notifiers,
and pass additional arguments to vfio_remove_kvm_msi_virq.
All for use by CPR in a subsequent patch. No functional change.
Signed-off-by: Steve Sistare
---
hw/vfio/pci.c |
Preserve vfio INTX state across cpr-exec. Preserve VFIOINTx fields as
follows:
pin : Recover this from the vfio config in kernel space
interrupt : Preserve its eventfd descriptor across exec.
unmask : Ditto
route.irq : This could perhaps be recovered in vfio_pci_post_load by
calling pc
Define vfio_find_ram_discard_listener as a subroutine so additional calls to
it may be added in a subsequent patch.
Signed-off-by: Steve Sistare
---
hw/vfio/common.c | 35 ++-
1 file changed, 22 insertions(+), 13 deletions(-)
diff --git a/hw/vfio/common.c b/hw/vf
Support vfio devices with the cpr-exec live migration mode.
See the commit messages of the individual patches for details.
No user-visible interfaces are added.
This series is extracted from the following and updated for the latest QEMU:
[PATCH V9 00/46] Live Update
https://lore.kernel.org/qe
Define a vmstate "needed" helper. This will be moved to the preceding patch
series "Live update: cpr-exec" because it is needed by multiple devices.
Signed-off-by: Steve Sistare
---
include/migration/cpr.h | 1 +
migration/cpr.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/
Philippe Mathieu-Daudé writes:
> "General command" (GEN_CMD, CMD56) is described as:
>
> GEN_CMD is the same as the single block read or write
> commands (CMD24 or CMD17). The difference is that [...]
> the data block is not a memory payload data but has a
> vendor specific format and mea
On Tue, Jul 09, 2024 at 01:53:59AM +0800, Yuan Liu wrote:
> add Intel QATzip compression method introduction
>
> Signed-off-by: Yuan Liu
> Reviewed-by: Nanhai Zou
Reviewed-by: Peter Xu
Thanks.
--
Peter Xu
On Tue, Jul 09, 2024 at 08:42:59AM +, Liu, Yuan1 wrote:
> > -Original Message-
> > From: Yichen Wang
> > Sent: Saturday, July 6, 2024 2:29 AM
> > To: Paolo Bonzini ; Daniel P. Berrangé
> > ; Eduardo Habkost ; Marc-André
> > Lureau ; Thomas Huth ;
> > Philippe Mathieu-Daudé ; Peter Xu ;
On Tue, Jul 09, 2024 at 07:22:16PM +0200, Eric Auger wrote:
> On 7/9/24 19:11, Nicolin Chen wrote:
> > On Tue, Jul 09, 2024 at 11:20:16AM +0200, Eric Auger wrote:
> >> On 6/26/24 02:28, Nicolin Chen wrote:
> >>> Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
> >>> instance
On 7/9/24 09:51, Paolo Bonzini wrote:
On Tue, Jul 9, 2024 at 2:18 PM Daniel P. Berrangé wrote:
My thought is that the initial merge focuses only on the build system
integration. So that's basically patches 1 + 2 in this series.
Patch 3, the high level APIs is where I see most of the work and
c
On Tue, Jul 09, 2024 at 03:26:58PM +0200, Eric Auger wrote:
> > @@ -1580,12 +1647,33 @@ static void create_pcie(VirtMachineState *vms)
> > qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
> > create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
> >
> > -if (vms->
github.com/legoater/qemu/ tags/pull-aspeed-20240709
for you to fetch changes up to d847ea7cfc6321e2519f587d4077428d90557178:
machine_aspeed.py: update to test network for AST2700 (2024-07-09 08:05:44
+0200)
aspeed queue:
* suppo
github.com/legoater/qemu/ tags/pull-vfio-20240709
for you to fetch changes up to 83d90192026eaded6319a6d27466ad7d606a27e0:
vfio/display: Fix vfio_display_edid_init() error path (2024-07-09 11:50:37
+0200)
vfio queue:
* Fix
On 7/9/24 19:11, Nicolin Chen wrote:
> On Tue, Jul 09, 2024 at 11:20:16AM +0200, Eric Auger wrote:
>> On 6/26/24 02:28, Nicolin Chen wrote:
>>> Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
>>> instance(s). Add a helper to read the sysfs for the number of instances.
>>
On Tue, Jul 09, 2024 at 07:06:50PM +0200, Eric Auger wrote:
> On 7/9/24 18:59, Nicolin Chen wrote:
> > Hi Eric,
> >
> > Thanks for the comments!
> >
> > On Tue, Jul 09, 2024 at 11:11:56AM +0200, Eric Auger wrote:
> >> On 6/26/24 02:28, Nicolin Chen wrote:
> >>> A nested SMMU must use iommufd ioctls
On Tue, Jul 09, 2024 at 07:14:19AM +, Mostafa Saleh wrote:
> Hi Jean,
>
> On Thu, Jul 04, 2024 at 07:12:35PM +0100, Jean-Philippe Brucker wrote:
> > On Mon, Jul 01, 2024 at 11:02:31AM +, Mostafa Saleh wrote:
> > > In the next patch, combine_tlb() will be added which combines 2 TLB
> > > en
On Tue, Jul 09, 2024 at 11:20:16AM +0200, Eric Auger wrote:
> On 6/26/24 02:28, Nicolin Chen wrote:
> > Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
> > instance(s). Add a helper to read the sysfs for the number of instances.
> > Log them in a vms list using a new struct
On 7/9/24 18:59, Nicolin Chen wrote:
> Hi Eric,
>
> Thanks for the comments!
>
> On Tue, Jul 09, 2024 at 11:11:56AM +0200, Eric Auger wrote:
>> On 6/26/24 02:28, Nicolin Chen wrote:
>>> A nested SMMU must use iommufd ioctls to communicate with the host-level
>>> SMMU instance for 2-stage transla
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