Re: [PATCH v1 2/2] xen: mapcache: Fix unmapping of first entries in buckets

On Thu, Jul 4, 2024 at 9:48 PM Edgar E. Iglesias wrote: > On Thu, Jul 04, 2024 at 05:44:52PM +0100, Alex Bennée wrote: > > Anthony PERARD writes: > > > > > On Tue, Jul 02, 2024 at 12:44:21AM +0200, Edgar E. Iglesias wrote: > > >> From: "Edgar E. Iglesias" > > >> > > >> This fixes the clobbering

[PULL 16/16] hw/sd/sdcard: Extract TYPE_SDMMC_COMMON from TYPE_SD_CARD

In order to keep eMMC model simpler to maintain, extract common properties and the common code from class_init to the (internal) TYPE_SDMMC_COMMON. Update the corresponding QOM cast macros. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by:

[PULL 12/16] hw/sd/sdcard: Remove default case in read/write on DAT lines

All read/write on DAT lines are explicitly handled. Reaching this point would be a programming error: replace by an assertion. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-79-phi...@l

[PULL 13/16] hw/sd/sdcard: Trace length of data read on DAT lines

Some commands expect less than BLOCK_LENGTH. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-80-phi...@linaro.org> --- hw/sd/sd.c | 4 ++-- hw/sd/trace-events | 2 +- 2 files ch

[PULL 11/16] hw/sd/sdcard: Remove noise from sd_cmd_name()

These CMD names weren't really useful, "UNKNOWN_CMD" is simpler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-78-phi...@linaro.org> --- hw/sd/sd.c | 5 - 1 file changed, 5 deleti

[PULL 09/16] hw/sd/sdcard: Remove sd_none enum from sd_cmd_type_t

All handlers using the 'sd_none' enum got converted, remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-76-phi...@linaro.org> --- include/hw/sd/sd.h | 1 - hw/sd/sd.c |

[PULL 15/16] hw/sd/sdcard: Introduce set_csd/set_cid handlers

In preparation of introducing eMMC support which have different CSD/CID structures, introduce a pair of handlers in SDCardClass. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-82-phi...

[PULL 07/16] hw/sd/sdcard: Rename sd_cmd_SEND_OP_COND handler

The correct command name is 'SD SEND_OP_COND', rename accordingly. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240703134356.85972-4-phi...@linaro.org> --- hw/sd/sd.c | 4 ++-- 1 file changed, 2 insert

[PULL 14/16] hw/sd/sdcard: Cover more SDCardStates

So far eMMC will only use sd_sleep_state, but all all states specified for completeness. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-81-phi...@linaro.org> --- hw/sd/sd.c | 11 ++

[PULL 08/16] hw/sd/sdcard: Add sd_cmd_GEN_CMD handler (CMD56)

"General command" (GEN_CMD, CMD56) is described as: GEN_CMD is the same as the single block read or write commands (CMD24 or CMD17). The difference is that [...] the data block is not a memory payload data but has a vendor specific format and meaning. Thus this block must not be stored ov

[PULL 06/16] hw/sd/sdcard: Use spec v3.01 by default

Recent SDHCI expect cards to support the v3.01 spec to negociate lower I/O voltage. Select it by default. Versioned machine types with a version of 9.0 or earlier retain the old default (spec v2.00). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery

[PULL 10/16] hw/sd/sdcard: Remove noise from sd_acmd_name()

These ACMD names weren't really useful, "UNKNOWN_ACMD" is simpler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Tested-by: Cédric Le Goater Message-Id: <20240628070216.92609-77-phi...@linaro.org> --- hw/sd/sd.c | 12 +--- 1 file changed

[PULL 03/16] tests/qtest/npcm7xx_sdhci: Access the card using its published address

Currently setup_sd_card() asks the card its address, but discard the response and use hardcoded 0x4567. Set the SDHC_CMD_RESPONSE bit to have the controller record the bus response, and read the response from the RSPREG0 register. Then we can select the card with its real address. Signed-off-by:

[PULL 04/16] hw/sd/sdcard: Generate random RCA value

Rather than using the obscure 0x4567 magic value, use a real random one. Signed-off-by: Philippe Mathieu-Daudé Tested-by: Cédric Le Goater Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Message-Id: <20240702140842.54242-5-phi...@linaro.org> --- hw/sd/sd.c | 11 --- hw

[PULL 05/16] hw/sd/sdcard: Remove leftover comment about removed 'spi' Property

Commit c3287c0f70 ("hw/sd: Introduce a "sd-card" SPI variant model") removed the 'spi' property. Remove the comment left over. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Manos Pitsidianakis Tested-by: Andrew Jeffery Message-Id: <20240703085907.66775-2-phi...@linaro.org> --- hw/sd/sd.c

[PULL 00/16] SD/MMC patches for 2024-07-06

The following changes since commit f2cb4026fccfe073f84a4b440e41d3ed0c3134f6: Merge tag 'pull-maintainer-july24-050724-1' of https://gitlab.com/stsquad/qemu into staging (2024-07-05 09:15:48 -0700) are available in the Git repository at: https://github.com/philmd/qemu.git tags/sdmmc-20240706

[PULL 02/16] hw/sd/npcm7xx_sdhci: Use TYPE_SYSBUS_SDHCI definition

Use the macro instead of two explicit string literals. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Message-Id: <20240702140842.54242-2-phi...@linaro.org> --- hw/sd/npcm7xx_sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/sd/npcm7xx_sdhci.c

[PULL 01/16] hw/sd/sdhci: Log non-sequencial access as GUEST_ERROR

Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Tested-by: Andrew Jeffery Message-Id: <20240702140842.54242-3-phi...@linaro.org> --- hw/sd/sdhci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 27673e1c70..d02c3e3

Re: [PATCH v46 0/5] hw/sd/sdcard: Cleanups before adding eMMC support

On 3/7/24 15:43, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (5): hw/sd/sdcard: Use spec v3.01 by default hw/sd/sdcard: Add sd_cmd_GEN_CMD handler (CMD56) hw/sd/sdcard: Rename sd_cmd_SEND_OP_COND handler hw/sd/sdcard: Introduce set_csd/set_cid handlers hw/sd/sdcard: Extra

Re: [PATCH 0/4] qtest/npcm7xx_sdhci: Use card-provided address (RCA)

On 2/7/24 16:08, Philippe Mathieu-Daudé wrote: Philippe Mathieu-Daudé (4): hw/sd/npcm7xx_sdhci: Use TYPE_SYSBUS_SDHCI definition hw/sd/sdhci: Log non-sequencial access as GUEST_ERROR tests/qtest/npcm7xx_sdhci: Access the card using its published address hw/sd/sdcard: Generate random

Re: [PATCH 4/4] target/hexagon/imported/mmvec: Fix superfluous trailing semicolon

On 7/4/2024 3:47 AM, Zhao Liu wrote: Fix the superfluous trailing semicolon in target/hexagon/imported/mmvec/ ext.idef. Cc: Brian Cain Signed-off-by: Zhao Liu Reviewed-by: Brian Cain --- target/hexagon/imported/mmvec/ext.idef | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) di

Re: [PATCH v2 20/40] gitlab: don't bother with KVM for TCI builds

On 5/7/24 18:49, Thomas Huth wrote: On 05/07/2024 18.34, Philippe Mathieu-Daudé wrote: On 5/7/24 10:40, Alex Bennée wrote: In fact any other accelerator would be pointless as the point is to exercise the TCI accelerator anyway. Signed-off-by: Alex Bennée ---   .gitlab-ci.d/buildtest.yml   | 2

Re: [PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support

Hi, Would it make it easier for review if we squash patch 3: [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation and patch 8: [PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support In the same patch? I'm asking because I've been noticing since the first versions that s

Re: [PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation

Hi, On 7/4/24 11:20 AM, Jason Chien wrote: Hi Danial, On 2024/6/25 上午 04:18, Daniel Henrique Barboza wrote: From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-n

Re: [PATCH 00/14] rust: example of bindings code for Rust in QEMU

Hi, first of all I want to clarify the raison d'etre for this posting, which I have also explained to Manos. Nothing you see here is code that will be certainly included in QEMU; it's (mostly) throwaway by design. I don't have much attachment to any of the code except perhaps the casting and refere

[PATCH] e1000: Fix the unexpected assumption that the receive buffer is full

Unexpected work by certain Windows guests equipped with the e1000 interface can cause the network to go down and never come back up again unless the guest's interface is reset. To reproduce the failure: 1. Set up two guests with a Windows 2016 or 2019 server operating system. 2. Set up the e100

Re: [PATCH v2 1/2] system: Sort QEMU_ARCH_VIRTIO_PCI definition

On 7/5/24 05:45, Philippe Mathieu-Daudé wrote: Sort the QEMU_ARCH_VIRTIO_PCI to simplify adding/removing entries. Signed-off-by: Philippe Mathieu-Daudé --- system/qdev-monitor.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/system/qdev-monitor.c b/sys

Re: [PATCH 00/14] rust: example of bindings code for Rust in QEMU

On 7/5/24 01:06, Paolo Bonzini wrote: On Thu, Jul 4, 2024 at 9:26 PM Pierrick Bouvier wrote: Patches 9-10 deal with how to define new subclasses in Rust. They are a lot less polished and less ready. There is probably a lot of polish that could be applied to make the code look nicer, but I gue

[PATCH v4 2/4] migration: Add migration parameters for QATzip

From: Bryan Zhang Adds support for migration parameters to control QATzip compression level and to enable/disable software fallback when QAT hardware is unavailable. This is a preparatory commit for a subsequent commit that will actually use QATzip compression. Signed-off-by: Bryan Zhang Signed

[PATCH v4 4/4] tests/migration: Add integration test for 'qatzip' compression method

From: Bryan Zhang Adds an integration test for 'qatzip'. Signed-off-by: Bryan Zhang Signed-off-by: Hao Xiang Signed-off-by: Yichen Wang Reviewed-by: Fabiano Rosas --- tests/qtest/migration-test.c | 35 +++ 1 file changed, 35 insertions(+) diff --git a/tests/

[PATCH v4 1/4] meson: Introduce 'qatzip' feature to the build system

From: Bryan Zhang Add a 'qatzip' feature, which is automatically disabled, and which depends on the QATzip library if enabled. Signed-off-by: Bryan Zhang Signed-off-by: Hao Xiang Signed-off-by: Yichen Wang --- meson.build | 10 ++ meson_options.txt | 2

[PATCH v4 3/4] migration: Introduce 'qatzip' compression method

From: Bryan Zhang Adds support for 'qatzip' as an option for the multifd compression method parameter, and implements using QAT for 'qatzip' compression and decompression. Signed-off-by: Bryan Zhang Signed-off-by: Hao Xiang Signed-off-by: Yichen Wang --- hw/core/qdev-properties-system.c |

[PATCH v4 0/4] Implement using Intel QAT to offload ZLIB

v4: - Rebase changes on top of 1a2d52c7fcaeaaf4f2fe8d4d5183dccaeab67768 - Move the IOV initialization to qatzip implementation - Only use qatzip to compress normal pages v3: - Rebase changes on top of master - Merge two patches per Fabiano Rosas's comment - Add versions into comments and documenta

Re: [External] [PATCH v3 0/4] Implement using Intel QAT to offload ZLIB

> On Jul 5, 2024, at 1:32 AM, Liu, Yuan1 wrote: > >> -Original Message- >> From: Peter Xu mailto:pet...@redhat.com>> >> Sent: Thursday, July 4, 2024 11:36 PM >> To: Liu, Yuan1 mailto:yuan1@intel.com>> >> Cc: Wang, Yichen > >; Paolo Bonzini >> mailto

Re: [RFC PATCH 0/4] hw/display/virtio-gpu: Introducing asynchronous guest display render

On 7/2/2024 11:26 PM, Marc-André Lureau wrote: Hi On Tue, Jul 2, 2024 at 10:11 PM Kim, Dongwon > wrote: Hi Marc-André, On 7/2/2024 3:29 AM, Marc-André Lureau wrote: > Hi > > On Fri, Jun 21, 2024 at 3:20 AM mailto:dongwon@intel.com>

Re: [PULL 00/40] maintainer updates for testing, plugins and gdbstub

On 7/5/24 08:30, Alex Bennée wrote: The following changes since commit 5915139aba1646220630596de30c673528e047c9: Merge tag 'for-upstream' ofhttps://gitlab.com/bonzini/qemu into staging (2024-07-04 09:16:07 -0700) are available in the Git repository at: https://gitlab.com/stsquad/qemu.g

Re: [PATCH 1/2] ui/egl-helpers: Consolidate create-sync and create-fence

Hi Marc-André, On 7/3/2024 4:23 AM, Marc-André Lureau wrote: Hi On Wed, Jul 3, 2024 at 12:57 AM > wrote: From: Dongwon Kim mailto:dongwon@intel.com>> There is no reason to split those two operations so combining two functions - egl_dmabuf_create_

Re: [PATCH 0/2] target/arm: Fix unwind from dc zva and FEAT_MOPS

On Thu, 2024-07-04 at 14:48 -0700, Richard Henderson wrote: > On 7/4/24 08:18, Richard Henderson wrote: > > On 7/4/24 07:50, Ilya Leoshkevich wrote: > > > On Tue, 2024-07-02 at 16:41 -0700, Richard Henderson wrote: > > > > While looking into Zoltan's attempt to speed up ppc64 DCBZ > > > > (data cac

Re: [PULL 17/20] target/arm: Do memory type alignment check when translation disabled

On Fri, 5 Jul 2024 at 12:46, Bernhard Beschow wrote: > Am 27. Mai 2024 17:49:26 UTC schrieb Bernhard Beschow : > >Am 27. Mai 2024 16:20:44 UTC schrieb Richard Henderson > >: > >>On 5/27/24 08:29, Bernhard Beschow wrote: > >>> I think the kernel's output indicates that the MMU is active: > >>> > >

[PATCH v2] disas/riscv: Add decode for Zawrs extension

From: Balaji Ravikumar Add disassembly support for these instructions from Zawrs: * wrs.sto * wrs.nto Signed-off-by: Balaji Ravikumar Signed-off-by: Rob Bradford --- disas/riscv.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/disas/riscv.c b/disas/riscv.c index 05b663ebfe..ff0323

Re: [PATCH v2 20/40] gitlab: don't bother with KVM for TCI builds

On 05/07/2024 18.34, Philippe Mathieu-Daudé wrote: On 5/7/24 10:40, Alex Bennée wrote: In fact any other accelerator would be pointless as the point is to exercise the TCI accelerator anyway. Signed-off-by: Alex Bennée ---   .gitlab-ci.d/buildtest.yml   | 2 +-   .gitlab-ci.d/crossbuilds.yml |

Re: [PATCH v2 20/40] gitlab: don't bother with KVM for TCI builds

On 5/7/24 10:40, Alex Bennée wrote: In fact any other accelerator would be pointless as the point is to exercise the TCI accelerator anyway. Signed-off-by: Alex Bennée --- .gitlab-ci.d/buildtest.yml | 2 +- .gitlab-ci.d/crossbuilds.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions

Re: [PATCH v5 2/7] plugins: save value during memory accesses

On 7/4/24 17:34, Pierrick Bouvier wrote: +static void +plugin_gen_mem_callbacks_i32(TCGv_i32 val, + TCGv_i64 copy_addr, TCGTemp *orig_addr, + MemOpIdx oi, enum qemu_plugin_mem_rw rw) +{ +#ifdef CONFIG_PLUGIN +if (tcg_ctx->plugin_insn !=

Re: [PATCH 0/4] Python: Add 3.13 support, play linter whackamole

On Wed, Jun 26, 2024, 7:22 PM John Snow wrote: > Fix some regressions in check-python-tox that have crept in since Pylint > 3.x, and add Python 3.13 support to the pipeline. > > GitLab pipeline (before I fixed the missing DCO, but let's be honest, it > can't possibly be worth re-running so many t

Re: [PATCH 5/8] aspeed: Set eMMC 'boot-config' property to reflect HW strapping

On 5/7/24 15:28, Philippe Mathieu-Daudé wrote: On 5/7/24 07:38, Cédric Le Goater wrote: On 7/5/24 5:41 AM, Andrew Jeffery wrote: On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote: From: Cédric Le Goater When the boot-from-eMMC HW strapping bit is set, use the 'boot-config' property t

Re: [PATCH v2 0/2] docs/python: bump minimum Sphinx version

On Wed, Jul 3, 2024, 1:52 PM John Snow wrote: > With recent deprecations, we can advance our minimum sphinx version > safely. This is heavily motivated by new qapidoc work which is much > easier to maintain cross-version compatibility for - see difficulties in > our dbus documentation which only

[PULL 20/40] gitlab: don't bother with KVM for TCI builds

In fact any other accelerator would be pointless as the point is to exercise the TCI accelerator anyway. Reviewed-by: Thomas Huth Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-21-alex.ben...@linaro.org> diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 4

[PULL 31/40] gdbstub: Move GdbCmdParseEntry into a new header file

From: Gustavo Romero Move GdbCmdParseEntry and its associated types into a separate header file to allow the use of GdbCmdParseEntry and other gdbstub command functions outside of gdbstub.c. Since GdbCmdParseEntry and get_param are now public, kdoc GdbCmdParseEntry and rename get_param to gdb_ge

[PULL 33/40] target/arm: Fix exception case in allocation_tag_mem_probe

From: Gustavo Romero If page in 'ptr_access' is inaccessible and probe is 'true' allocation_tag_mem_probe should not throw an exception, but currently it does, so fix it. Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20240628050850.536447-5

[PULL 21/40] test/plugin: make insn plugin less noisy by default

While the match functionality is useful lets make the verbosity optional while we are actually running. Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-22-alex.ben...@linaro.org> diff --git a/tests/plugin/insn.c b/tests/plugin/insn.c index 5e0aa032

[PULL 38/40] gdbstub: Use true to set cmd_startswith

From: Gustavo Romero cmd_startswith is a boolean so use 'true' to set it instead of 1. Signed-off-by: Gustavo Romero Message-Id: <20240628050850.536447-10-gustavo.rom...@linaro.org> Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-39-alex.ben...@l

[PULL 26/40] plugins/lockstep: clean-up output

We were repeating information which wasn't super clear. As we already will have dumped the last failing PC just note the divergence and dump the previous instruction log. Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-27-alex.ben...@linaro.org> diff --git a/contrib/plugins/lockste

[PULL 22/40] test/plugins: preserve the instruction record over translations

We are interested in the particular instruction so we should use a stable record for it. We could bring this down to physical address but for now vaddr + disas seems to do the trick. Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-23-alex.ben...@lin

[PULL 28/40] plugins: Free CPUPluginState before destroying vCPU state

From: Philippe Mathieu-Daudé cpu::plugin_state is allocated in cpu_common_initfn() when the vCPU state is created. Release it in cpu_common_finalize() when we are done. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-Id: <20240606124010.2460-3-phi...@linaro.org> Sig

[PULL 19/40] linux-user/main: Suppress out-of-range comparison warning for clang

From: Richard Henderson For arm32 host and arm64 guest we get .../main.c:851:32: error: result of comparison of constant 70368744177664 with expression of type 'unsigned long' is always false [-Werror,-Wtautological-constant-out-of-range-compare] if (TASK_UNMAPPED_BASE < reserved_va) {

[PULL 32/40] gdbstub: Add support for target-specific stubs

From: Gustavo Romero Currently, it's not possible to have stubs specific to a given target, even though there are GDB features which are target-specific, like, for instance, memory tagging. This commit introduces gdb_extend_qsupported_features, gdb_extend_query_table, and gdb_extend_set_table fu

[PULL 30/40] gdbstub: Clean up process_string_cmd

From: Gustavo Romero Change 'process_string_cmd' to return true on success and false on failure, instead of 0 and -1. Signed-off-by: Gustavo Romero Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240628050850.536447-2-gustavo.rom...@

[PULL 24/40] plugins/lockstep: make mixed-mode safe

The ExecState is shared across the socket and if we want to compare say 64 bit and 32 bit binaries we need the two to use the same sizes for things. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-25-alex.ben...@linaro.org> diff --git a/contrib/plugi

[PULL 23/40] plugins/lockstep: preserve sock_path

We can't assign sock_path directly from the autofree'd GStrv, take a copy. Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-24-alex.ben...@linaro.org> diff --git a/contrib/plugins/lockstep.c b/contrib/plugins/lockstep.c index 237543b43a..67a779ee9d

[PULL 36/40] gdbstub: Make hex conversion function non-internal

From: Gustavo Romero Make gdb_hextomem non-internal so it's not confined to use only in gdbstub.c. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Message-Id: <20240628050850.536447-8-gustavo.rom...@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-37-alex

[PULL 39/40] gdbstub: Add support for MTE in user mode

From: Gustavo Romero This commit implements the stubs to handle the qIsAddressTagged, qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' subcommands to work with QEMU gdbstub on aarch64 user mode. It also implements the get/set functions for the special GDB MTE register 'tag_ctl', us

[PULL 18/40] tests/tcg/arm: Use vmrs/vmsr instead of mcr/mrc

From: Richard Henderson Clang 14 generates /home/rth/qemu/src/tests/tcg/arm/fcvt.c:431:9: error: invalid operand for instruction asm("mrc p10, 7, r1, cr1, cr0, 0\n\t" ^ :1:6: note: instantiated into assembly here mrc p10, 7, r1, cr1, cr0, 0 ^ /home/rth/qemu/src/t

[PULL 25/40] plugins/lockstep: mention the one-insn-per-tb option

This really helps with lockstep although its super slow on big jobs. Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-26-alex.ben...@linaro.org> diff --git a/contrib/plugins/lockstep.c b/contrib/plugins/lockstep.c index 8b90b37f67..1765fd6c36 100644

[PULL 34/40] target/arm: Make some MTE helpers widely available

From: Gustavo Romero Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240628050850.536447-6-gustavo.rom...@linaro.org> Signed-

[PULL 27/40] plugins: Ensure vCPU index is assigned in init/exit hooks

From: Philippe Mathieu-Daudé Since vCPUs are hashed by their index, this index can't be uninitialized (UNASSIGNED_CPU_INDEX). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Message-Id: <20240606124010.2460-2-phi...@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20240

[PULL 29/40] accel/tcg: Move qemu_plugin_vcpu_init__async() to plugins/

From: Philippe Mathieu-Daudé Calling qemu_plugin_vcpu_init__async() on the vCPU thread is a detail of plugins, not relevant to TCG vCPU management. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Pierrick Bouvier Message-Id: <20240606124010.2460-4-phi...@lina

[PULL 40/40] tests/tcg/aarch64: Add MTE gdbstub tests

From: Gustavo Romero Add tests to exercise the MTE stubs. The tests will only run if a version of GDB that supports MTE is available in the test environment. Signed-off-by: Gustavo Romero [AJB: re-base and checkpatch fixes] Message-Id: <20240628050850.536447-12-gustavo.rom...@linaro.org> Signed

[PULL 05/40] tests/docker: Specify --userns keep-id for Podman

From: Akihiko Odaki Previously we are always specifying -u $(UID) to match the UID in the container with one outside. This causes a problem with rootless Podman. Rootless Podman remaps user IDs in the container to ones controllable for the current user outside. The -u option instructs Podman to

[PULL 17/40] tests/tcg/arm: Use -march and -mfpu for fcvt

From: Richard Henderson Clang requires the architecture to be set properly in order to assemble the half-precision instructions. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-13-richard.hender...@linaro.org> Signed-off-by: Alex Bennée Message-I

[PULL 01/40] tests/lcitool: fix debian-i686-cross toolchain prefix

I guess we never noticed and tried to build with this cross image. Fix the toolchain prefix so we actually build 32 bit images. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-2-alex.ben...@linaro.org> diff --git a/tests/docker/dockerfiles/debian-i68

[PULL 09/40] tests/tcg/aarch64: Explicitly specify register width

From: Akihiko Odaki clang version 18.1.6 assumes a register is 64-bit by default and complains if a 32-bit value is given. Explicitly specify register width when passing a 32-bit value. Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240627-tcg-v2-3-1690a8133...

Re: [PATCH v4 1/1] hw/cxl: Support firmware updates

just a small request, pls use same prefix for all patches in the series including the cover letter.

[PULL 11/40] tests/tcg/aarch64: Do not use x constraint

From: Akihiko Odaki clang version 18.1.6 does not support x constraint for AArch64. Use w instead. Signed-off-by: Akihiko Odaki Message-Id: <20240627-tcg-v2-5-1690a8133...@daynix.com> Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-7-richard.hender...@linaro.org> Signed-off-by: A

[PULL 10/40] tests/tcg/aarch64: Fix irg operand type

From: Akihiko Odaki irg expects 64-bit integers. Passing a 32-bit integer results in compilation failure with clang version 18.1.6. Signed-off-by: Akihiko Odaki Message-Id: <20240627-tcg-v2-4-1690a8133...@daynix.com> Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-6-richard.hende

[PULL 13/40] tests/tcg/arm: Fix fcvt result messages

From: Akihiko Odaki The test cases for "converting double-precision to single-precision" emits float but the result variable was typed as uint32_t and corrupted the printed values. Propertly type it as float. Signed-off-by: Akihiko Odaki Fixes: 8ec8a55e3fc9 ("tests/tcg/arm: add fcvt test cases

[PULL 02/40] testing: restore some testing for i686

The commit 4f9a8315e6 (gitlab-ci.d/crossbuilds: Drop the i386 system emulation job) was a little too aggressive dropping testing for 32 bit system builds. Partially revert but using the debian-i686 cross build images this time as fedora has deprecated the 32 bit stuff. As the SEV breakage gets in

[PULL 35/40] target/arm: Factor out code for setting MTE TCF0 field

From: Gustavo Romero Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set acros

[PULL 15/40] tests/tcg/arm: Use -fno-integrated-as for test-arm-iwmmxt

From: Richard Henderson Clang does not support IWMXT instructions. Fall back to the external assembler. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-11-richard.hender...@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176

[PULL 12/40] tests/tcg/aarch64: Add -fno-integrated-as for sme

From: Richard Henderson The only use of SME is inline assembly. Both gcc and clang only support SME with very recent releases; by deferring detection to the assembler we get better test coverage. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-8-

[PULL 00/40] maintainer updates for testing, plugins and gdbstub

The following changes since commit 5915139aba1646220630596de30c673528e047c9: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2024-07-04 09:16:07 -0700) are available in the Git repository at: https://gitlab.com/stsquad/qemu.git tags/pull-maintainer-july24-050724-1

[PULL 37/40] gdbstub: Pass CPU context to command handler

From: Gustavo Romero Allow passing the current CPU context to command handlers via user_ctx when the handler requires it. Signed-off-by: Gustavo Romero Message-Id: <20240628050850.536447-9-gustavo.rom...@linaro.org> Reviewed-by: Manos Pitsidianakis Signed-off-by: Alex Bennée Message-Id: <2024

[PULL 08/40] tests/tcg/aarch64: Drop -fno-tree-loop-distribute-patterns

From: Richard Henderson This option is not supported by clang, and is not required in order to get sve code generation with gcc 12. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-4-richard.hender...@linaro.org> Signed-off-by: Alex Bennée Message

[PULL 03/40] tracepoints: move physmem trace points

They don't need to be in the global trace-events file and can have a local trace header. Also add address_space_map tracepoint for tracking mapping behaviour. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-4-alex.ben...@linaro.org> diff --git a/syst

[PULL 04/40] hw/core: ensure kernel_end never gets used undefined

Really the problem here is the return values of fit_load_[kernel|fdt]() are a little all over the place. However we don't want to somehow get through not having set kernel_end and having it just be random unused data. The compiler complained on an --enable-gcov build: In file included from ../.

[PULL 07/40] tests/tcg: Adjust variable defintion from cc-option

From: Richard Henderson Define the variable to the compiler flag used, not "y". This avoids replication of the compiler flag itself. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-3-richard.hender...@linaro.org> Signed-off-by: Alex Bennée Messag

[PULL 06/40] tests/tcg/minilib: Constify digits in print_num

From: Richard Henderson This avoids a memcpy to the stack when compiled with clang. Since we don't enable optimization, nor provide memcpy, this results in an undefined symbol error at link time. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Akihiko Odaki M

[PULL 16/40] tests/tcg/arm: Manually register allocate half-precision numbers

From: Akihiko Odaki Clang does not allow specifying an integer as the value of a single precision register. Explicitly move value from a general register. Signed-off-by: Akihiko Odaki [rth: Use one single inline asm block.] Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-

[PULL 14/40] tests/tcg/arm: Drop -N from LDFLAGS

From: Richard Henderson This is redudant with a linker script, and is not supported by clang. Signed-off-by: Richard Henderson Reviewed-by: Akihiko Odaki Message-Id: <20240630190050.160642-10-richard.hender...@linaro.org> Signed-off-by: Alex Bennée Message-Id: <20240705084047.857176-15-alex.b

Re: [PATCH v46 0/5] hw/sd/sdcard: Cleanups before adding eMMC support

On 7/3/24 3:43 PM, Philippe Mathieu-Daudé wrote: (patches from v42 already reviewed not reposted) Since v45: - RAZ/WI on GEN_CMD (Luc & Manos) - Rename sd_cmd_SEND_OP_COND - Introduce TYPE_SDMMC_COMMON Philippe Mathieu-Daudé (5): hw/sd/sdcard: Use spec v3.01 by default hw/sd/sdcard: Add s

Re: About VFIO Device Pass-through on Qemu.

On Fri, 5 Jul 2024 17:08:49 +0800 (CST) tugouxp <13824125...@163.com> wrote: > Hi folks: > > > I have a questions about device vfio pass-through usage snarios, > PCI device pass-throug for example. did the GPA that host physical > memory mapped to Guest vcpu through MMU must be identical wi

Re: [PATCH v1] target/i386: kvm: Block migration when enfore_cpuid is set to false

On Fri, Jul 05, 2024 at 10:22:23AM +, Wang, Wei W wrote: > On Thursday, July 4, 2024 11:59 PM, Peter Xu wrote: > > On Thu, Jul 04, 2024 at 03:10:27PM +, Wang, Wei W wrote: > > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c index > > > > > 4c2e6f3a71..7db4fe4ead 100644 > > > > > --

Re: [PATCH v46 0/5] hw/sd/sdcard: Cleanups before adding eMMC support

On 3/7/24 15:43, Philippe Mathieu-Daudé wrote: (patches from v42 already reviewed not reposted) Since v45: - RAZ/WI on GEN_CMD (Luc & Manos) - Rename sd_cmd_SEND_OP_COND - Introduce TYPE_SDMMC_COMMON Philippe Mathieu-Daudé (5): hw/sd/sdcard: Use spec v3.01 by default hw/sd/sdcard: Add sd_

Re: [PATCH 5/8] aspeed: Set eMMC 'boot-config' property to reflect HW strapping

On 5/7/24 07:38, Cédric Le Goater wrote: On 7/5/24 5:41 AM, Andrew Jeffery wrote: On Thu, 2024-07-04 at 07:36 +0200, Cédric Le Goater wrote: From: Cédric Le Goater When the boot-from-eMMC HW strapping bit is set, use the 'boot-config' property to set the boot config register to boot from the

[PATCH qemu v4 0/1] hw/cxl: Support firmware updates

v4: Trivial rebase due to reordering of patch queue for upstreaming. A couple of white space fixes (checkpatch) This one was waiting on a v3 revision from Davildlohr (which he posted last week) rather than DCD as such, but the various series before this one cause a lot of churn so it's easier

[PATCH v4 1/1] hw/cxl: Support firmware updates

From: Davidlohr Bueso Implement transfer and activate functionality per 3.1 spec for supporting update metadata (no actual buffers). Transfer times are arbitrarily set to ten and two seconds for full and part transfers, respectively. cxl update-firmware mem0 -F fw.img cxl update-firmware mem0

Re: [PATCH] system: Enable the device aliases for or1k, too

On 5/7/24 14:39, Philippe Mathieu-Daudé wrote: On 5/7/24 11:08, Thomas Huth wrote: Now that we've got a "virt" machine for or1k that supports PCI, too, we can also enable the virtio device aliases like we do on other similar platforms. This will e.g. help to run the iotests with qemu-system-or1k

[PATCH v2 2/2] system: Enable the device aliases for or1k, too

From: Thomas Huth Now that we've got a "virt" machine for or1k that supports PCI too (commit 40fef82c4e "hw/openrisc: Add PCI bus support to virt") we can also enable the virtio device aliases like we do on other similar platforms. This will e.g. help to run the iotests with qemu-system-or1k late

[PATCH v2 0/2] system: Enable the device aliases for or1k, too

Respin of Thomas' v1 sorting the definition first. Philippe Mathieu-Daudé (1): system: Sort QEMU_ARCH_VIRTIO_PCI definition Thomas Huth (1): system: Enable the device aliases for or1k, too system/qdev-monitor.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) -- 2

[PATCH v2 1/2] system: Sort QEMU_ARCH_VIRTIO_PCI definition

Sort the QEMU_ARCH_VIRTIO_PCI to simplify adding/removing entries. Signed-off-by: Philippe Mathieu-Daudé --- system/qdev-monitor.c | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index 6af6ef7d66..acdc8b73a3 100

Re: [PATCH] system: Enable the device aliases for or1k, too

On 5/7/24 11:08, Thomas Huth wrote: Now that we've got a "virt" machine for or1k that supports PCI, too, we can also enable the virtio device aliases like we do on other similar platforms. This will e.g. help to run the iotests with qemu-system-or1k later. Indeed, since 2022 in commit 40fef82c4

  1   2   3   >