On 2024/06/29 1:03, Mark Cave-Ayland wrote:
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
Reviewed-by: Akihiko Odaki
On 6/29/24 09:36, Michael Tokarev wrote:
..
+ while (p < end && *t) {
+ if (*t == ' ') {
+ if (g_ascii_isspace(*p)) {
+ ++p;
+ } else {
+ ++t;
}
+ } else if (*t == g_ascii_tolower(*p)) {
+ ++p, ++t;
+
On 6/29/24 09:20, Michael Tokarev wrote:
On 6/28/24 08:49, Vladimir Sementsov-Ogievskiy wrote:
We already know where colon is, so no reason to search for it. Also,
avoid a code, which looks like we forget to check return value of
strchr() to NULL.
Suggested-by: Kevin Wolf
Signed-off-by: Vladim
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.0 was released 2021:
h
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.0 was released 2021:
h
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.0 was released 2021:
h
--
audio/coreaudio.m | 5 -
net/vmnet-bridged.m | 13 +
net/vmnet-common.m| 3 ---
8 files changed, 3 insertions(+), 86 deletions(-)
---
base-commit: 046a64b9801343e2e89eef10c7a48eec8d8c0d4f
change-id: 20240628-macos-d194d420f01a
Best regards,
--
Akihiko Odaki
macOS versions older than 12.0 are no longer supported.
docs/about/build-platforms.rst says:
> Support for the previous major version will be dropped 2 years after
> the new major version is released or when the vendor itself drops
> support, whichever comes first.
macOS 12.0 was released 2021:
h
On 6/28/24 08:49, Vladimir Sementsov-Ogievskiy wrote:
We already know where colon is, so no reason to search for it. Also,
avoid a code, which looks like we forget to check return value of
strchr() to NULL.
Suggested-by: Kevin Wolf
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
This replaces
On Fri, Jun 28, 2024 at 04:20:02PM +0100, Peter Maydell wrote:
> On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki wrote:
> >
> > FDT properties are aligned by 4 bytes, not 8 bytes.
> >
> > Signed-off-by: Akihiko Odaki
> > ---
> > hw/ppc/vof.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
util/cpuinfo-ppc: Add FreeBSD support
Signed-off-by: Brad Smith
---
v2: Use ifndef with PPC_FEATURE2_ARCH_3_1
util/cpuinfo-ppc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c
index 47af55aa0c..f0b9b895f1 100644
--- a/util/cpu
On 2024-06-28 12:19 p.m., Richard Henderson wrote:
On 6/27/24 19:00, Brad Smith wrote:
util/cpuinfo-ppc: Add FreeBSD support
Signed-off-by: Brad Smith
---
With corrected sign-off.
Also this was based on the tcg-next branch.
util/cpuinfo-ppc.c | 7 ++-
1 file changed, 6 insertions(+),
On 6/28/24 10:54, Richard Henderson wrote:
On 6/28/24 05:42, Alex Bennée wrote:
Incorrect brace positions causes an unintended overflow on 32 bit
builds and shenanigans result.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
Suggested-by: Mark Cave-Ayland
Signed-off-by: Alex Benné
On 6/28/24 05:42, Alex Bennée wrote:
The ExecState is shared across the socket and if we want to compare
say 64 bit and 32 bit binaries we need the two to use the same sizes
for things.
Signed-off-by: Alex Bennée
---
contrib/plugins/lockstep.c | 4 ++--
1 file changed, 2 insertions(+), 2 del
On Fri, Jun 28, 2024 at 9:12 PM Pierrick Bouvier
wrote:
> However, even tough I can build the executable, I get this error:
> $ ./build/qemu-system-aarch64 -M virt
> C:\w\qemu\build\qemu-system-aarch64.exe: unknown type 'x-pl011-rust'
>
> Any idea of what could be missing here?
Maybe the underlyi
On Fri, Jun 28, 2024 at 11:27:06AM -0700, Gregor Haas wrote:
> The read() syscall is not guaranteed to return all data from a file. The
> default ROM loader implementation currently does not take this into account,
> instead failing if all bytes are not read at once. This change loads the ROM
> usi
Punch holes only when the image is opened with discard=on or discard=unmap.
Tested by:
- new write-zeroes-unmap iotest on xfs, ext4, and tmpfs
- tests/qemu-iotests/check -raw
- tests/qemu-iotests/check -qcow2
Changes since v2
- Add write-zeroes-unmap iotest
- Fix iotest missing discard=unmap
v2
The test works since we punch holes by default even when opening the
image without discard=on or discard=unmap. Fix the test to enable
discard.
---
tests/qemu-iotests/245 | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qemu-iotests/245 b/tests/qemu-iotests/245
index a934c
When opening an image with discard=off, we punch hole in the image when
writing zeroes, making the image sparse. This breaks users that want to
ensure that writes cannot fail with ENOSPACE by using fully allocated
images[1].
bdrv_co_pwrite_zeroes() correctly disables BDRV_REQ_MAY_UNMAP if we
opene
On Thu, Jun 27, 2024 at 2:42 PM Kevin Wolf wrote:
> Am 26.06.2024 um 18:27 hat Nir Soffer geschrieben:
> > On Wed, Jun 26, 2024 at 12:17 PM Daniel P. Berrangé >
> > wrote:
> >
> > > On Mon, Jun 24, 2024 at 06:08:26PM +0200, Kevin Wolf wrote:
> > > > Am 24.06.2024 um 17:23 hat Stefan Hajnoczi ges
On 6/27/24 16:47, Pierrick Bouvier wrote:
On 6/25/24 11:08, Manos Pitsidianakis wrote:
On Tue, 25 Jun 2024 19:00, Zhao Liu wrote:
[snip]
This is for future-proofing the Rust integration in general. I
haven't been
able to compile under macos yet because bindgen cannot find the system clang
hea
The read() syscall is not guaranteed to return all data from a file. The
default ROM loader implementation currently does not take this into account,
instead failing if all bytes are not read at once. This change loads the ROM
using g_file_get_contents() instead, which correctly reads all data usin
Hi Richard,
On 6/28/24 2:00 PM, Richard Henderson wrote:
On 6/28/24 08:49, Gustavo Romero wrote:
I thought you meant osdep.h should not be included _at all_ in my case, either
in mte_user_helper.h or in mte_user_helper.c. Maybe the wording in the docs
should be "Do not include "qemu/osdep.h" fr
On 6/28/24 05:42, Alex Bennée wrote:
@@ -1885,7 +1885,7 @@ static void ram_block_add(RAMBlock *new_block, Error
**errp)
} else { /* list is empty */
QLIST_INSERT_HEAD_RCU(&ram_list.blocks, new_block, next);
}
-ram_list.mru_block = NULL;
+qatomic_rcu_set(&ram_list.mr
On 6/28/24 05:42, Alex Bennée wrote:
I guess we never noticed and tried to build with this cross image. Fix
the toolchain prefix so we actually build 32 bit images.
Signed-off-by: Alex Bennée
---
tests/docker/dockerfiles/debian-i686-cross.docker | 2 +-
tests/lcitool/refresh
Please ignore this one.
Wrong command and all patches came out as one.
Sorry about that.
On Fri, Jun 28, 2024 at 10:50 AM Deepak Gupta wrote:
>
> `zimop` stands for `may be operations`. `zcmop` stands for compressed
> `may be operations`. For some RISC-V CPU extension, once compiled into
> the bi
Analogous to zimop, there are 8 encodings carved out of illegal space
encodings (c.lui xn, 0) in compressed instructions which are defined
to be zcmops short for compressed may be operations.
Unlike zimops (which write 0 to rd), zcmops don't actually write anything
to any register. Their encodings
This patch adds assigned codepoints for decoder for 32bit instructions
and provide implementation for instruction. If extension is present,
then moves 0 to `rd`.
Signed-off-by: Deepak Gupta
---
target/riscv/insn32.decode | 15 +++
target/riscv/insn_trans/trans_zimops.c.inc |
`zimop` stands for `may be operations`. `zcmop` stands for compressed
`may be operations`. For some RISC-V CPU extension, once compiled into
the binary are part of generated code which can't be gated behind a probe
of whether an instruction set is supported or not. One such example is
`zicfiss` [1]
On 6/24/24 1:55 AM, Thomas Huth wrote:
[...]
I think it should be fine, both functions are basically just a wrapper
around the write() function in sclp.c, with sclp_print() being rather
dumb while printf() is doing the usual string formatting before
writing it out. I think in the long run,
On 6/28/24 05:42, Alex Bennée wrote:
Incorrect brace positions causes an unintended overflow on 32 bit
builds and shenanigans result.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2413
Suggested-by: Mark Cave-Ayland
Signed-off-by: Alex Bennée
---
target/i386/tcg/translate.c | 2 +-
`zimop` stands for `may be operations`. `zcmop` stands for compressed
`may be operations`. For some RISC-V CPU extension, once compiled into
the binary are part of generated code which can't be gated behind a probe
of whether an instruction set is supported or not. One such example is
`zicfiss` [1]
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
meson.build | 13 -
meson_options.txt | 2 --
scripts/meson-buildoptions.sh | 3 ---
3 files changed, 18 deletions(-)
diff --git a/meson.build b/meson.build
index 6e694ecd9fe..54e6b09f4fb
This reverts commit 433cd6d94a8256af70a5200f236dc8047c3c1468.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini
---
util/cpuinfo-i386.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/cpuinfo-i386.c b/util
.bdrv_needs_filename is only set for drivers that also set bdrv_file_open,
i.e. protocol drivers.
So we can make the assertion always, it will always pass for those drivers
that use bdrv_open.
Signed-off-by: Paolo Bonzini
---
block.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff -
It is the only CCOp, among those that compute ZF from one of the cc_op_*
registers, that uses cpu_cc_src. Do not make it the odd one off,
instead use cpu_cc_dst like the others.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 2 +-
target/i386/tcg/
Do not rely on finish->id_block_uaddr, so that there are no casts from
pointer to uint64_t. They break on 32-bit hosts.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/target/i386/
Free the "id_block" name for the binary version of the data.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 30b83f1d77d..6daa8c264cd 10
Free the "id_auth" name for the binary version of the data.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 2d4cfd41e83..a6b063b762c 100
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 16
1 file changed, 16 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 934c514e64f..95bad55bf46 100644
--- a/target/i386/tcg/translate.c
+++ b
Add a Meson option to configure which x86-64 instruction
set to use. QEMU will now default to x86-64-v1 + cmpxchg16b for
64-bit builds (that corresponds to a Pentium 4 for 32-bit builds).
The baseline can be tuned down to Pentium Pro for 32-bit builds (with
-Dx86_version=0), or up as desired.
Ac
POPCNT was missing, and the entries were all out of order after
ADCX/ADOX/ADCOX were moved close to EFLAGS. Just use designated
initializers.
Fixes: 4885c3c4953 ("target-i386: Use ctpop helper", 2017-01-10)
Fixes: cc155f19717 ("target/i386: rewrite flags writeback for ADCX/ADOX",
2024-06-11)
Sig
From: Roman Kiryanov
to use the QEMU headers with a C++ compiler.
Signed-off-by: Roman Kiryanov
Link: https://lore.kernel.org/r/20240618224553.878869-1-r...@google.com
Signed-off-by: Paolo Bonzini
---
include/exec/memory.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 +
util/cpuinfo-i386.c | 1 +
host/include/i386/ho
Handle it like the other arithmetic cc_ops. This simplifies a
bit the implementation of bit test instructions.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 13 +++--
target/i386/tcg/translate.c | 3 +--
2 files changed, 12 insertions(+)
This reverts commit 45ccdbcb24baf99667997fac5cf60318e5e7db51.
The x86-64 instruction set can now be tuned down to x86-64 v1
or i386 Pentium Pro.
Signed-off-by: Paolo Bonzini
---
host/include/i386/host/cpuinfo.h | 1 +
tcg/i386/tcg-target.h| 5 +++--
util/cpuinfo-i386.c |
From: Richard Henderson
hwaddr uses HWADDR_PRIx, sizeof yields size_t so uses %zu,
and gsize uses G_GSIZE_FORMAT.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Link:
https://lore.kernel.org/r/20240626194950.1725800-4-richard.hender...@linaro.org
Signed-off-by: Paolo Bon
From: Richard Henderson
This code was using both uint32_t and uint64_t for len.
Consistently use size_t instead.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Link:
https://lore.kernel.org/r/20240626194950.1725800-3-richard.hender...@linaro.org
Signed-off-by: Paolo Bonz
Do not rely on finish->id_auth_uaddr, so that there are no casts from
pointer to uint64_t. They break on 32-bit hosts.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/i386
The typeof_strip_qual() is most useful for the atomic fetch-and-modify
operations in atomic.h, but it can be used elsewhere as well. For example,
QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a
requirement.
Move the macro to compiler.h and, while at it, move it under #if
The set of BlockDrivers that have .bdrv_file_open coincides with those
that have .protocol_name and guess what---checking drv->bdrv_file_open
is done to see if the driver is a protocol. So check drv->protocol_name
instead.
Signed-off-by: Paolo Bonzini
---
block.c | 11 +--
1 file change
bdrv_file_open and bdrv_open are completely equivalent, they are
never checked except to see which one to invoke. So merge them
into a single one.
Signed-off-by: Paolo Bonzini
---
include/block/block_int-common.h | 3 ---
block.c | 4 +---
block/blkdebug.c
Since there is no bdrv_file_open callback anymore, rename the implementations
so that they end with "_open" instead of "_file_open". NFS is the exception
because all the functions are named nfs_file_*.
Suggested-by: Kevin Wolf
Signed-off-by: Paolo Bonzini
---
block/blkio.c | 8
block/
From: Roman Kiryanov
void* pointer arithmetic is a GCC extentension which could not be
available in other build tools (e.g. C++). This changes removes this
assumption.
Signed-off-by: Roman Kiryanov
Suggested-by: Paolo Bonzini
Link: https://lore.kernel.org/r/20240620201654.598024-1-r...@google.
The following changes since commit 28b8a57ad63670aa0ce90334523dc552b13b4336:
Merge tag 'pull-riscv-to-apply-20240627-1' of
https://github.com/alistair23/qemu into staging (2024-06-27 07:36:16 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstrea
Treat it as a MIPS64 machine.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
Signed-off-by: Paolo Bonzini
---
configure | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure b/configure
index 5ad1674ca5f..8b6a2f16ceb 100755
--- a/configure
+++ b/configure
On 6/27/24 06:58, Akihiko Odaki wrote:
clang version 18.1.6 does not support x constraint for AArch64.
Use w instead.
Signed-off-by: Akihiko Odaki
---
tests/tcg/arm/fcvt.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
Oops, this was an error from the beginning.
Revie
On 6/27/24 06:58, Akihiko Odaki wrote:
irg expects 64-bit integers. Passing a 32-bit integer results in
compilation failure with clang version 18.1.6.
Signed-off-by: Akihiko Odaki
---
tests/tcg/aarch64/mte-1.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Hender
On 6/27/24 06:58, Akihiko Odaki wrote:
clang version 18.1.6 assumes a register is 64-bit by default and
complains if a 32-bit value is given. Explicitly specify register width
when passing a 32-bit value.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
---
tests/tcg/aarch64/bt
On 6/27/24 06:58, Akihiko Odaki wrote:
sme-smopa-2.c requires sme-i16i64 but the compiler option used not to
specify it. Instead, the extension was specified with the inline
assembly, resulting in mixing assembly code targeting sme-i1664 and C
code that does not target sme-i1664.
clang version 1
On 6/27/24 06:58, Akihiko Odaki wrote:
The test cases for "converting double-precision to single-precision"
emits float but the result variable was typed as uint32_t and corrupted
the printed values. Propertly type it as float.
Signed-off-by: Akihiko Odaki
Fixes: 8ec8a55e3fc9 ("tests/tcg/arm: ad
Hi Igor
On Fri, 28 Jun 2024 at 13:25, Igor Mammedov wrote:
>
> On Fri, 7 Jun 2024 14:17:24 +
> Ricardo Ribalda wrote:
>
> > Signed-off-by: Ricardo Ribalda
> > ---
> > tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/tests/qtest/b
On 6/28/24 08:49, Gustavo Romero wrote:
I thought you meant osdep.h should not be included _at all_ in my case, either
in mte_user_helper.h or in mte_user_helper.c. Maybe the wording in the docs
should be "Do not include "qemu/osdep.h" from header files. Include it from .c
files, when necessary."
On 6/28/24 09:37, Philippe Mathieu-Daudé wrote:
On 28/6/24 16:31, Richard Henderson wrote:
On 6/19/24 05:49, Philippe Mathieu-Daudé wrote:
Merge gdbstub64.c in gdbstub.c and remove uses of
target specific TARGET_AARCH64 definition.
Small step toward single ARM/Aarch64 binary.
Philippe Mathieu-
On 28/6/24 16:31, Richard Henderson wrote:
On 6/19/24 05:49, Philippe Mathieu-Daudé wrote:
Merge gdbstub64.c in gdbstub.c and remove uses of
target specific TARGET_AARCH64 definition.
Small step toward single ARM/Aarch64 binary.
Philippe Mathieu-Daudé (2):
target/arm: Merge gdbstub64.c withi
On Fri, 28 Jun 2024 at 17:01, Richard Henderson
wrote:
>
> On 6/28/24 07:23, Peter Maydell wrote:
> > To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR
> > view of floating point control and status (such as the FEAT_AFP ones),
> > we need to make sure those bits can be migrated.
On 28/6/24 18:03, Mark Cave-Ayland wrote:
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h | 7 +--
2 files changed, 1
On 6/27/24 19:00, Brad Smith wrote:
util/cpuinfo-ppc: Add FreeBSD support
Signed-off-by: Brad Smith
---
With corrected sign-off.
Also this was based on the tcg-next branch.
util/cpuinfo-ppc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/util/cpuinfo-ppc.c b/uti
On 28/6/24 17:49, Gustavo Romero wrote:
Hi Phil,
On 6/28/24 4:08 AM, Philippe Mathieu-Daudé wrote:
On 28/6/24 07:08, Gustavo Romero wrote:
Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this fi
On 6/28/24 07:23, Peter Maydell wrote:
In order to allow FPCR bits that aren't in the FPSCR (like the new
bits that are defined for FEAT_AFP), we need to make sure that writes
to the FPSCR only write to the bits of FPCR that are architecturally
mapped, and not the others.
Implement this with a n
On 6/28/24 07:23, Peter Maydell wrote:
Now that we store FPSR and FPCR separately, the FPSR_MASK and
FPCR_MASK macros are slightly confusingly named and the comment
describing them is out of date. Rename them to FPSCR_FPSR_MASK and
FPSCR_FPCR_MASK, document that they are the mask of which FPSCR
On 6/28/24 07:23, Peter Maydell wrote:
The QC, N, Z, C, V bits live in the FPSR, not the FPCR. Rename the
macros that define these bits accordingly.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h | 17 ++---
target/arm/tcg/mve_helper.c | 8
tar
On 6/28/24 07:23, Peter Maydell wrote:
Now that we have refactored the set/get functions so that the FPSCR
format is no longer the authoritative one, we can keep FPSR and FPCR
in separate CPU state fields.
As well as the get and set functions, we also have a scattering of
places in the code whic
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Peter Maydell
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h | 7 +--
2 files changed, 11 insertions(+), 6 deletions(-)
v2:
- Delete d
On 6/28/24 07:23, Peter Maydell wrote:
We already have a load_cpu_field_low32() to load the low half of a
64-bit CPU struct field to a TCGv_i32; however we haven't yet needed
the store equivalent. We'll want that in the next patch, so
implement it.
Signed-off-by: Peter Maydell
---
target/arm/
On 6/28/24 07:23, Peter Maydell wrote:
To support FPSR and FPCR bits that don't exist in the AArch32 FPSCR
view of floating point control and status (such as the FEAT_AFP ones),
we need to make sure those bits can be migrated. This commit allows
that, whilst maintaining backwards and forwards mig
On 28/06/2024 16:28, Peter Maydell wrote:
On Fri, 28 Jun 2024 at 11:55, Mark Cave-Ayland
wrote:
This prevents the IRQs from being leaked when the macio IDE device is used.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/macio.c| 10 ++
include/hw/misc/macio/macio.h |
On 6/28/24 07:23, Peter Maydell wrote:
+void vfp_set_fpsr(CPUARMState *env, uint32_t val)
+{
+ARMCPU *cpu = env_archcpu(env);
+
+vfp_set_fpsr_to_host(env, val);
+
+if (arm_feature(env, ARM_FEATURE_NEON) ||
+cpu_isar_feature(aa32_mve, cpu)) {
+/*
+ * The bit we
Hi Phil,
On 6/28/24 4:08 AM, Philippe Mathieu-Daudé wrote:
On 28/6/24 07:08, Gustavo Romero wrote:
Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this field as well, so keep it as a separate fun
On Fri, Jun 28, 2024, 5:52 AM Markus Armbruster wrote:
> John Snow writes:
>
> > We do not need a dedicated section for notes. By eliminating a specially
> > parsed section, these notes can be treated as normal rST paragraphs in
> > the new QMP reference manual, and can be placed and styled much
On 6/28/24 07:23, Peter Maydell wrote:
In AArch32, the floating point control and status bits are all in a
single register, FPSCR. In AArch64, these were split into separate
FPCR and FPSR registers, but the bit layouts remained the same, with
no overlaps, so that you could construct an FPSCR val
On Fri, 28 Jun 2024 at 11:55, Mark Cave-Ayland
wrote:
>
> This prevents the IRQs from being leaked when the macio IDE device is used.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/ide/macio.c| 10 ++
> include/hw/misc/macio/macio.h | 5 +
> 2 files changed, 11 inser
On Fri, Jun 28, 2024, 11:10 AM John Snow wrote:
>
>
> On Fri, Jun 28, 2024, 3:55 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Sphinx does not like sections without titles, because it wants to
>> > convert every section into a reference. When there is no title, it
>> > struggles to
On Thu, 27 Jun 2024 at 14:41, Akihiko Odaki wrote:
>
> These GThreads are never referenced.
>
> Signed-off-by: Akihiko Odaki
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, Jun 28, 2024, 9:24 AM Markus Armbruster wrote:
> John Snow writes:
>
> > This is a directive that creates a syntactic sugar for creating
> > "Example" boxes very similar to the ones already used in the bitmaps.rst
> > document, please see e.g.
> >
> https://www.qemu.org/docs/master/inter
On Thu, 27 Jun 2024 at 14:40, Akihiko Odaki wrote:
>
> This fixes LeakSanitizer warnings.
>
> Signed-off-by: Akihiko Odaki
> ---
> tests/qtest/libqtest.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c
> index f89da7b80797..1605c0c9f615 10
On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki wrote:
>
> FDT properties are aligned by 4 bytes, not 8 bytes.
>
> Signed-off-by: Akihiko Odaki
> ---
> hw/ppc/vof.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c
> index e3b430a81f4f..b5b6514d79fc
On Fri, Jun 28, 2024, 9:09 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Factor out the compatibility parser helper so it can be shared by other
> > directives.
>
> Suggest "Factor out the compatibility parser helper into a base class,
> so it can be shared by other directives."
Sure.
Gustavo Romero writes:
> Hi Alex,
>
> On 6/28/24 9:14 AM, Alex Bennée wrote:
>> Gustavo Romero writes:
>>
>>> Factor out the code used for setting the MTE TCF0 field from the prctl
>>> code into a convenient function. Other subsystems, like gdbstub, need to
>>> set this field as well, so keep i
On Thu, 27 Jun 2024 at 14:39, Akihiko Odaki wrote:
>
> This fixes LeakSanitizer warnings.
>
> Signed-off-by: Akihiko Odaki
> ---
> hw/core/cpu-common.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
> index f131cde2c038..a3073c17d098 100644
>
On Fri, Jun 28, 2024, 3:55 AM Markus Armbruster wrote:
> John Snow writes:
>
> > Sphinx does not like sections without titles, because it wants to
> > convert every section into a reference. When there is no title, it
> > struggles to do this and transforms the tree inproperly.
> >
> > Depending
On Sat, 22 Jun 2024 at 13:57, Ryan Wendland wrote:
>
> When a usb device is disconnected the transfer service functions bails
> before appropraite transfer error flags are set.
(typo: "appropriate")
> This patch sets the appropriate condition code OHCI_CC_DEVICENOTRESPONDING
> when a device is d
On 6/28/24 07:23, Peter Maydell wrote:
The M-profile FPSCR LTPSIZE is bits [18:16]; this is the same
field as A-profile FPSCR Len, not Stride. Correct the comment
in vfp_get_fpscr().
We also implemented M-profile FPSCR.QC, but forgot to delete
a TODO comment from vfp_set_fpscr(); remove it now.
The frontend can use this command to retrieve
VIRTIO Shared Memory Regions configuration from
the backend. The response contains the number of
shared memory regions, their size, and shmid.
This is useful when the frontend is unaware of
specific backend type and configuration,
for example, in the `
With SHMEM_MAP messages, sharing descriptors between
devices will cause that these devices do not see the
mappings, and fail to access these memory regions.
To solve this, introduce MEM_READ/WRITE requests
that will get triggered as a fallback when
vhost-user memory translation fails.
Signed-off-
Implement function handlers for memory read and write
operations.
Signed-off-by: Albert Esteve
---
hw/virtio/vhost-user.c | 34 ++
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/hw/virtio/vhost-user.c b/hw/virtio/vhost-user.c
index 18cacb2d68..79be
Hi all,
v1->v2:
- Corrected typos and clarifications from
first review
- Added SHMEM_CONFIG frontend request to
query VIRTIO shared memory regions from
backends
- vhost-user-device to use SHMEM_CONFIG
to request and initialise regions
- Added MEM_READ/WRITE backend requests
in case addre
Add a cache BAR in the vhost-user-device
into which files can be directly mapped.
The number, shmid, and size of the VIRTIO Shared
Memory subregions is retrieved through a get_shmem_config
message sent by the vhost-user-base module
on the realize step, after virtio_init().
By default, if VHOST_US
Add SHMEM_MAP/UNMAP requests to vhost-user to
handle VIRTIO Shared Memory mappings.
This request allows backends to dynamically map
fds into a VIRTIO Shared Memory Region indentified
by its `shmid`. Then, the fd memory is advertised
to the driver as a base addres + offset, so it
can be read/writte
Hi Alex,
On 6/28/24 9:14 AM, Alex Bennée wrote:
Gustavo Romero writes:
Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this field as well, so keep it as a separate function to avoid
duplication
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