Re: [PATCH v2] tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers

在 2024/6/19 下午1:50, Richard Henderson 写道: Simplify the logic for two-part, 32-bit pc-relative addresses. Rather than assume all such fit in int32_t, do some arithmetic and assert a result, do some arithmetic first and then check to see if the pieces are in range. Reported-by: Song Gao Signed-of

Re: [PATCH] hw/gpio/aspeed: Add bounds checking for register table access

Hi Andrew, On Wed, Jun 19, 2024 at 1:58 AM Andrew Jeffery wrote: > Hello Zheyu Ma, > > On Tue, 2024-06-18 at 15:09 +0200, Zheyu Ma wrote: > > Added bounds checking in the aspeed_gpio_read() and aspeed_gpio_write() > > functions to ensure the index idx is within the valid range of the > > reg_tab

Re: [PATCH 03/13] docs/qapidoc: delint a tiny portion of the module

John Snow writes: > In a forthcoming series that adds a new QMP documentation generator, it > will be helpful to have a linting baseline. However, there's no need to > shuffle around the deck chairs too much, because most of this code will > be removed once that new qapidoc generator (the "transm

Re: [PATCH 2/2] target/ppc/arch_dump: set prstatus pid to cpuid

On 19/06/2024 07.00, Omar Sandoval wrote: Every other architecture does this, and debuggers need it to be able to identify which prstatus note corresponds to which CPU. Signed-off-by: Omar Sandoval --- target/ppc/arch_dump.c | 21 - 1 file changed, 12 insertions(+), 9 del

Re: [PATCH 1/2] target/s390x/arch_dump: use correct byte order for pid

On 19/06/2024 07.00, Omar Sandoval wrote: The pid field of prstatus needs to be big endian like all of the other fields. Fixes: f738f296eaae ("s390x/arch_dump: pass cpuid into notes sections") Signed-off-by: Omar Sandoval --- target/s390x/arch_dump.c | 2 +- 1 file changed, 1 insertion(+), 1

[PATCH] MAINTAINERS: Cover all tests/qtest/migration-* files

Beside migration-test.c, there is nowadays migration-helpers.[ch], too, so update the entry in the migration section to also cover these files now. While we're at it, exclude these files in the common qtest section, since the migration test is well covered by the migration maintainers already. Sinc

[PATCH v2] tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers

Simplify the logic for two-part, 32-bit pc-relative addresses. Rather than assume all such fit in int32_t, do some arithmetic and assert a result, do some arithmetic first and then check to see if the pieces are in range. Reported-by: Song Gao Signed-off-by: Richard Henderson --- Hi Song. I wa

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On 6/11/24 03:33, Manos Pitsidianakis wrote: This commit adds a re-implementation of hw/char/pl011.c in Rust. It uses generated Rust bindings (produced by `ninja aarch64-softmmu-generated.rs`) to register itself as a QOM type/class. How to build: 1. Make sure rust, cargo and bindgen (cargo ins

[PATCH 2/2] target/ppc/arch_dump: set prstatus pid to cpuid

Every other architecture does this, and debuggers need it to be able to identify which prstatus note corresponds to which CPU. Signed-off-by: Omar Sandoval --- target/ppc/arch_dump.c | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/ppc/arch_dump.c

[PATCH 1/2] target/s390x/arch_dump: use correct byte order for pid

The pid field of prstatus needs to be big endian like all of the other fields. Fixes: f738f296eaae ("s390x/arch_dump: pass cpuid into notes sections") Signed-off-by: Omar Sandoval --- target/s390x/arch_dump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/s390x/arch_d

[PATCH 0/2] arch_dump: fix prstatus pid on s390x and ppc

Hello, I maintain drgn [1], a debugger for the Linux kernel. I ran into a quirk of the NT_PRSTATUS note in kernel core dumps [2], so I looked into how QEMU's dump-guest-memory command generates NT_PRSTATUS. I noticed that on most architectures, the note's PID field is set to the CPU ID plus 1. The

Re: [RFC PATCH v2 1/5] build-sys: Add rust feature option

On 6/11/24 03:33, Manos Pitsidianakis wrote: Add options for Rust in meson_options.txt, meson.build, configure to prepare for adding Rust code in the followup commits. `rust` is a reserved meson name, so we have to use an alternative. `with_rust` was chosen. A cargo_wrapper.py script is added t

Re: [PATCH 9/9] contrib/plugins: add ips plugin example for cost modeling

On 6/18/24 02:53, Alex Bennée wrote: Pierrick Bouvier writes: On 6/17/24 13:56, Dr. David Alan Gilbert wrote: * Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote: On 6/14/24 15:00, Dr. David Alan Gilbert wrote: * Pierrick Bouvier (pierrick.bouv...@linaro.org) wrote: Hi Dave, On 6/12/24

Re: [RFC PATCH v2 0/5] Implement ARM PL011 in Rust

On 6/11/24 03:33, Manos Pitsidianakis wrote: If `cargo` and `bindgen` is installed in your system, you should be able to build qemu-system-aarch64 with configure flag --enable-rust and launch an arm virt VM. One of the patches hardcodes the default UART of the machine to the Rust one, so if somet

Re: [PATCH v2] virtio-pci: Fix the use of an uninitialized irqfd.

On Mon, Jun 17, 2024 at 6:38 PM Philippe Mathieu-Daudé wrote: > > Hi Cindy, > > On 17/6/24 11:55, Cindy Lu wrote: > > The crash was reported in MAC OS and NixOS, here is the link for this bug > > https://gitlab.com/qemu-project/qemu/-/issues/2334 > > https://gitlab.com/qemu-project/qemu/-/issues/2

PING: [PATCH v6 00/10] Support persistent reservation operations

Hi, Klaus, the pr related operations of the nvme layer are almost ready. Stefan, the block layer has been modified according to your comments. Please help review the code again. Thanks! On 2024/6/13 15:13, Changqi Lu wrote: > Hi, > > patch v6 has been modified. > > v5->v6: > - Add relevant comm

Re: [PULL v1 0/3] Xilinx DMA/Ethernet updates

On 6/18/24 08:49, Edgar E. Iglesias wrote: From: "Edgar E. Iglesias" The following changes since commit 900536d3e97aed7fdd9cb4dadd3bf7023360e819: Merge tag 'dirtylimit-dirtyrate-pull-request-20240617' ofhttps://github.com/newfriday/qemu into staging (2024-06-17 11:40:24 -0700) are availab

Re: [PATCH] hw/arm/virt-acpi-build: Drop local iort_node_offset

On 6/18/24 17:17, Nicolin Chen wrote: Both the other two callers of build_iort_id_mapping() just directly pass in the IORT_NODE_OFFSET macro. Keeping a "const uint32_t" local variable storing the same value doesn't have any gain. Simplify this by replacing the only place using this local variabl

Re: [PATCH v2] exec: use char* for pointer arithmetic

On 6/18/24 17:04, Roman Kiryanov wrote: void* pointer arithmetic is not in the C standard. This change allows using the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I5a064853429f627c17a9213910811dea4ced6174 Signed-off-by: Roman Kiryanov --- v2: change `char*` into `char

Re: [PATCH v2 02/10] migration: Rename thread debug names

On 18/06/2024 02:15, Peter Xu wrote: > The postcopy thread names on dest QEMU are slightly confusing, partly I'll > need to blame myself on 36f62f11e4 ("migration: Postcopy preemption > preparation on channel creation"). E.g., "fault-fast" reads like a fast > version of "fault-default", but it's

Re: Historical QAPI schema parser, "compiled schema", and qapi-schema-diff

On Thu, Jun 13, 2024 at 12:12 PM Daniel P. Berrangé wrote: > On Thu, Jun 13, 2024 at 02:13:15AM -0400, John Snow wrote: > > Hi, recently I've been working on overhauling our QMP documentation; see > > https://jsnow.gitlab.io/qemu/qapi/index.html for a recent > work-in-progress > > page showcasing

[PATCH 12/13] qapi/parser: don't parse rST markup as section headers

The double-colon synax is rST formatting that precedes a literal code block. We do not want to capture these as QAPI-specific sections. Coerce blocks that start with e.g. "Example::" to be parsed as untagged paragraphs instead of special tagged sections. Signed-off-by: John Snow --- scripts/qap

[PATCH 13/13] qapi: convert "Example" sections to rST

Eliminate the "Example" sections in QAPI doc blocks, converting them into QMP example code blocks. This is generally done in this patch by converting "Example:" or "Examples:" lines into ".. code-block:: QMP" lines. The old "Example:" or "Examples:" syntax is now caught as an error; but with the p

[PATCH 11/13] qapi: add markup to note blocks

Generally, surround command-line options with ``literal`` markup to help it stand out from prose in rendered HTML, and add cross-references to replace "see also" messages. References to types, values, and other QAPI definitions are not yet adjusted here; they will be converted en masse in a subseq

[PATCH 05/13] qapi/parser: fix comment parsing immediately following a doc block

If a comment immediately follows a doc block, the parser doesn't ignore that token appropriately. Fix that. e.g. > ## > # = Hello World! > ## > > # I'm a comment! will break the parser, because it does not properly ignore the comment token if it immediately follows a doc block. Fixes: 3d035cd2c

[PATCH 10/13] qapi: update prose in note blocks

Where I've noticed, rephrase the note to read more fluently. Signed-off-by: John Snow --- qapi/block-core.json | 4 ++-- qga/qapi-schema.json | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qapi/block-core.json b/qapi/block-core.json index cacedfb771c..9ef23ec02ae 100644 -

[PATCH 08/13] qapi: ensure all errors sections are uniformly typset

Transactions have the only instance of an Errors section that isn't a rST list; turn it into one. Signed-off-by: John Snow --- docs/devel/qapi-code-gen.rst | 7 +++ qapi/transaction.json| 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/docs/devel/qapi-code-gen.rst

[PATCH 07/13] qapi: fix non-compliant JSON examples

The new QMP documentation generator wants to parse all examples as "QMP". We have an existing QMP lexer in docs/sphinx/qmp_lexer.py (Seen in-use here: https://qemu-project.gitlab.io/qemu/interop/bitmaps.html) that allows the use of "->", "<-" and "..." tokens to denote QMP protocol flow with elisio

[PATCH 09/13] qapi: convert "Note" sections to plain rST

We do not need a dedicated section for notes. By eliminating a specially parsed section, these notes can be treated as normal rST paragraphs in the new QMP reference manual, and can be placed and styled much more flexibly. Convert all existing "Note" and "Notes" sections to pure rST. As part of th

[PATCH 01/13] [DO-NOT-MERGE]: Add some ad-hoc linting helpers.

These aren't ready for upstream inclusion, because they do not properly manage version dependencies, execution environment and so on. These are just the tools I use in my Own Special Environment :tm: for testing and debugging. They've been tested only on Fedora 38 for right now, which means: Pyth

[PATCH 03/13] docs/qapidoc: delint a tiny portion of the module

In a forthcoming series that adds a new QMP documentation generator, it will be helpful to have a linting baseline. However, there's no need to shuffle around the deck chairs too much, because most of this code will be removed once that new qapidoc generator (the "transmogrifier") is in place. To

[PATCH 06/13] docs/qapidoc: fix nested parsing under untagged sections

Sphinx does not like sections without titles, because it wants to convert every section into a reference. When there is no title, it struggles to do this and transforms the tree inproperly. Depending on the rST used, this may result in an assertion error deep in the docutils HTMLWriter. (Observed

[PATCH 00/13] qapi: convert "Note" and "Example" sections to rST

This series focuses primarily on converting our existing QAPI/QMP documentation to remove special "Note" and "Example" sections in favor of rST markup for the same. This is being done primarily to reduce the number of specially parsed QAPI sections we have in favor of allowing fully arbitrary rST

[PATCH 04/13] qapi/parser: preserve indentation in QAPIDoc sections

Change get_doc_indented() to preserve indentation on all subsequent text lines, and create a compatibility dedent() function for qapidoc.py to remove that indentation. This is being done for the benefit of a new qapidoc generator which requires that indentation in argument and features sections are

[PATCH 02/13] qapi: linter fixups

Fix minor irritants to pylint/flake8 et al. (Yes, these need to be guarded by the Python tests. That's a work in progress, a series that's quite likely to follow once I finish this Sphinx project. Please pardon the temporary irritation.) Signed-off-by: John Snow Reviewed-by: Markus Armbruster -

[PATCH] hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev

The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config(). Do it directly instead of bridging with an iommu mr pointer. Signed-off-by: Nicolin Chen --- hw/arm/smmu-common.c | 8 ++-- hw/arm/smmuv3.c | 12 include/hw/arm/smmu-common.h | 4 ++-

[PATCH] hw/arm/virt-acpi-build: Drop local iort_node_offset

Both the other two callers of build_iort_id_mapping() just directly pass in the IORT_NODE_OFFSET macro. Keeping a "const uint32_t" local variable storing the same value doesn't have any gain. Simplify this by replacing the only place using this local variable with the macro directly. Signed-off-b

Re: [PATCH 3/3] exec: use char* for pointer arithmetic

Hi Richard, On Tue, Jun 18, 2024 at 4:05 PM Richard Henderson wrote: > We require "char *" with a space. thank you for looking into this. I sent v2 for this one.

[PATCH v2] exec: use char* for pointer arithmetic

void* pointer arithmetic is not in the C standard. This change allows using the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I5a064853429f627c17a9213910811dea4ced6174 Signed-off-by: Roman Kiryanov --- v2: change `char*` into `char *` (add the missing space). include/exe

Re: [PATCH] hw/gpio/aspeed: Add bounds checking for register table access

Hello Zheyu Ma, On Tue, 2024-06-18 at 15:09 +0200, Zheyu Ma wrote: > Added bounds checking in the aspeed_gpio_read() and aspeed_gpio_write() > functions to ensure the index idx is within the valid range of the > reg_table array. > > The correct size of reg_table is determined dynamically based on

Re: [RFC PATCH] cxl: avoid duplicating report from MCE & device

On 6/18/24 9:53 AM, Shiyang Ruan wrote: > Background: > Since CXL device is a memory device, while CPU consumes a poison page of > CXL device, it always triggers a MCE by interrupt (INT18), no matter > which-First path is configured. This is the first report. Then > currently, in FW-First p

Re: [PATCH 4/9] sysemu: add set_virtual_time to accel ops

On 6/12/24 08:35, Alex Bennée wrote: We are about to remove direct calls to individual accelerators for this information and will need a central point for plugins to hook into time changes. From: Alex Bennée You don't need a from in the middle. :-) Reviewed-by: Philippe Mathieu-Daudé Signed

Re: [PATCH 3/9] plugins: Ensure register handles are not NULL

On 6/12/24 08:35, Alex Bennée wrote: From: Akihiko Odaki Ensure register handles are not NULL so that a plugin can assume NULL is invalid as a register handle. Signed-off-by: Akihiko Odaki Message-Id:<20240229-null-v1-1-e716501d9...@daynix.com> Signed-off-by: Alex Bennée --- plugins/api.c | 4

Re: [PATCH 2/9] gdbstub: move enums into separate header

On 6/12/24 08:35, Alex Bennée wrote: This is an experiment to further reduce the amount we throw into the exec headers. It might not be as useful as I initially thought because just under half of the users also need gdbserver_start(). Signed-off-by: Alex Bennée --- include/exec/gdbstub.h|

Re: [PATCH 1/9] include/exec: add missing include guard comment

On 6/12/24 08:35, Alex Bennée wrote: Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 3/3] exec: use char* for pointer arithmetic

On 6/18/24 15:46, Roman Kiryanov wrote: @@ -2839,7 +2839,7 @@ static inline uint8_t address_space_ldub_cached(MemoryRegionCache *cache, { assert(addr < cache->len); if (likely(cache->ptr)) { -return ldub_p(cache->ptr + addr); +return ldub_p((char*)cache->ptr + addr)

Re: [PATCH 2/3] exec: avoid using C++ keywords in function parameters

On 6/18/24 15:45, Roman Kiryanov wrote: to use the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: Ic4e49b9c791616bb22c973922772b0494706092c Signed-off-by: Roman Kiryanov --- include/exec/memory.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: R

Re: [PATCH 1/3] exec: Make the MemOp enum cast explicit

On 6/18/24 15:45, Roman Kiryanov wrote: to use the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I785f2e65d192287f1f964d2840131b653755648c Signed-off-by: Roman Kiryanov --- include/exec/memop.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/includ

Re: [PATCH 23/23] Add get_ucontext_sigreturn function

On 6/17/24 11:58, Ajeet Singh wrote: From: Stacey Son Function checks the processor state to ensure that the current execution mode is EL0 and no flags indicating interrupts or exceptions are set Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 18 ++

Re: [PATCH 22/23] Add set_mcontext function for ARM AArch64 in bsd-user

On 6/17/24 11:58, Ajeet Singh wrote: From: Stacey Son The function copies register values from the provided target_mcontext_t structure to the CPUARMState registers Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 22 ++ 1 file chang

Re: [PATCH 21/23] Add setup_sigframe_arch function for ARM AArch64 in bsd-user

On 6/17/24 11:58, Ajeet Singh wrote: From: Warner Losh The function utilizes the `get_mcontext` function to retrieve the machine context for the current CPUARMState Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/signal.c | 14 ++ 1 file changed, 14 ins

Re: [PATCH 20/23] Add get_mcontext function for ARM AArch64 in bsd-user

On 6/17/24 11:58, Ajeet Singh wrote: From: Stacey Son function to retrieve machine context,it populates the provided target_mcontext_t structure with information from the CPUARMState registers Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans --- bsd-user/aar

[PATCH 3/3] exec: use char* for pointer arithmetic

void* pointer arithmetic is not in the C standard. This change allows using the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I5a064853429f627c17a9213910811dea4ced6174 Signed-off-by: Roman Kiryanov --- include/exec/memory.h | 8 include/exec/memo

[PATCH 2/3] exec: avoid using C++ keywords in function parameters

to use the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: Ic4e49b9c791616bb22c973922772b0494706092c Signed-off-by: Roman Kiryanov --- include/exec/memory.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/memory.h b/include/exec/memory.h

[PATCH 1/3] exec: Make the MemOp enum cast explicit

to use the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I785f2e65d192287f1f964d2840131b653755648c Signed-off-by: Roman Kiryanov --- include/exec/memop.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/exec/memop.h b/include/exec/memop.h index

Re: [PATCH 19/23] Add ARM AArch64 signal trampoline argument setup for bsd-user

On 6/17/24 11:58, Ajeet Singh wrote: From: Stacey Son function to set up signal handler arguments it populates register values in `CPUARMState` based on the provided signal, signal frame, signal action, and frame address Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch6

Re: [PATCH 18/23] Add ARM AArch64 specific signal definitions for bsd-user

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son Defined register indices and sizes,introduced structures to represent general purpose registers, floating point registers, and machine context Signed-off-by: Stacey Son Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-authored-by

Re: [PATCH 17/23] Add ARM AArch64 sigcode setup function for bsd-user

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son signal trampoline function initializes a sequence of instructions to handle signal returns and exits, and copies this code to the target offset. Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_sigtr

Re: [PATCH 16/23] Add function to retrieve additional ARM AArch64 hwcap

On 6/17/24 11:57, Ajeet Singh wrote: From: Warner Losh Function to retrieve the extended hardware capability flags Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 29 + 1 file changed, 29 insertions(+) Reviewed-by:

Re: [PATCH 15/23] Add function to retrieve ARM AArch64 hardware capabilities

On 6/17/24 11:57, Ajeet Singh wrote: From: Warner Losh The function initializes default hardware capabilities and finds additional features using the `GET_FEATURE_ID` macro Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 38 ++

Re: [PATCH 14/23] Add ARM AArch64 hardware capability definitions

On 6/17/24 11:57, Ajeet Singh wrote: From: Warner Losh Defined a huge list of hardware capabilites and added macros for retrieving hwcap flags Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_elf.h | 61 ++ 1 file changed, 61

Re: [PATCH 13/23] Add ARM AArch64 ELF definitions for bsd-user

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son Defined mmap and dynamic load adresses and set various elf parameters Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Kyle Evans --- bsd-user/aarch64/target_arch_elf.h | 37 ++ 1 file chang

Re: [PATCH 12/23] Add ability to get rval2

On 6/17/24 11:57, Ajeet Singh wrote: From: Warner Losh Function accesses the x1 register which holds the value Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh --- bsd-user/aarch64/target_arch_vmparam.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/bsd-user/aarch64/target

Re: [PATCH 11/23] Update ARM AArch64 VM parameter definitions for bsd-user

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son Defined address spaces for FreeBSD/arm64 and added function for getting stack pointer from CPU and setting a return value. Signed-off-by: Stacey Son Signed-off-by: Warner Losh Signed-off-by: Ajeet Singh Co-authored-by: Sean Bruno Co-aut

Re: [PATCH 10/23] Add thread initialization for BSD-USER

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son Initializes thread's register state Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke --- bsd-user/aarch64/target_arch_thread.h | 16 1 file changed, 16 insertions(+) diff --git a/bs

Re: [PATCH 09/23] Add thread setup for BSD-USER

On 6/17/24 11:57, Ajeet Singh wrote: From: Stacey Son Function for setting up thread upcall which will add thread support to BSD-User Signed-off-by: Stacey Son Signed-off-by: Ajeet Singh Co-authored-by: Jessica Clarke --- bsd-user/aarch64/target_arch_thread.h | 45

Re: [PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

On Tue, Jun 18, 2024 at 02:51:41PM -0700, Nicolin Chen wrote: > On Tue, Jun 18, 2024 at 05:34:21PM -0400, Michael S. Tsirkin wrote: > > On Tue, Jun 18, 2024 at 02:19:25PM -0700, Nicolin Chen wrote: > > > On Tue, Jun 18, 2024 at 05:14:32PM -0400, Michael S. Tsirkin wrote: > > > > > @@ -306,8 +314,8

Re: [PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

On Tue, Jun 18, 2024 at 05:34:21PM -0400, Michael S. Tsirkin wrote: > On Tue, Jun 18, 2024 at 02:19:25PM -0700, Nicolin Chen wrote: > > On Tue, Jun 18, 2024 at 05:14:32PM -0400, Michael S. Tsirkin wrote: > > > > @@ -306,8 +314,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, > > > > VirtMac

Re: [PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

On Tue, Jun 18, 2024 at 02:19:25PM -0700, Nicolin Chen wrote: > On Tue, Jun 18, 2024 at 05:14:32PM -0400, Michael S. Tsirkin wrote: > > > @@ -306,8 +314,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, > > > VirtMachineState *vms) > > > } > > > > > > /* Append the last RC

Re: [PATCH] hw/usb/hcd-dwc2: Handle invalid address access in read and write functions

On Tue, Jun 18, 2024 at 1:37 PM Philippe Mathieu-Daudé wrote: > Hi Paul, > > On 18/6/24 20:58, Paul Zimmerman wrote: > > On Tue, Jun 18, 2024 at 6:56 AM Zheyu Ma > > wrote: > > > > > > This commit modifies the dwc2_hsotg_read() and dwc2_hsotg_write() > > functions >

[PATCH] block/file-posix: Consider discard flag when opening

Set has_discard only when BDRV_O_UNMAP is not set. With this users that want to keep their images fully allocated can disable hole punching when writing zeros or discarding using: -drive file=thick.img,discard=off This change is not entirely correct since it changes the default discard behavio

Re: [PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

On Tue, Jun 18, 2024 at 05:14:32PM -0400, Michael S. Tsirkin wrote: > > @@ -306,8 +314,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, > > VirtMachineState *vms) > > } > > > > /* Append the last RC -> ITS ID mapping */ > > -if (next_range.input_base < 0x) { >

Re: [PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

On Tue, Jun 18, 2024 at 02:11:10PM -0700, Nicolin Chen wrote: > It's observed that Linux kernel booting with the VM reports a "conflicting > mapping for input ID" FW_BUG. > > The IORT doc defines "Number of IDs" to be "the number of IDs in the range > minus one", while virt-acpi-build.c simply sto

[PATCH v3] hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mapping

It's observed that Linux kernel booting with the VM reports a "conflicting mapping for input ID" FW_BUG. The IORT doc defines "Number of IDs" to be "the number of IDs in the range minus one", while virt-acpi-build.c simply stores the number of IDs in the id_count without the "minus one". Meanwhile

Re: [PULL v2 00/76] Misc patches for 2024-06-18

On 18/6/24 22:20, Philippe Mathieu-Daudé wrote: Per https://lore.kernel.org/qemu-devel/68014035-47e7-48b4-b11b-83b219f4e...@linaro.org/, please ignore this v2. Misc patches queue . Remove deprecated pc-i440fx-2.0 -> 2.3 machin

Re: [PATCH] hw/usb/hcd-dwc2: Handle invalid address access in read and write functions

Hi Paul, On 18/6/24 20:58, Paul Zimmerman wrote: On Tue, Jun 18, 2024 at 6:56 AM Zheyu Ma > wrote: > > This commit modifies the dwc2_hsotg_read() and dwc2_hsotg_write() functions > to handle invalid address access gracefully. Instead of using > g_assert_not_reac

Re: [PATCH] block: m25p80: Fix heap-buffer-overflow in flash_erase function

On 18/6/24 21:11, Zheyu Ma wrote: Thanks for your useful advice! So how about report the issue and return: We might report the issue to the user, but there should be a way the hardware report the issue to the guest software running. Usually signaled as error condition, irq, ... We need to figu

Re: [RFC PATCH] migration/savevm: do not schedule snapshot_save_job_bh in qemu_aio_context

On Fri, Jun 14, 2024 at 11:29:13AM +0200, Fiona Ebner wrote: > Am 12.06.24 um 17:34 schrieb Stefan Hajnoczi: > > > > Thank you for investigating! It looks like we would be trading one > > issue (the assertion failures you mentioned) for another (a rare, but > > possible, hang). > > > > I'm not su

Re: [PULL 00/76] Misc patches for 2024-06-18

; ofhttps://github.com/newfriday/qemu  into staging (2024-06-17 11:40:24 -0700) are available in the Git repository at:    https://github.com/philmd/qemu.git  tags/misc-20240618 for you to fetch changes up to 02ad1f5b04bf2941852f405c87535307365f7041:    ui+display: rename is_buffer_shared() -> surface

[PULL v2 00/76] Misc patches for 2024-06-18

u.git tags/misc-20240618 for you to fetch changes up to 9bf66ef9c7bacd410084f285fbcac6ee4189bab2: ui+display: rename is_buffer_shared() -> surface_is_allocated() (2024-06-18 22:17:15 +0200) Spurious warning (3 times): WARNING: added, moved or deleted file(s), does MAINTAINERS

[PULL v2 56/76] accel/tcg: Make TCGCPUOps::cpu_exec_halt mandatory

From: Peter Maydell Now that all targets set TCGCPUOps::cpu_exec_halt, we can make it mandatory and remove the fallback handling that calls cpu_has_work. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20240603160933.1141717-4-peter

Re: [PULL 00/76] Misc patches for 2024-06-18

4-06-17 11:40:24 -0700) are available in the Git repository at:    https://github.com/philmd/qemu.git  tags/misc-20240618 for you to fetch changes up to 02ad1f5b04bf2941852f405c87535307365f7041:    ui+display: rename is_buffer_shared() -> surface_is_allocated() (2024-06-18 17:54:40 +020

Re: [PATCH v2] hw/arm/virt-acpi-build: Fix IORT id_count

On Tue, Jun 18, 2024 at 04:03:34PM -0400, Michael S. Tsirkin wrote: > On Mon, Jun 17, 2024 at 03:39:45PM -0700, Nicolin Chen wrote: > > -next_range.input_base = idmap->input_base + idmap->id_count; > > +next_range.input_base = idmap->input_base + idmap->id_count + > > 1; >

Re: [PULL 00/76] Misc patches for 2024-06-18

in the Git repository at: https://github.com/philmd/qemu.git tags/misc-20240618 for you to fetch changes up to 02ad1f5b04bf2941852f405c87535307365f7041: ui+display: rename is_buffer_shared() -> surface_is_allocated() (2024-06-18 17:54:40 +0200) Spurious warning (3 times): WARNING: ad

Re: [PATCH v2] hw/arm/virt-acpi-build: Fix IORT id_count

On Mon, Jun 17, 2024 at 03:39:45PM -0700, Nicolin Chen wrote: > The IORT doc defines "Number of IDs" ("id_count" in the virt-acpi-build) > to be "the number of IDs in the range minus one". Otherwise, Linux kernel > reports "conflicting mapping for input ID" FW_BUG at the overlapped ID. > > Fixes:

Re: [PATCH v2] hw/arm/virt-acpi-build: Fix IORT id_count

On Tue, Jun 18, 2024 at 03:38:31PM -0400, Michael S. Tsirkin wrote: > > > > -next_range.input_base = idmap->input_base + > > > > idmap->id_count; > > > > +next_range.input_base = idmap->input_base + > > > > idmap->id_count + 1; > > > > } > > > > > > > > > > Given

Re: [PATCH v2] hw/arm/virt-acpi-build: Fix IORT id_count

On Tue, Jun 18, 2024 at 12:04:20PM -0700, Nicolin Chen wrote: > On Tue, Jun 18, 2024 at 05:49:58AM -0400, Michael S. Tsirkin wrote: > > On Mon, Jun 17, 2024 at 03:39:45PM -0700, Nicolin Chen wrote: > > > The IORT doc defines "Number of IDs" ("id_count" in the virt-acpi-build) > > > to be "the numbe

Re: [PATCH 13/18] tcg/loongarch64: Split out vdvjvk in tcg_out_vec_op

On 6/17/24 19:28, gaosong wrote: 在 2024/5/28 上午5:19, Richard Henderson 写道:   case INDEX_op_andc_vec:   /*    * vandn vd, vj, vk: vd = vk & ~vj    * andc_vec vd, vj, vk: vd = vj & ~vk - * vk and vk are swapped + * vj and vk are swapped    */ -  

Re: [PATCH] block: m25p80: Fix heap-buffer-overflow in flash_erase function

Thanks for your useful advice! So how about report the issue and return: diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 8dec134832..2121b43708 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -617,6 +617,12 @@ static void flash_erase(Flash *s, int offset, FlashCMD cmd)

Re: [PATCH v2] hw/arm/virt-acpi-build: Fix IORT id_count

On Tue, Jun 18, 2024 at 05:49:58AM -0400, Michael S. Tsirkin wrote: > On Mon, Jun 17, 2024 at 03:39:45PM -0700, Nicolin Chen wrote: > > The IORT doc defines "Number of IDs" ("id_count" in the virt-acpi-build) > > to be "the number of IDs in the range minus one". Otherwise, Linux kernel > > reports

Re: [PATCH] hw/usb/hcd-dwc2: Handle invalid address access in read and write functions

On Tue, Jun 18, 2024 at 6:56 AM Zheyu Ma wrote: > > This commit modifies the dwc2_hsotg_read() and dwc2_hsotg_write() functions > to handle invalid address access gracefully. Instead of using > g_assert_not_reached(), which causes the program to abort, the functions > now log an error message and

Re: [RFC] vhost: Introduce packed vq and add buffer elements

Hi, On Tuesday, June 18, 2024 11:48:34 PM GMT+5:30 Sahil Siddiq wrote: > [...] > > hw/virtio/vhost-shadow-virtqueue.c | 124 - > hw/virtio/vhost-shadow-virtqueue.h | 66 ++- > 2 files changed, 167 insertions(+), 23 deletions(-) > > diff --git a/hw/virtio/

[RFC] vhost: Introduce packed vq and add buffer elements

This is the first patch in a series to add support for packed virtqueues in vhost_shadow_virtqueue. This patch implements the insertion of available buffers in the descriptor area. It takes into account descriptor chains, but does not consider indirect descriptors. VhostShadowVirtqueue has also be

Re: [PATCH 5/5] pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.c

On 6/17/24 10:43 PM, Michael Kowal wrote: From: Frederic Barrat Moving xive2_nvp_pic_print_info() align with the other "pic_print_info" functions and allows us to call functions internal to xive2.c. In XIVE Gen 2 there were some minor changes to the TIMA header that were updated when printed.

Re: [PATCH 4/5] pnv/xive2: Fail VST entry address computation if table has no VSD

On 6/17/24 10:43 PM, Michael Kowal wrote: From: Frederic Barrat Fail VST entry address computatio if firmware doesn't define a descriptor computation for one of the Virtualization Structure Tables (VST), there's no point in trying to compute the address of its entry. Abort the operation an

Re: [PATCH 3/5] pnv/xive2: Set Translation Table for the NVC port space

On 6/17/24 10:43 PM, Michael Kowal wrote: From: Frederic Barrat Set Translation Table for the NVC port space is missing. The xive model doesn't take into account the remapping of IO operations via the Set Translation Table but firmware is allowed to define it for the Notify Virtual Crowd (NVC)

Re: [PATCH 2/5] pnv/xive2: Enable VST NVG and NVC index compression

On 6/17/24 10:42 PM, Michael Kowal wrote: From: Frederic Barrat Enable NVG and NVC VST tables for index compression which indicates the number of bits the address is shifted to the right for the table accesses. The compression values are defined as: - No compression 0001 - 1 bit sh

Re: [PATCH 1/5] pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection support

Hello Michael, On 6/17/24 10:42 PM, Michael Kowal wrote: From: Frederic Barrat XIVE offers a 'cache watch facility', which allows software to read/update a potentially cached table entry with no software lock. There's one such facility in the Virtualization Controller (VC) to update the ESB an

Re: [PATCH v3 2/4] target/ppc: Move VSX vector with length storage access insns to decodetree.

On 6/18/24 01:58, Chinmay Rath wrote: Moving the following instructions to decodetree specification : {l, st}xvl(l) : X-form The changes were verified by validating that the tcg-ops generated by those instructions remain the same, which were captured using the '-d in_asm,op'

[PATCH] hw/net: Fix Coverity Issue for npcm-gmac

There is an extra `buf=` set that is not used by npcm-gmac. Remove it for coverity to be happy. Signed-off-by: Nabih Estefan --- hw/net/npcm_gmac.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index 1b71e2526e..b397fd5064 100644 --- a/hw/net/npcm_gma

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