Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

Am 13.06.24 um 19:07 schrieb Thomas Huth: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Thus add a CONFIG switch that can be used to disable these CPUs (and old machine types that use

Re: [PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

Mao On 2024/6/14 上午1:30, Jiaxun Yang wrote: Hi all, This series implemented S3 and S4 sleep for loongarch virt machine and microvm. For loongarch/virt a kernel patch is requried [1]. [1]: https://lore.kernel.org/loongarch/20240613-loongarch64-sleep-v1-0-a245232af...@flygoat.com/ Please

Re: [PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

> > Regards > Bibo Mao > > > On 2024/6/14 上午1:30, Jiaxun Yang wrote: >> Hi all, >> >> This series implemented S3 and S4 sleep for loongarch virt machine >> and microvm. >> >> For loongarch/virt a kernel patch is requried [1]. >> >&

Re: [PULL 00/15] CPU-related test updates

On 6/12/24 06:20, Thomas Huth wrote: The following changes since commit 80e8f0602168f451a93e71cbb1d59e93d745e62e: Merge tag 'bsd-user-misc-2024q2-pull-request' of gitlab.com:bsdimp/qemu into staging (2024-06-09 11:21:55 -0700) are available in the Git repository at: https://gitlab.com/t

Re: [PULL 0/5] virtio-grants-v8-tag

On 6/12/24 14:29, Stefano Stabellini wrote: The following changes since commit 80e8f0602168f451a93e71cbb1d59e93d745e62e: Merge tag 'virtio-grants-v8-tag' into staging (2024-06-09 11:21:55 -0700) are available in the Git repository at: https://gitlab.com/sstabellini/qemu.git for you t

Re: [PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

microvm. For loongarch/virt a kernel patch is requried [1]. [1]: https://lore.kernel.org/loongarch/20240613-loongarch64-sleep-v1-0-a245232af...@flygoat.com/ Please review. Thanks Signed-off-by: Jiaxun Yang --- Jiaxun Yang (3): acpi/ged: Implement S3 and S4 sleep hw/loongarch/virt

RE: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions

>-Original Message- >From: Eric Auger >Subject: Re: [PATCH v3 4/7] virtio-iommu: Compute host reserved regions > > > >On 6/13/24 12:00, Duan, Zhenzhong wrote: >> Hi Eric, >> >>> -Original Message- >>> From: Eric Auger >>> Subject: [PATCH v3 4/7] virtio-iommu: Compute host reserv

RE: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for tdx-guest object

>-Original Message- >From: Li, Xiaoyao >Subject: Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for >tdx-guest object > >On 6/13/2024 4:35 PM, Duan, Zhenzhong wrote: >> >> >>> -Original Message- >>> From: Li, Xiaoyao >>> Subject: Re: [PATCH v5 25/65] i386/tdx: Add p

[RFC PATCH v3] target/loongarch/kvm: Implement LoongArch PMU extension.

Implement PMU extension for LoongArch kvm mode. Use OnOffAuto type variable pmu to check the PMU feature. If the PMU Feature is not supported with KVM host, it reports error if there is pmu=on command line. If there is no any command line about pmu parameter, it checks whether KVM host supports th

Re: [PATCH v7 3/3] hw/nvme: Add SPDM over DOE support

On Fri, 2024-06-14 at 11:28 +1000, Alistair Francis wrote: > From: Wilfred Mallawa > > Setup Data Object Exchance (DOE) as an extended capability for the > NVME small typo here 🤓️ [s/Setup Data Object Exchance/Setup Data Object Exchange] Wilfred > controller and connect SPDM to it (CMA) to it. >

Re: [PATCH v7 1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0

Reviewed-by: Wilfred Mallawa On Fri, 2024-06-14 at 11:28 +1000, Alistair Francis wrote: > Add all of the defined protocols/features from the PCIe-SIG r6.0 > "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)" > table. > > Signed-off-by: Alistair Francis > Reviewed-by: Jonathan Ca

Re: [PATCH v7 1/2] hw/misc/riscv_iopmp: Add RISC-V IOPMP device

On Thu, Jun 13, 2024 at 05:26:03PM +0800, LIU Zhiwei wrote: > > Hi Ethan, > > On 2024/6/12 11:17, Ethan Chen wrote: > > Support basic functions of IOPMP specification v0.9.1 rapid-k model. > > The specification url: > > https://github.com/riscv-non-isa/iopmp-spec/releases/tag/v0.9.1 > > > > IOPM

[PATCH v7 2/3] backends: Initial support for SPDM socket support

From: Huai-Cheng Kuo SPDM enables authentication, attestation and key exchange to assist in providing infrastructure security enablement. It's a standard published by the DMTF [1]. SPDM supports multiple transports, including PCIe DOE and MCTP. This patch adds support to QEMU to connect to an ex

[PATCH v7 1/3] hw/pci: Add all Data Object Types defined in PCIe r6.0

Add all of the defined protocols/features from the PCIe-SIG r6.0 "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)" table. Signed-off-by: Alistair Francis Reviewed-by: Jonathan Cameron --- include/hw/pci/pcie_doe.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw

[PATCH v7 0/3] Initial support for SPDM Responders

The Security Protocol and Data Model (SPDM) Specification defines messages, data objects, and sequences for performing message exchanges over a variety of transport and physical media. - https://www.dmtf.org/sites/default/files/standards/documents/DSP0274_1.3.0.pdf SPDM currently supports PCIe D

[PATCH v7 3/3] hw/nvme: Add SPDM over DOE support

From: Wilfred Mallawa Setup Data Object Exchance (DOE) as an extended capability for the NVME controller and connect SPDM to it (CMA) to it. Signed-off-by: Wilfred Mallawa Signed-off-by: Alistair Francis Reviewed-by: Jonathan Cameron Acked-by: Klaus Jensen --- docs/specs/index.rst|

Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for tdx-guest object

On 6/13/2024 4:35 PM, Duan, Zhenzhong wrote: -Original Message- From: Li, Xiaoyao Subject: Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for tdx-guest object On 6/6/2024 6:45 PM, Daniel P. Berrangé wrote: Copying Zhenzhong Duan as my point relates to the proposed libv

Re: [PATCH v5 17/65] i386/tdx: Adjust the supported CPUID based on TDX restrictions

On 6/13/2024 4:26 PM, Duan, Zhenzhong wrote: + * + * It also has side effect to enable unsupported bits, e.g., the + * bits of "fixed0" type while present natively. It's safe because + * the unsupported bits will be masked off by .fixed0 later. + */ +    *ret |= host_cpuid_reg

[PATCH RFC V3 29/29] hw/arm/virt: Expose cold-booted CPUs as MADT GICC Enabled

Hotpluggable CPUs MUST be exposed as 'online-capable' according to the new change. However, cold-booted CPUs, if marked as 'online-capable' during boot time, might not be detected by legacy operating systems. This could cause compatibility problems. Original Change Link: https://bugzilla.tianocore

[PATCH RFC V3 28/29] tcg/mttcg: enable threads to unregister in tcg_ctxs[]

From: Miguel Luis [BROKEN: This patch is just for reference. It has problems as it does not takes care of the TranslationBlocks and their assigned regions during CPU unrealize] When using TCG acceleration in a multi-threaded context each vCPU has its own thread registered in tcg_ctxs[] upon crea

[PATCH RFC V3 27/29] hw/arm: Support hotplug capability check using _OSC method

Physical CPU hotplug results in (un)setting of ACPI _STA.Present bit. AARCH64 platforms do not support physical CPU hotplug. Virtual CPU hotplug support being implemented toggles ACPI _STA.Enabled Bit to achieve hotplug functionality. This is not same as physical CPU hotplug support. In future, if

[PATCH RFC V3 26/29] target/arm/kvm, tcg: Register/Handle SMCCC hypercall exits to VMM/Qemu

From: Author Salil Mehta Add registration and Handling of HVC/SMC hypercall exits to VMM Co-developed-by: Jean-Philippe Brucker Signed-off-by: Jean-Philippe Brucker Signed-off-by: Salil Mehta --- target/arm/arm-powerctl.c | 51 target/arm/helper.c | 2 +- targ

[PATCH] hw/arm/virt-acpi-build: Fix IORT id_count

The IORT doc defines "Number of IDs" ("id_count" in the virt-acpi-build) to be "the number of IDs in the range minus one". Otherwise, Linux kernel reports "conflicting mapping for input ID" FW_BUG at the overlapped ID. Fixes: 42e0f050e3a5 ("hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv

[PATCH RFC V3 25/29] target/arm/kvm: Write CPU state back to KVM on reset

From: Jean-Philippe Brucker When a KVM vCPU is reset following a PSCI CPU_ON call, its power state is not synchronized with KVM at the moment. Because the vCPU is not marked dirty, we miss the call to kvm_arch_put_registers() that writes to KVM's MP_STATE. Force mp_state synchronization. Signed-

[PATCH RFC V3 24/29] target/arm: Add support of *unrealize* ARMCPU during vCPU Hot-unplug

vCPU Hot-unplug will result in QOM CPU object unrealization which will do away with all the vCPU thread creations, allocations, registrations that happened as part of the realization process. This change introduces the ARM CPU unrealize function taking care of exactly that. Note, initialized KVM v

[PATCH RFC V3 23/29] hw/arm: Changes required for reset and to support next boot

Updates the firmware config with the next boot cpus information and also registers the reset callback to be called when guest reboots to reset the cpu. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/boot.c | 2 +- hw/arm/virt.c | 17

[PATCH RFC V3 21/29] hw/intc/arm-gicv3*: Changes required to (re)init the vCPU register info

vCPU register info needs to be re-initialized each time vCPU is hot-plugged. This has to be done both for emulation/TCG and KVM case. This is done in context to the GIC update notification for any vCPU hot-(un)plug events. This change adds that support and re-factors existing to maximize the code r

[PATCH RFC V3 22/29] arm/virt: Update the guest(via GED) about CPU hot-(un)plug events

During any vCPU hot-(un)plug, running guest VM needs to be intimated about the new vCPU being added or request the deletion of the vCPU which is already part of the guest VM. This is done using the ACPI GED event which eventually gets demultiplexed to a CPU hotplug event and further to specific hot

[PATCH RFC V3 20/29] hw/arm, gicv3: Changes to update GIC with vCPU hot-plug notification

Virtual CPU hot-(un)plug events MUST be notified to the GIC. Introduce a notfication mechanism to update any such events to GIC so that it can update its vCPU to GIC CPU interface association. This is required to implement a workaround to the limitations posed by the ARM architecture. For details

[PATCH RFC V3 19/29] arm/virt: Changes to (un)wire GICC<->vCPU IRQs during hot-(un)plug

Refactors the existing GIC create code to extract common code to wire the vcpu<->gic interrupts. This function could be used with cold-plug case and also used when vCPU is hot-plugged. It also introduces a new function to unwire the vcpu<->gic interrupts for the vCPU hot-unplug cases. Co-developed

[PATCH RFC V3 18/29] arm/virt: Add/update basic hot-(un)plug framework

Add CPU hot-unplug hooks and update hotplug hooks with additional sanity checks for use in hotplug paths. Note: The functional contents of the hooks (currently left with TODO comments) will be gradually filled in subsequent patches in an incremental approach to patch and logic building, which woul

[PATCH RFC V3 17/29] arm/virt: Release objects for *disabled* possible vCPUs after init

During `machvirt_init()`, QOM ARMCPU objects are pre-created along with the corresponding KVM vCPUs in the host for all possible vCPUs. This is necessary due to the architectural constraint that KVM restricts the deferred creation of KVM vCPUs and VGIC initialization/sizing after VM initialization.

[PATCH RFC V3 16/29] hw/acpi: Make _MAT method optional

From: Jean-Philippe Brucker The GICC interface on arm64 vCPUs is statically defined in the MADT, and doesn't require a _MAT entry. Although the GICC is indicated as present by the MADT entry, it can only be used from vCPU sysregs, which aren't accessible until hot-add. Co-developed-by: Jean-Phil

[PATCH RFC V3 15/29] hw/arm: MADT Tbl change to size the guest with possible vCPUs

Changes are required during the building of the MADT table by QEMU to accommodate disabled possible vCPUs. This information will be used by the guest kernel to size up its resources during boot time. The pre-sizing of the guest kernel based on possible vCPUs will facilitate the hotplug of the disab

[PATCH RFC V3 14/29] hw/acpi: ACPI/AML Changes to reflect the correct _STA.{PRES, ENA} Bits to Guest

ACPI AML changes are required to properly reflect the `_STA.PRES` and `_STA.ENA` bits to the guest during initialization, when CPUs are hot-plugged, and after CPUs are hot-unplugged. Signed-off-by: Salil Mehta --- hw/acpi/cpu.c | 53 ++ hw/acpi/ge

[PATCH RFC V3 13/29] arm/virt: Make ARM vCPU *present* status ACPI *persistent*

ARM arch does not allow CPUs presence to be changed [1] after kernel has booted. Hence, firmware/ACPI/Qemu must ensure persistent view of the vCPUs to the Guest kernel even when they are not present in the QoM i.e. are unplugged or are yet-to-be-plugged References: [1] Check comment 5 in the bugzi

[PATCH RFC V3 12/29] arm/virt/acpi: Build CPUs AML with CPU Hotplug support

Support for Virtual CPU Hotplug requires a sequence of ACPI handshakes between QEMU and the guest kernel when a vCPU is plugged or unplugged. Most of the AML code to support these handshakes already exists. This AML needs to be built during VM initialization for the ARM architecture as well, if GED

[PATCH RFC V3 11/29] arm/virt: Create GED dev before *disabled* CPU Objs are destroyed

ACPI CPU hotplug state (is_present=_STA.PRESENT, is_enabled=_STA.ENABLED) for all the possible vCPUs MUST be initialized during machine init. This is done during the creation of the GED device. VMM/Qemu MUST expose/fake the ACPI state of the disabled vCPUs to the Guest kernel as 'present' (_STA.PRE

[PATCH RFC V3 10/29] arm/virt: Add cpu hotplug events to GED during creation

Add the CPU Hotplug event to the set of supported GED events during the creation of the GED device at VM initialization. Additionally, initialize the memory map for the CPU Hotplug control device, which is used for event exchanges between QEMU/VMM and the guest. Signed-off-by: Salil Mehta Reviewe

[PATCH RFC V3 09/29] arm/acpi: Enable ACPI support for vcpu hotplug

ACPI is required to interface QEMU with the guest. Roughly falls into below cases, 1. Convey the possible vcpus config at the machine init time to the guest using various DSDT tables like MADT etc. 2. Convey vcpu hotplug events to guest(using GED) 3. Assist in evaluation of various ACPI methods

[PATCH RFC V3 08/29] arm/virt: Init PMU at host for all possible vcpus

PMU for all possible vCPUs must be initialized at the VM initialization time. Refactor existing code to accomodate possible vCPUs. This also assumes that all processor being used are identical. Past discussion for reference: Link: https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00131.html

[PATCH RFC V3 07/29] arm/virt, gicv3: Changes to pre-size GIC with possible vcpus @machine init

The GIC needs to be pre-sized with possible vCPUs at initialization time. This is necessary because memory regions and resources associated with GICC/GICR, etc., cannot be changed (added, deleted, or modified) after the VM has been initialized. Additionally, `GIC_TYPER` needs to be initialized with

[PATCH RFC V3 06/29] arm/virt, kvm: Pre-create disabled possible vCPUs @machine init

In the ARMv8 architecture, the GIC must know all the CPUs it is connected to during its initialization, and this cannot change afterward. This must be ensured during the initialization of the VGIC as well in KVM, which requires all vCPUs to be created and present during its initialization. This is

[PATCH RFC V3 05/29] arm/virt, target/arm: Machine init time change common to vCPU {cold|hot}-plug

Introduce the common logic required during the initialization of both cold and hot-plugged vCPUs. Additionally, initialize the *disabled* state of the vCPUs, which will be used further during the initialization phases of various other components like GIC, PMU, ACPI, etc., as part of the virtual mac

[PATCH RFC V3 04/29] hw/arm/virt: Move setting of common CPU properties in a function

Factor out CPU properties code common for {hot,cold}-plugged CPUs. This allows code reuse. Signed-off-by: Salil Mehta --- hw/arm/virt.c | 261 -- include/hw/arm/virt.h | 4 + 2 files changed, 182 insertions(+), 83 deletions(-) diff --git a/hw/ar

[PATCH RFC V3 02/29] cpu-common: Add common CPU utility for possible vCPUs

This patch adds various utility functions that may be required to fetch or check the state of possible vCPUs. It also introduces the concept of *disabled* vCPUs, which are part of the *possible* vCPUs but are not enabled. This state will be used during machine initialization and later during the pl

[PATCH RFC V3 03/29] hw/arm/virt: Limit number of possible vCPUs for unsupported Accel or GIC Type

If Virtual CPU Hotplug support does not exist on a particular Accel platform or ARM GIC version, we should limit the possible vCPUs to those available during boot time (i.e SMP CPUs) and explicitly disable Virtual CPU Hotplug support. Signed-off-by: Salil Mehta --- hw/arm/virt.c | 66 +++

[PATCH RFC V3 00/29] Support of Virtual CPU Hotplug for ARMv8 Arch

PROLOGUE To assist in review and set the right expectations from this RFC, please first read the sections *APPENDED AT THE END* of this cover letter: 1. Important *DISCLAIMER* [Section (X)] 2. Work presented at KVMForum Conference (slides available) [Section (V)F] 3. Organization of patc

[PATCH RFC V3 01/29] arm/virt, target/arm: Add new ARMCPU {socket, cluster, core, thread}-id property

This shall be used to store user specified topology{socket,cluster,core,thread} and shall be converted to a unique 'vcpu-id' which is used as slot-index during hot(un)plug of vCPU. Co-developed-by: Keqian Zhu Signed-off-by: Keqian Zhu Signed-off-by: Salil Mehta --- hw/arm/virt.c | 10 +

Re: [PATCH v2] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

On 6/13/2024 1:22 PM, Taylor Simpson wrote: hexagon-core.xml only exposes register p3_0 which is an alias that aggregates the predicate registers. It is more convenient for users to interact directly with the predicate registers. Tested with lldb downloaded from this location https://github.c

[PATCH v2 2/9] gdbstub: Move GdbCmdParseEntry into a new header file

Move GdbCmdParseEntry and its associated types into a separate header file to allow the use of GdbCmdParseEntry and other gdbstub command functions outside of gdbstub.c. Since GdbCmdParseEntry and get_param are now public, kdoc GdbCmdParseEntry and rename get_param to gdb_get_cmd_param. This comm

[RFC PATCH v4 4/5] target/riscv: rvv: Provide group continuous ld/st flow for unit-stride ld/st instructions

The vector unmasked unit-stride and whole register load/store instructions will load/store continuous memory. If the endian of both the host and guest architecture are the same, then we can group the element load/store to load/store more data at a time. Signed-off-by: Max Chou --- target/riscv/v

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

On 13/06/2024 19.17, Philippe Mathieu-Daudé wrote: Hi Thomas, On 13/6/24 19:07, Thomas Huth wrote: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Thus add a CONFIG switch that can be use

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Thu, Jun 13, 2024 at 11:16 AM Daniel P. Berrangé wrote: > I guess there's a balance to be had somewhere on the spectrum between doing > everything against the raw C binding, vs everything against a perfectly > idiomatic Rust API wrapping the C bniding. The latter might be the ideal, > but from

Re: [PATCH 4/4] migration/postcopy: Add postcopy-recover-setup phase

Peter Xu writes: > On Thu, Jun 13, 2024 at 11:51:58AM -0300, Fabiano Rosas wrote: >> Peter Xu writes: >> >> > This patch adds a migration state on src called "postcopy-recover-setup". >> > The new state will describe the intermediate step starting from when the >> > src QEMU started an postcopy

[RFC PATCH v4 1/5] accel/tcg: Avoid unnecessary call overhead from qemu_plugin_vcpu_mem_cb

If there are not any QEMU plugin memory callback functions, checking before calling the qemu_plugin_vcpu_mem_cb function can reduce the function call overhead. Signed-off-by: Max Chou --- accel/tcg/ldst_common.c.inc | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/acce

Re: [PATCH v2 6/9] target/arm: Factor out code for setting MTE TCF0 field

On 13/6/24 19:21, Gustavo Romero wrote: Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this

Re: [PATCH v2 5/9] target/arm: Make some MTE helpers widely available

Hi Gustavo, On 13/6/24 19:20, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems by moving them from mte_helper.c to a new header file, mte_helper.h. Signed-off-by: Gustavo Romero --- target/arm/tcg/mte_helper.c | 184

Re: [PATCH v2 6/9] target/arm: Factor out code for setting MTE TCF0 field

Hi Phil, On 6/13/24 2:35 PM, Philippe Mathieu-Daudé wrote: On 13/6/24 19:21, Gustavo Romero wrote: Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate fun

[RFC PATCH v4 2/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unmasked unit-stride load/store

This commit references the sve_ldN_r/sve_stN_r helper functions in ARM target to optimize the vector unmasked unit-stride load/store instructions by following items: * Get the loose bound of activate elements * Probing pages/resolving host memory address/handling watchpoint at beginning * Provide

Re: [PATCH 4/4] migration/postcopy: Add postcopy-recover-setup phase

On Thu, Jun 13, 2024 at 02:21:04PM -0300, Fabiano Rosas wrote: > >> > @@ -3666,7 +3716,7 @@ void migrate_fd_connect(MigrationState *s, Error > >> > *error_in) > >> > { > >> > Error *local_err = NULL; > >> > uint64_t rate_limit; > >> > -bool resume = s->state == MIGRATION_STATUS_POST

[RFC PATCH v4 5/5] target/riscv: Inline unit-stride ld/st and corresponding functions for performance

In the vector unit-stride load/store helper functions. the vext_ldst_us & vext_ldst_whole functions corresponding most of the execution time. Inline the functions can avoid the function call overhead to improve the helper function performance. Signed-off-by: Max Chou --- target/riscv/vector_help

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

On 13/6/24 19:22, Thomas Huth wrote: On 13/06/2024 19.17, Philippe Mathieu-Daudé wrote: Hi Thomas, On 13/6/24 19:07, Thomas Huth wrote: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Th

[PATCH v2 22/22] qga: centralize logic for disabling/enabling commands

It is confusing having many different pieces of code enabling and disabling commands, and it is not clear that they all have the same semantics, especially wrt prioritization of the block/allow lists. The code attempted to prevent the user from setting both the block and allow lists concurrently, h

Re: [PATCH] ui/gtk: Wait until the current guest frame is rendered before switching to RUN_STATE_SAVE_VM

Hi Marc-André, On 6/13/2024 6:16 AM, Marc-André Lureau wrote: Hi On Wed, Jun 12, 2024 at 10:50 PM Kim, Dongwon > wrote: On 6/11/2024 10:44 PM, Marc-André Lureau wrote: > Hi > > On Wed, Jun 12, 2024 at 5:29 AM Kim, Dongwon mailto:dongwon

[RFC PATCH v4 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

Hi, Sorry for the quick update the version, this version fixes the cross-page probe checking bug that I forgot to apply to the v3 version. This RFC patch set tries to fix the issue of https://gitlab.com/qemu-project/qemu/-/issues/2137. In this RFC, we added patches that 1. Provide a fast path to

[PATCH v2 20/22] qga: remove pointless 'blockrpcs_key' variable

This variable was used to support back compat for the old config file key name, and became redundant after the following change: commit a7a2d636ae4549ef0551134d4bf8e084a14431c4 Author: Philippe Mathieu-Daudé Date: Thu May 30 08:36:43 2024 +0200 qga: Remove deprecated 'blacklist' argu

[PATCH v2 0/9] Add MTE stubs for aarch64 user mode

This patchset adds the stubs necessary to support GDB memory tagging commands on QEMU aarch64 user mode. These new stubs handle the qIsAddressTagged, qMemTag, and QMemTag packets, which allow GDB memory tagging subcommands 'check', 'print-allocation-tag', and 'set-allocation-tag' to work. The rema

[PATCH v2 3/9] gdbstub: Add support for target-specific stubs

Currently, it's not possible to have stubs specific to a given target, even though there are GDB features which are target-specific, like, for instance, memory tagging. This commit introduces gdb_extend_qsupported_features, gdb_extend_query_table, and gdb_extend_set_table functions as interfaces t

[PATCH v2] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

hexagon-core.xml only exposes register p3_0 which is an alias that aggregates the predicate registers. It is more convenient for users to interact directly with the predicate registers. Tested with lldb downloaded from this location https://github.com/llvm/llvm-project/releases/download/llvmorg-1

Re: [PATCH v2 5/9] target/arm: Make some MTE helpers widely available

Hi Phil! On 6/13/24 2:32 PM, Philippe Mathieu-Daudé wrote: Hi Gustavo, On 13/6/24 19:20, Gustavo Romero wrote: Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems by moving them from mte_helper.c to a new header file, mte_helper.h. Signed-off

[PATCH v2 5/9] target/arm: Make some MTE helpers widely available

Make the MTE helpers allocation_tag_mem_probe, load_tag1, and store_tag1 available to other subsystems by moving them from mte_helper.c to a new header file, mte_helper.h. Signed-off-by: Gustavo Romero --- target/arm/tcg/mte_helper.c | 184 +-- target/arm/tcg/mte_help

RE: [PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

> -Original Message- > From: Ted Woodward > Sent: Thursday, June 13, 2024 9:03 AM > To: ltaylorsimp...@gmail.com; Matheus Bernardino (QUIC) > > Cc: qemu-devel@nongnu.org; Brian Cain ; > alex.ben...@linaro.org; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...

[PATCH v2 08/22] qga: conditionalize schema for commands unsupported on Windows

Rather than creating stubs for every command that just return QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to fully exclude generation of the commands on Windows. The command will be rejected at QMP dispatch time instead, avoiding reimplementing rejection by blocking the stub commands.

[PATCH v2 15/22] qga: conditionalize schema for commands requiring libudev

Rather than creating stubs for every command that just return QERR_UNSUPPORTED, use 'if' conditions in the schema to fully exclude generation of the filesystem trimming commands on POSIX platforms lacking required APIs. The command will be rejected at QMP dispatch time instead, avoiding reimplemen

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

On Thu, Jun 13, 2024 at 6:06 PM Zhao Liu wrote: > I think deeper and higher level bindings will have more opens and will > likely require more discussion and exploration. So could we explore this > direction on another reference Rust device? > > I also think there won’t be too many Rust devices in

[RFC PATCH v4 3/5] target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride whole register load/store

The vector unit-stride whole register load/store instructions are similar to unmasked unit-stride load/store instructions that is suitable to be optimized by using a direct access to host ram fast path. Signed-off-by: Max Chou --- target/riscv/vector_helper.c | 185 +-

Re: [PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

Hi Thomas, On 13/6/24 19:07, Thomas Huth wrote: Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Thus add a CONFIG switch that can be used to disable these CPUs (and old machine types that

Re: [PATCH v5 5/5] iotests: Add `vvfat` tests

Am 13.06.2024 um 16:07 hat Amjad Alsharafi geschrieben: > On Wed, Jun 12, 2024 at 08:43:26PM +0800, Amjad Alsharafi wrote: > > Added several tests to verify the implementation of the vvfat driver. > > > > We needed a way to interact with it, so created a basic `fat16.py` driver > > that handled wr

Re: [PATCH 1/4] migration/multifd: Avoid the final FLUSH in complete()

On Thu, Jun 13, 2024 at 11:54:58AM -0300, Fabiano Rosas wrote: > Fabiano Rosas writes: > > > Peter Xu writes: > > > >> We always do the flush when finishing one round of scan, and during > >> complete() phase we should scan one more round making sure no dirty page > >> existed. In that case we

[PATCH 1/3] acpi/ged: Implement S3 and S4 sleep

Implement S3 and S4 sleep with ACPI_GED_REG_SLEEP_CTL.SLP_TYP writes. Implement wakeup callback and WAK_STS register to inform guest about current states. All new functions are gated by "slp-typs" property, it is defaulted to S5 only and machines can opt-in for S3 and S4. Signed-off-by: Jiaxun Y

[PATCH 2/3] hw/loongarch/virt: Wire up S3 and S4 sleep

Wire up S3 and S4 sleep by setting relevant slp-typs bits for GED and generate _S3 and _S4 methods in acpi table. Signed-off-by: Jiaxun Yang --- hw/loongarch/acpi-build.c | 18 ++ hw/loongarch/virt.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/hw/loongarch/acp

[PATCH 0/3] S3 and S4 sleep for loongarch/virt & microvm

Hi all, This series implemented S3 and S4 sleep for loongarch virt machine and microvm. For loongarch/virt a kernel patch is requried [1]. [1]: https://lore.kernel.org/loongarch/20240613-loongarch64-sleep-v1-0-a245232af...@flygoat.com/ Please review. Thanks Signed-off-by: Jiaxun Yang

[PATCH 3/3] hw/i386/microvm: Wire up S3 and S4 sleep

Wire up S3 and S4 sleep by setting relevant slp-typs bits for GED and generate _S3 and _S4 methods in acpi table. Signed-off-by: Jiaxun Yang --- hw/i386/acpi-microvm.c | 18 ++ hw/i386/microvm.c | 3 +++ 2 files changed, 21 insertions(+) diff --git a/hw/i386/acpi-microvm.c

Re: [RFC PATCH v2 3/5] rust: add PL011 device model

Hi Paolo, On Thu, Jun 13, 2024 at 09:56:39AM +0200, Paolo Bonzini wrote: > Date: Thu, 13 Jun 2024 09:56:39 +0200 > From: Paolo Bonzini > Subject: Re: [RFC PATCH v2 3/5] rust: add PL011 device model > > Il gio 13 giu 2024, 09:13 Daniel P. Berrangé ha > scritto: > > > On Wed, Jun 12, 2024 at 11:

Re: [PATCH] tests/qtest/fuzz/virtio_net_fuzz.c: fix virtio_net_fuzz_multi

On 13/06/2024 13.59, Дмитрий Фролов wrote: On 13.06.2024 13:08, Thomas Huth wrote: On 23/05/2024 12.28, Dmitry Frolov wrote: If QTestState was already CLOSED due to error, calling qtest_clock_step() afterwards makes no sense and only raises false-crash with message: "assertion timer != NULL f

[PATCH v2 7/9] gdbstub: Make get cpu and hex conversion functions non-internal

Make the gdb_first_attached_cpu and gdb_hextomem non-internal so they are not confined to use only in gdbstub.c. Signed-off-by: Gustavo Romero --- gdbstub/internals.h| 2 -- include/exec/gdbstub.h | 5 + include/gdbstub/commands.h | 6 ++ 3 files changed, 11 insertions(+), 2

[PATCH v2 6/9] target/arm: Factor out code for setting MTE TCF0 field

Factor out the code used for setting the MTE TCF0 field from the prctl code into a convenient function. Other subsystems, like gdbstub, need to set this field as well, so keep it as a separate function to avoid duplication and ensure consistency in how this field is set across the board. Signed-of

[PATCH v2 1/9] gdbstub: Clean up process_string_cmd

Change 'process_string_cmd' to return true on success and false on failure, instead of 0 and -1. Signed-off-by: Gustavo Romero --- gdbstub/gdbstub.c | 40 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.

[PATCH v2 9/9] tests/tcg/aarch64: Add MTE gdbstub tests

Add tests to exercise the MTE stubs. Signed-off-by: Gustavo Romero --- tests/tcg/aarch64/Makefile.target | 11 ++- tests/tcg/aarch64/gdbstub/test-mte.py | 86 ++ tests/tcg/aarch64/mte-8.c | 102 ++ 3 files changed, 197 insertions(+),

[PATCH v2 4/9] target/arm: Fix exception case in allocation_tag_mem_probe

If page in 'ptr_access' is inaccessible and probe is 'true' allocation_tag_mem_probe should not throw an exception, but currently it does, so fix it. Signed-off-by: Gustavo Romero --- target/arm/tcg/mte_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/arm/tcg/mte_helper.c b

[PATCH v2 8/9] gdbstub: Add support for MTE in user mode

This commit implements the stubs to handle the qIsAddressTagged, qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' subcommands to work with QEMU gdbstub on aarch64 user mode. It also implements the get/set functions for the special GDB MTE register 'tag_ctl', used to control the MTE f

Re: [PATCH 3/4] migration: Use MigrationStatus instead of int

Peter Xu writes: > On Wed, Jun 12, 2024 at 10:42:27AM -0400, Peter Xu wrote: >> @@ -1544,7 +1545,7 @@ bool migration_in_postcopy(void) >> } >> } >> >> -bool migration_postcopy_is_alive(int state) >> +bool migration_postcopy_is_alive(MigrationStatus state) >> { >> switch (state) { >>

[PATCH v2 16/22] qga: conditionalize schema for commands requiring utmpx

Rather than creating stubs for every command that just return QERR_UNSUPPORTED, use 'if' conditions in the QAPI schema to fully exclude generation of the get-users command on POSIX platforms lacking required APIs. The command will be rejected at QMP dispatch time instead, avoiding reimplementing r

Re: [PATCH] tests/qtest/fuzz/virtio_net_fuzz.c: fix virtio_net_fuzz_multi

This fixes the almost-immediate timeout issue for me on the virtio_net_fuzz target, but I'm not sure why this works or if it is fixing the right problem: qtest_probe_child is designed to run from a libqtest process which uses waitpid on the PID of the child (qemu) process (stored in QTestState->qe

Re: [RFC PATCH v2 0/2] ui/gtk: Introduce new param - Connectors

Hi Marc-André, On 6/12/2024 11:56 PM, Marc-André Lureau wrote: Hi On Thu, Jun 13, 2024 at 3:34 AM Kim, Dongwon > wrote: On 6/11/2024 11:42 PM, Marc-André Lureau wrote: > Hi > > On Tue, Jun 11, 2024 at 10:28 PM Kim, Dongwon mailto:dongwon...

[PATCH] target/s390x: Add a CONFIG switch to disable legacy CPUs

Old CPU models are not officially supported anymore by IBM, and for downstream builds of QEMU, we would like to be able to disable these CPUs in the build. Thus add a CONFIG switch that can be used to disable these CPUs (and old machine types that use them by default). Signed-off-by: Thomas Huth

Re: [PATCH 0/4] migration: New postcopy state, and some cleanups

On Wed, Jun 12, 2024 at 10:42:24AM -0400, Peter Xu wrote: > The major goal of this patchset is patch 4, which introduced a new postcopy > state so that we will send an event in postcopy reconnect failures that > Libvirt would prefer to have. There's more information for that issue in > the commit

Re: [RFC PATCH v3 0/5] Improve the performance of RISC-V vector unit-stride/whole register ld/st instructions

Richard, On 6/13/24 11:19 AM, Max Chou wrote: Hi, This RFC patch set tries to fix the issue of https://gitlab.com/qemu-project/qemu/-/issues/2137. To avoid confusion on what we're doing here: this series is another optimization effort that Max is doing for RISC-V vector. We're also working in

Re: [PATCH 8/9] plugins: add time control API

Philippe Mathieu-Daudé writes: > On 12/6/24 17:35, Alex Bennée wrote: >> Expose the ability to control time through the plugin API. Only one >> plugin can control time so it has to request control when loaded. >> There are probably more corner cases to catch here. >> From: Alex Bennée > > Some o

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