Hi
On Sun, Mar 24, 2024 at 7:23 PM Irina Ryapolova
wrote:
>
> After exit Qemu need to return the terminal to the default state.
>
> Signed-off-by: Irina Ryapolova
> ---
> chardev/char-win-stdio.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/chardev/char-win-stdio.c b/chardev/ch
On 3/25/24 10:06, Yao Xingtao wrote:
1. The g_pattern_match_string() is deprecated when glib2 version >= 2.70.
Use g_pattern_spec_match_string() instead to avoid this problem.
2. The type of second parameter in g_ptr_array_add() is
'gpointer' {aka 'void *'}, but the type of reg->name is
Richard Henderson writes:
> On 3/24/24 08:41, Sven Schnelle wrote:
>> 7f09e0: val=000fffb0301f r2=110e0f01 r1=01fff600
>> phys=fffb 4K aid=1 pl1=0, pl2=0 type=1 (DATA RW)
>> 'val' is the value constructed from IOR/ISR,
>
> Is this byte swapped in some weird way?
Hi!
On 24/03/2024 17.55, Arnaud Minier wrote:
Test:
- read/write from/to the usart registers
- send/receive a character/string over the serial port
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build| 3 +-
tests/qtest/stm32l4x5_usart-test.c |
On Sat, Mar 23, 2024 at 5:14 AM Si-Wei Liu wrote:
>
>
>
> On 3/21/2024 10:08 PM, Jason Wang wrote:
> > On Fri, Mar 22, 2024 at 5:43 AM Si-Wei Liu wrote:
> >>
> >>
> >> On 3/20/2024 8:56 PM, Jason Wang wrote:
> >>> On Thu, Mar 21, 2024 at 5:03 AM Si-Wei Liu wrote:
>
> On 3/19/2024 8:27
1. The g_pattern_match_string() is deprecated when glib2 version >= 2.70.
Use g_pattern_spec_match_string() instead to avoid this problem.
2. The type of second parameter in g_ptr_array_add() is
'gpointer' {aka 'void *'}, but the type of reg->name is 'const char*'.
Cast the type of reg->n
On Fri, 22 Mar 2024 03:21:21 -0700, Breno Leitao wrote:
> Hello Xuan,
>
> On Fri, Mar 22, 2024 at 10:00:22AM +0800, Xuan Zhuo wrote:
> > On Thu, 21 Mar 2024 09:54:30 -0700, Breno Leitao wrote:
>
> > > 4) Since the command above does not have a key, then the last
> > >scatter-gatter entry will
Hi Pierrick,
thanks for your reply, and I will modify and push the patch later.
thanks
Xingtao
> -Original Message-
> From: Pierrick Bouvier
> Sent: Monday, March 25, 2024 12:31 PM
> To: Yao, Xingtao/姚 幸涛 ; Peter Maydell
>
> Cc: alex.ben...@linaro.org; erdn...@crans.org; ma.mando...@g
Markus Armbruster writes:
> Commit d23055b8db8 (qapi: Require descriptions and tagged sections to
> be indented) indented add_client's example too much. Revert that.
>
> Signed-off-by: Markus Armbruster
> ---
> qapi/misc.json | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
>
Hi Daniel,
Thanks for your reviewing. I see your comments in the v7.
I have some doubts about what you said about the QAPI. Do you want me to
convert the current design into the QAPI parsing like the
IOThreadVirtQueueMapping? And we need to add new json definition in the
qapi/ directory?
Th
On 3/25/24 07:00, Xingtao Yao (Fujitsu) wrote:
Pete:
Thanks for your comment.
I also find a similar patch written by Pierrick:
https://lore.kernel.org/qemu-devel/20240118032400.3762658-15-pierrick.bouv...@linaro.org/
but for some reason, the patch was not merged yet.
shall I need to continue t
Split do_unit_cond to do_unit_zero_cond to only handle
conditions versus zero. These are the only ones that
are legal for UXOR. Simplify trans_uxor accordingly.
Rename do_unit to do_unit_addsub, since xor has been split.
Properly compute carry-out bits for add and subtract,
mirroring the code in
With r1 as zero is by far the only usage of UADDCM, as the easiest
way to invert a register. The compiler does occasionally use the
addition step as well, and we can simplify that to avoid a temp
and write directly into the destination.
Signed-off-by: Richard Henderson
---
target/hppa/translate
Two problems, both related to the reconstruction and computation
of carry bits. Simplify UXOR a bit, since no carry is involved.
While in the area, optimize UADDCM without condition, as that's
the common case for inverting a register.
r~
Richard Henderson (3):
targt/hppa: Fix DCOR reconstruc
The carry bits for each nibble N are located in bit (N+1)*4,
so the shift by 3 was off by one. Furthermore, the carry bit
for the most significant carry bit is indeed located in bit 64,
which is located in a different storage word.
Use a double-word shift-right to reassemble into a single word
an
Pete:
Thanks for your comment.
I also find a similar patch written by Pierrick:
https://lore.kernel.org/qemu-devel/20240118032400.3762658-15-pierrick.bouv...@linaro.org/
but for some reason, the patch was not merged yet.
shall I need to continue tracking the fixes of this bug?
> -Original M
In RVV and vcrypto instructions, the masked and tail elements are set to 1s
using vext_set_elems_1s function if the vma/vta bit is set. It is the element
agnostic policy.
However, this function can't deal the big endian situation. This patch fixes
the problem by adding handling of such case.
Sign
On Sun, 24 Mar 2024, Dr. David Alan Gilbert wrote:
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
Signed-off-by: Philippe Mathieu-Daudé
---
target/m68k/cpu.h | 2 +-
target/m68k/helper.c | 126 +
Ping...
On 1/22/2024 4:55 PM, Binbin Wu wrote:
Gentle ping...
Please help to review and consider applying the patch series. (The KVM
part has been merged).
On 1/12/2024 2:00 PM, Binbin Wu wrote:
Linear-address masking (LAM) [1], modifies the checking that is
applied to
*64-bit* linear addr
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> Replace qemu_printf() by monitor_printf() / monitor_puts() in monitor.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/m68k/cpu.h | 2 +-
> target/m68k/helper.c | 126 +-
> target/m68k/m
On 3/24/24 11:39, Richard Henderson wrote:
On 3/23/24 22:09, Sven Schnelle wrote:
64 Bit hppa no longer has a fixed 32/32 bit split between space and
offset. Instead it uses 42 bits for the offset. The lower 10 bits of
the space are always zero, leaving 22 bits actually used. Simply or
the value
On 3/24/24 08:41, Sven Schnelle wrote:
7f09e0: val=000fffb0301f r2=110e0f01 r1=01fff600
phys=fffb 4K aid=1 pl1=0, pl2=0 type=1 (DATA RW)
'val' is the value constructed from IOR/ISR,
Is this byte swapped in some weird way? I do not see how 'val' corresponds to
On 3/23/24 22:09, Sven Schnelle wrote:
64 Bit hppa no longer has a fixed 32/32 bit split between space and
offset. Instead it uses 42 bits for the offset. The lower 10 bits of
the space are always zero, leaving 22 bits actually used. Simply or
the values together to build the gva.
Signed-off-by:
On Sun, 24 Mar 2024 at 16:13, BALATON Zoltan wrote:
>
> Add missing space to fix character formatting where it was missed in
> two places.
>
> Fixes: 623d9065b6 (docs/system/ppc: Document running Linux on AmigaNG
> machines)
> Signed-off-by: BALATON Zoltan
> ---
Reviewed-by: Peter Maydell
than
The current logic assumes that at least 1 byte is present in the FIFO when
executing a non-DMA SELATNS command, but this may not be the case if the
guest executes an invalid ESP command sequence.
Reported-by: Chuhong Yuan
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 3 ++-
1 file changed
The aim is to restrict the esp_fifo_*() functions so that they only operate on
the hardware FIFO. When reading from cmdfifo in do_command_phase() use the
underlying esp_fifo8_pop_buf() function directly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 2 +-
1 file changed, 1 insertion(+), 1
Now that all users of esp_fifo_pop_buf() operate on the main FIFO there is no
need to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw
There are still a few places that use fifo8_push() instead of esp_fifo_push() in
order to push a value into the FIFO. Update those places to use esp_fifo_push()
instead.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 6 +++---
1 file changed, 3 insertion
Now that all users of esp_fifo_pop() operate on the main FIFO there is no need
to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/scs
The esp_cdb_length() function is only used as part of a calculation to determine
whether the cmdfifo contains an entire SCSI CDB. Rework esp_cdb_length() into a
new esp_cdb_ready() function which both enables us to handle the case where
scsi_cdb_length() returns -1, plus simplify the logic for its
This ensures that the DRQ line is always set correctly when reading/writing
single bytes to/from the FIFO.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/scsi/esp.c b/hw
This ensures that esp_update_drq() is called via esp_fifo_push() whenever the
host uses PDMA to transfer data to a SCSI device.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw
This new function sets the DRQ line correctly according to the current transfer
mode, direction and FIFO contents. Update esp_fifo_push_buf() and
esp_fifo_pop_buf()
to use it so that DRQ is always set correctly when reading/writing multiple
bytes
to/from the FIFO.
Signed-off-by: Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 9386704a58..5b169b3720 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -315,7 +315,8 @@ static void do
Instead of pushing data into the FIFO directly with fifo8_push_all(), add a new
esp_fifo_push_buf() function and use it accordingly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --gi
Now the esp_update_drq() is called for all reads/writes to the FIFO, there is
no need to manually raise and lower the DRQ signal.
Signed-off-by: Mark Cave-Ayland
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/611
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1831
---
hw/scsi/e
The aim is to restrict the esp_fifo_*() functions so that they only operate on
the hardware FIFO. When reading from cmdfifo in do_message_phase() use the
underlying esp_fifo8_pop_buf() function directly.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 2 +-
1 file changed, 1 insertion(+), 1
During normal use the cmdfifo will never wrap internally and cmdfifo_cdb_offset
will always indicate the start of the SCSI CDB. However it is possible that a
malicious guest could issue an invalid ESP command sequence such that cmdfifo
wraps internally and cmdfifo_cdb_offset could point beyond the
This allows these functions to be used earlier in the file without needing a
separate forward declaration.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --g
[MCA: Since v1 I've received a few reports of FIFO assert()s being triggered
and a
cmdfifo buffer overflow discovered by fuzzing the updated ESP code. The
updating of
all FIFO push/pop operations to use the esp_fifo_*() functions in this series
provides protection against this, and in conjunction
Update esp_fifo_pop_buf() to be a simple wrapper onto the new
esp_fifo8_pop_buf()
function.
Signed-off-by: Mark Cave-Ayland
---
hw/scsi/esp.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 590ff99744..1b7b118a0b 100644
--- a/hw/scsi
Now that all users of esp_fifo_push() operate on the main FIFO there is no need
to pass the FIFO explicitly.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
---
hw/scsi/esp.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/scsi/esp.c b/hw/sc
Hi Richard,
Richard Henderson writes:
> In particular Figure 2-14 for "data translation disabled" may be
> instructive. Suppose the cpu does not implement all of the physical
> address lines (true for all extant pa-risc cpus; qemu implements 40
> bits to match pa-8500 iirc). Suppose when repor
On 3/23/24 22:09, Sven Schnelle wrote:
The CPU seems to mask a few bits in the offset when running
under HP-UX. ISR/IOR register contents for an address in
the processor HPA (0xfffa) on my C8000 and J6750:
running on Linux: 3fff c000fffa0500
running on HP-UX:
On 3/24/24 12:07, Michael Tokarev wrote:
22.03.2024 22:46, Daniel Henrique Barboza :
On 3/22/24 14:16, Michael Tokarev wrote:
22.03.2024 11:53, Alistair Francis :
RISC-V PR for 9.0
* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming
On 3/23/24 22:09, Sven Schnelle wrote:
move it to cpu.h, so it can also be used in hppa_form_gva_psw()
Signed-off-by: Sven Schnelle
---
target/hppa/cpu.h | 10 --
target/hppa/translate.c | 12 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
Reviewed-by: Richar
On 3/24/24 18:13, Richard Henderson wrote:
On 3/23/24 11:15, Helge Deller wrote:
The uaddcmt (UNIT ADD COMPLEMENT AND TRAP ON CONDITION) instruction
triggers a trap if the condition is true, and stores the result of the
addition in the target register otherwise.
It does not use the condition to
On 3/23/24 22:09, Sven Schnelle wrote:
64 Bit hppa no longer has a fixed 32/32 bit split between space and
offset. Instead it uses 42 bits for the offset. The lower 10 bits of
the space are always zero, leaving 22 bits actually used. Simply or
the values together to build the gva.
Signed-off-by:
On 3/23/24 11:15, Helge Deller wrote:
The uaddcmt (UNIT ADD COMPLEMENT AND TRAP ON CONDITION) instruction
triggers a trap if the condition is true, and stores the result of the
addition in the target register otherwise.
It does not use the condition to nullify the following instruction, so
drop t
Test:
- read/write from/to the usart registers
- send/receive a character/string over the serial port
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build| 3 +-
tests/qtest/stm32l4x5_usart-test.c | 326 +
2 files changed,
Add a function to change the settings of the
serial connection.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/char/stm32l4x5_usart.c | 98 +++
hw/char/trace-events | 1 +
2 files changed, 99 insertions(+)
diff --git a/hw/char/stm32l4x5
Add the USART to the SoC and connect it to the other implemented devices.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
docs/system/arm/b-l475e-iot01a.rst | 2 +-
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 82 +++---
in
Implement the ability to read and write characters to the
usart using the serial port.
The character transmission is based on the
cmsdk-apb-uart implementation.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/char/stm32l4x5_usart.c | 139 ++
h
The "clock_set_mul_div" function doesn't propagate the clock period to
the children if it is changed (e.g. by enabling/disabling
a clock multiplexer).
This was overlooked during the implementation due to late changes.
This commit propagates the change if the multiplier or divider changes.
The usa
Add the basic infrastructure (register read/write, type...)
to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
of the STM32L4x5 to deduplicate code and enable the
implementation of different behaviors depending on the type.
Signed-off-by: Arnaud Minier
S
This patch adds the STM32L4x5 USART
(Universal Synchronous/Asynchronous Receiver/Transmitter)
device and is part of a series implementing the
STM32L4x5 with a few peripherals.
It implements the necessary functionalities to receive/send
characters over the serial port, which are useful to
communica
On 3/24/24 09:09, Sven Schnelle wrote:
64 Bit hppa no longer has a fixed 32/32 bit split between space and
offset. Instead it uses 42 bits for the offset. The lower 10 bits of
the space are always zero, leaving 22 bits actually used. Simply or
the values together to build the gva.
Signed-off-by:
On 3/24/24 09:09, Sven Schnelle wrote:
The CPU seems to mask a few bits in the offset when running
under HP-UX. ISR/IOR register contents for an address in
the processor HPA (0xfffa) on my C8000 and J6750:
running on Linux: 3fff c000fffa0500
running on HP-UX:
Add missing space to fix character formatting where it was missed in
two places.
Fixes: 623d9065b6 (docs/system/ppc: Document running Linux on AmigaNG machines)
Signed-off-by: BALATON Zoltan
---
docs/system/ppc/amigang.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/d
On 3/24/24 09:09, Sven Schnelle wrote:
move it to cpu.h, so it can also be used in hppa_form_gva_psw()
Signed-off-by: Sven Schnelle
Reviewed-by: Helge Deller
Helge
---
target/hppa/cpu.h | 10 --
target/hppa/translate.c | 12 +++-
2 files changed, 11 insertions(+)
After exit Qemu need to return the terminal to the default state.
Signed-off-by: Irina Ryapolova
---
chardev/char-win-stdio.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/chardev/char-win-stdio.c b/chardev/char-win-stdio.c
index 1a18999e78..4fa2c3de8b 100644
--- a/chardev/char-win-st
CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
for injecting interrupts into VS level in situations not fully supported by the
facilities described thus far, but only with more active involvement of the
hypervisor.
A hypervisor must use hvictl for any of the follow
From: Vadim Shakirov
In the AIA specification in the paragraph "Virtual interrupts for VS level"
it is indicated for interrupts 13-63: if the bit in hideleg is enabled,
then the corresponding vsip and vsie bits are aliases to sip and sie
Signed-off-by: Vadim Shakirov
Reviewed-by: Alistair Franc
Need to convert mmu_idx to privilege mode for PMP function.
Signed-off-by: Irina Ryapolova
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ce7322011d..fc090d729a 100644
--- a/target/risc
22.03.2024 22:46, Daniel Henrique Barboza :
On 3/22/24 14:16, Michael Tokarev wrote:
22.03.2024 11:53, Alistair Francis :
RISC-V PR for 9.0
* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming iforce register
* Remove the dependency of Zv
On Sat, 23 Mar 2024 at 06:20, Akihiko Odaki wrote:
>
> [NSWindow setContentAspectRatio:] does not trigger window resize itself,
> so the wrong aspect ratio will persist if nothing resizes the window.
> Call [NSWindow setContentSize:] in such a case.
>
> Fixes: 91aa508d0274 ("ui/cocoa: Let the plat
The current handling of invalid virtqueue elements inside the TX/RX virt
queue handlers is wrong.
They are added in a per-stream invalid queue to be processed after the
handler is done examining each message, but the invalid message might
not be specifying any stream_id; which means it's invalid t
This is a logic fix for the error handling in the TX/RX virt queue
handlers. A potential invalid address dereference was reported and fixed
by Zheyu Ma in <20240322110827.568412-1-zheyum...@gmail.com>. This patch
moves the invalid message storage from the stream structs to the virtio
device str
On Tue, Mar 19, 2024 at 04:42:54PM +0100, Philippe Mathieu-Daudé wrote:
> Convert cpu_get_tb_cpu_state() to TCGCPUOps::get_cpu_state().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/tricore/cpu.h | 12
> target/tricore/cpu.c | 13 +
> 2 files changed, 13 inser
On Tue, Mar 19, 2024 at 06:14:13AM +0100, Philippe Mathieu-Daudé wrote:
> 'address' got converted from target_ulong to vaddr in commit
> 68d6eee73c ("target/tricore: Convert to CPUClass::tlb_fill").
> Use the corresponding format string to avoid casting.
>
> Signed-off-by: Philippe Mathieu-Daudé
pkt->payload_frags +
NET_TX_PKT_PL_START_FRAG - 1,
pkt->payload_len);
---
base-commit: ba49d760eb04630e7b15f423ebecf6c871b8f77b
change-id: 20240324-tx-c57d3c22ad73
Best regards,
--
Akihiko Odaki
64 Bit hppa no longer has a fixed 32/32 bit split between space and
offset. Instead it uses 42 bits for the offset. The lower 10 bits of
the space are always zero, leaving 22 bits actually used. Simply or
the values together to build the gva.
Signed-off-by: Sven Schnelle
---
target/hppa/mem_help
Hi,
in preparation of getting 64bit HP-UX running in qemu, here are a few fixes
to make HP-UX progress a bit further.
Sven Schnelle (3):
target/hppa: use gva_offset_mask() everywhere
target/hppa: mask offset bits in gva
target/hppa: fix building gva for wide mode
target/hppa/cpu.h
The CPU seems to mask a few bits in the offset when running
under HP-UX. ISR/IOR register contents for an address in
the processor HPA (0xfffa) on my C8000 and J6750:
running on Linux: 3fff c000fffa0500
running on HP-UX: 301f c000fffa0500
I haven't foun
move it to cpu.h, so it can also be used in hppa_form_gva_psw()
Signed-off-by: Sven Schnelle
---
target/hppa/cpu.h | 10 --
target/hppa/translate.c | 12 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index a92dc3
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