PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
interrupts and TLB misses and is quite costly. Running the
kvm-unit-tests sieve program with radix MMU enabled thrashes the TCG
TLB and spends a lot of time in TLB and page table walking code. The
test takes 67 seconds to complete
{
"emoji": "🙏",
"version": 1
}
This option controls the host page size. From the mis-usage in
our own testsuite, this is easily confused with guest page size.
The only thing that occurs when changing the host page size is
that stuff breaks, because one cannot actually change the host
page size. Therefore reject all but the no
v2: Fix bsd-user build errors.
r~
The following changes since commit 3d54cbf269d63ff1d500b35b2bcf4565ff8ad485:
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
(2024-02-22 15:44:29 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.
Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user.
It should be removed from bsd-user as well, but defer that cleanup.
Reviewed-by: Warner Losh
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Tested-by: Ilya Leoshkevich
Acked-by: Helge Deller
Message-Id: <
When show-cursor is on, most of the time Windows VM draws the cursor by
itself and hands it over to Qemu as a separate resource. However,
sometimes, Windows OS gives control of the cursor to applications like
Notepad. In such cases a software cursor which is part of the overall
framebuffer is drawn
When show-cursor is on, most of the time Windows VM draws the cursor by
itself and hands it over to Qemu as a separate resource. However,
sometimes, Windows OS gives control of the cursor to applications like
Notepad. In such cases a software cursor which is part of the overall
framebuffer is drawn
On 2/23/24 03:45, Peter Maydell wrote:
bsd-user fails to compile:
https://gitlab.com/qemu-project/qemu/-/jobs/6241616724
../bsd-user/main.c:379:30: error: use of undeclared identifier 'arg';
did you mean 'argv'?
if (qemu_strtoui(arg, NULL, 10, &size) || size != want) {
^~~
Gr
On 2/23/24 00:32, Jinjie Ruan via wrote:
A PE that implements FEAT_NMI and FEAT_GICv3 also implements
FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
FEAT_GICv3_NMI
So included support FEAT_GICv3_NMI feature as part of virt platform
GIC initialization if FEAT_NMI and FE
On 2/23/24 00:32, Jinjie Ruan via wrote:
In CPU Interface, if the IRQ has the superpriority property, report
NMI to the corresponding PE.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove handling nmi_is_irq flag.
---
hw/intc/arm_gicv3_cpuif.c | 6 +-
1 file changed, 5 insertions(+), 1 deletio
On 2/23/24 01:35, Ilya Leoshkevich wrote:
On Thu, Feb 22, 2024 at 05:03:09PM -1000, Richard Henderson wrote:
Handle combined host and guest alignment requirements.
Handle host and guest page size differences.
Handle SHM_EXEC.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/115
Signed-of
On 2/23/24 00:32, Jinjie Ruan via wrote:
This patch set implements FEAT_NMI and FEAT_GICv3_NMI for armv8. These
introduce support for a new category of interrupts in the architecture
which we can use to provide NMI like functionality.
There are two modes for using this FEAT_NMI. When PSTATE.ALLI
On 2/23/24 00:32, Jinjie Ruan via wrote:
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI prioirty
is higher than 0x80, otherwise it is higher than 0x0. And save NMI
super prioirty information in hppi.superprio to deliver NMI exception.
Since both GICR and GICD can deliver NMI, it i
On 2/23/24 00:32, Jinjie Ruan via wrote:
Add the NMIAR CPU interface registers which deal with acknowledging NMI.
When introduce NMI interrupt, there are some updates to the semantics for the
register ICC_IAR1_EL1 and ICC_HPPIR1_EL1. For ICC_IAR1_EL1 register, it
should return 1022 if the intid
On 2/23/24 00:32, Jinjie Ruan via wrote:
Augment the GICv3's QOM device interface by adding one
new set of sysbus IRQ line, to signal NMI to each CPU.
Signed-off-by: Jinjie Ruan
---
v3:
- Add support for VNMI.
---
hw/intc/arm_gicv3_common.c | 6 ++
include/hw/intc/arm_gic_common.h
Het Gala writes:
> Introduce support for adding a 'channels' argument to migrate_qmp_fail,
> migrate_incoming_qmp and migrate_qmp functions within the migration qtest
> framework, enabling enhanced control over migration scenarios.
Can't we just pass a channels string like you did in the origina
On 2/23/24 00:32, Jinjie Ruan via wrote:
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so the NMI exception trap entry
behave like IRQ.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove the FIQ NMI handle.
---
target/arm/helpe
On 2/23/24 00:32, Jinjie Ruan via wrote:
Added properties to enable FEAT_GICv3_NMI feature, setup distributor
and redistributor registers to indicate NMI support.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_common.c | 1 +
hw/intc/arm_gicv3_dist.c | 2 ++
hw/intc/gicv3
On 2/23/24 00:32, Jinjie Ruan via wrote:
Wire the new NMI and VNMI interrupt line from the GIC to each CPU.
Signed-off-by: Jinjie Ruan
---
v3:
- Also add VNMI wire.
---
hw/arm/virt.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 2/23/24 00:32, Jinjie Ruan via wrote:
Add IS and FS bit in ISR_EL1 and handle the read. With CPU_INTERRUPT_NMI, both
CPSR_I and ISR_IS must be set.
Signed-off-by: Jinjie Ruan
--
v3:
- CPU_INTERRUPT_NMI do not set FIQ, so remove it.
- With CPU_INTERRUPT_NMI, both CPSR_I and ISR_IS must be set
On 2/23/24 00:32, Jinjie Ruan via wrote:
Add GICR_INMIR0 register and support access GICR_INMIR0.
Signed-off-by: Jinjie Ruan
---
hw/intc/arm_gicv3_redist.c | 23 +++
hw/intc/gicv3_internal.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/hw/intc/arm_gicv3_redi
On 23/02/2024 13.44, Paolo Bonzini wrote:
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
functions such as usb_create_simple can be inline
On 2/23/24 00:32, Jinjie Ruan via wrote:
According to Arm GIC section 4.6.3 Interrupt superpriority, the interrupt
with superpriority is always IRQ, never FIQ, so handle NMI same as IRQ in
arm_phys_excp_target_el().
Signed-off-by: Jinjie Ruan
---
v3:
- Remove nmi_is_irq flag in CPUARMState.
- Ha
On 2/23/24 00:32, Jinjie Ruan via wrote:
This only implements the external delivery method via the GICv3.
Signed-off-by: Jinjie Ruan
---
v3:
- Not include CPU_INTERRUPT_NMI when FEAT_NMI not enabled
- Add ARM_CPU_VNMI.
- Refator nmi mask in arm_excp_unmasked().
- Test SCTLR_ELx.NMI for ALLINT m
On Fri, 23 Feb 2024, Thomas Huth wrote:
On 23/02/2024 13.44, Paolo Bonzini wrote:
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
function
From: Peter Maydell
Reviewed-by: Thomas Huth
Reviewed-by: "Daniel P. Berrangé"
Reviewed-by: Alex Bennée
Signed-off-by: Peter Maydell
Message-ID: <20240222130920.362517-2-peter.mayd...@linaro.org>
Signed-off-by: Thomas Huth
---
docs/about/build-platforms.rst | 2 ++
docs/about/removed-feat
From: Peter Maydell
QEMU has historically used variable length arrays only very rarely.
Variable length arrays are a potential security issue where an
on-stack dynamic allocation isn't correctly size-checked, especially
when the size comes from the guest. (An example problem of this kind
from th
HPTES_PER_GROUP is 8 and HASH_PTE_SIZE_64 is 16, so we don't waste
too many bytes by always allocating the maximum amount of bytes on
the stack here to get rid of the variable length array.
Suggested-by: Peter Maydell
Message-ID: <20240221162636.173136-3-th...@redhat.com>
Reviewed-by: Peter Mayde
From: Paolo Bonzini
The processor tracing features in cpu_x86_cpuid() are hardcoded to a set
that should be safe on all processor that support PT virtualization.
But as an additional check, x86_cpu_filter_features() also checks
that the accelerator supports that safe subset, and if not it marks
C
On Tue, 20 Feb 2024 at 19:28, Philippe Mathieu-Daudé wrote:
> cpu_interrupt() doesn't scale well with heterogenous machines
> because its mask is target specific (defined in target/ARCH/cpu.h).
>
> While it is (often...) used by target-specific hw to notify cpu,
> there is no restriction to use su
On 23/02/2024 15.26, BALATON Zoltan wrote:
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and
replace them with newly added public header to allow moving internal.h
into hw/ide to really stop exposing it.
Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files)
Sign
On 23/02/2024 17.21, Alex Bennée wrote:
This is less than ideal but easier than making sure we get all the
iterations of the memory test. Update the comment accordingly.
Signed-off-by: Alex Bennée
---
tests/tcg/Makefile.target | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
d
From: Peter Maydell
We don't support 32-bit Windows any more, so we don't need to defend it
with this CI job.
Signed-off-by: Peter Maydell
Reviewed-by: Thomas Huth
Reviewed-by: "Daniel P. Berrangé"
Reviewed-by: Alex Bennée
Message-ID: <20240222130920.362517-3-peter.mayd...@linaro.org>
Signed
From: Daniel Palmer
>From the 68010 a word with the frame format and exception vector
are placed on the stack before the PC and SR.
M68K_FEATURE_QUAD_MULDIV is currently checked to workout if to do
this or not for the configured CPU but that flag isn't set for
68010 so currently the exception st
To be able to compile QEMU with -Wvla (to prevent potential security
issues), we need to get rid of the variable length array in the
kvmppc_save_htab() function. Replace it with a heap allocation instead.
Message-ID: <20240221162636.173136-2-th...@redhat.com>
Reviewed-by: Peter Maydell
Signed-off
On 2/23/24 00:32, Jinjie Ruan via wrote:
+static CPAccessResult aa64_allint_access(CPUARMState *env,
+ const ARMCPRegInfo *ri, bool isread)
+{
+if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
+(arm_hcrx_el2_eff(env) & HCRX_TALLINT)) {
From: Marc-André Lureau
When compiling with "configure --without-default-devices", the
dbus-display-test fails since it implicitly assumes that the
machine comes with a default console.
There doesn't seem to be an easy way to figure this during build time,
so skip the tests requiring the Console
Hi Peter!
The following changes since commit 3d54cbf269d63ff1d500b35b2bcf4565ff8ad485:
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
(2024-02-22 15:44:29 +)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2024-0
From: Peter Maydell
Now we don't build msys2-32bit we don't need the abstraction out of the
common msys2 handling from the 32-vs-64-bit specifics. Collapse it
down into the msys2-64bit job definition.
Signed-off-by: Peter Maydell
Reviewed-by: "Daniel P. Berrangé"
Reviewed-by: Philippe Mathieu-
If "configure" has been run with "--without-default-devices", there is
no e1000 device in the binaries, so the boot-serial-test currently fails
in that case since it tries to use the e1000 with the sam460ex machine.
Since we're testing the serial output here, and not the NIC, let's
simply switch t
From: Bibo Mao
The cdrom test skips to execute on LoongArch system with command
"make check", this patch enables cdrom test for LoongArch virt
machine platform.
With this patch, cdrom test passes to run on LoongArch virt
machine type.
Signed-off-by: Bibo Mao
Message-ID: <20240217100230.134042-
On 2/23/24 00:32, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
v3:
- Remove EL0 check in allint_check().
- Add TALLINT check for
On Tue, 20 Feb 2024 at 19:28, Philippe Mathieu-Daudé wrote:
>
> In order to remove calls to cpu_interrupt() from hw/ code,
> expose the TMR and SMP interrupts via QDev as named GPIOs.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/alpha/cpu.c | 30 ++
> 1 fi
On Fri, 23 Feb 2024, David Parsons wrote:
Hi Akihiko
I’ve re-worked the patch to match your suggestion. I have compiled
and tested it on Sonoma and Monterey and both builds worked correctly.
New patch is below. I’m new to sending patches to QEMU so please let
me know if I need to do anything el
On Tue, 23 Jan 2024 at 17:14, Peter Maydell wrote:
>
> Here's my proposal for the freeze dates for 9.0:
>
> 2024-03-12 Soft feature freeze (all feature changes must be in
>a pullreq on list by this date)
> 2024-03-19 Hard feature freeze. Tag rc0
> 2024-03-26 Tag rc1
> 2024-04-02 Tag rc
On 2/23/24 00:32, Jinjie Ruan via wrote:
The ALLINT bit in PSTATE is used to mask all IRQ or FIQ interrupts.
Place this in its own field within ENV, as that will
make it easier to handle ALLINT set/clear.
With the change to pstate_read/write, exception entry
and return are automatically handled
On Fri, 23 Feb 2024 08:21:42 -1000
Richard Henderson wrote:
> On 2/23/24 08:20, Peter Maydell wrote:
> > The qatomic_cmpxchg() and qatomic_cmpxchg__nocheck() macros have
> > a comment that reads:
> > Returns the eventual value, failed or not
> >
> > This is somewhere between cryptic and wrong,
This patch adds a new device STM32L4x5 GPIO device and is part
of a series implementing the STM32L4x5 with a few peripherals.
Changes from v4 :
- gpio.c : use helpers `is_pull_up()`, `is_pull_down()`, `is_output()`
for more clarity
- gpio.c : correct `update_gpio_idr()` in case of open-drain pin
s
On 2/23/24 08:20, Peter Maydell wrote:
The qatomic_cmpxchg() and qatomic_cmpxchg__nocheck() macros have
a comment that reads:
Returns the eventual value, failed or not
This is somewhere between cryptic and wrong, since the value actually
returned is the value that was in memory before the cmpx
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
Reviewed-by: Philippe Mathieu-Daudé
---
include/hw/arm/stm32l4x5_soc.h | 2 +
hw/arm/stm32l4x5_soc.c | 68 +++---
hw/arm/Kconfig | 3 +-
3 files changed, 58 insertions(+), 15 deletions(
Features supported :
- the 8 STM32L4x5 GPIOs are initialized with their reset values
(except IDR, see below)
- input mode : setting a pin in input mode "externally" (using input
irqs) results in an out irq (transmitted to SYSCFG)
- output mode : setting a bit in ODR sets the corresponding o
The qatomic_cmpxchg() and qatomic_cmpxchg__nocheck() macros have
a comment that reads:
Returns the eventual value, failed or not
This is somewhere between cryptic and wrong, since the value actually
returned is the value that was in memory before the cmpxchg. Reword
to match how we describe thes
The testcase contains :
- `test_idr_reset_value()` :
Checks the reset values of MODER, OTYPER, PUPDR, ODR and IDR.
- `test_gpio_output_mode()` :
Checks that writing a bit in register ODR results in the corresponding
pin rising or lowering, if this pin is configured in output mode.
- `test_gpio_inpu
On 2/23/24 08:01, Jonathan Cameron wrote:
Seen testing of CXL emulation on arm64 (currently out of tree).
CXL interleave occurs at subpage granularity so is emulated using an IO
Memory Region. The memory is general purpose and as such may contain page
tables. FEAT_HADFS using atomic accesses fro
On 23/2/24 09:56, Zhao Liu wrote:
From: Zhao Liu
IOAPICCommonClass implements its own private realize(), and this private
realize() allows error.
Since IOAPICCommonClass.realize() returns void, to check the error,
dereference @errp with ERRP_GUARD().
Signed-off-by: Zhao Liu
---
v2:
* Add t
On 2/23/2024 12:41 PM, Philippe Mathieu-Daudé wrote:
> On 23/2/24 15:01, Steven Sistare wrote:
>> On 2/23/2024 1:01 AM, Philippe Mathieu-Daudé wrote:
>>> On 22/2/24 22:47, Steve Sistare wrote:
Generalize hmp_split_at_comma() to take any delimiter string, rename
as str_split(), and move it
On Fri, 23 Feb 2024 at 10:02, Peter Maydell wrote:
>
> On Thu, 22 Feb 2024 at 21:21, Richard Henderson
> wrote:
> >
> > On 2/19/24 06:12, Jonathan Cameron wrote:
> > > I'm far from confident this handling here is correct. Hence
> > > RFC. In particular not sure on what locks I should hold for th
On Wed, Feb 21, 2024 at 10:15:53AM -0800, nifan@gmail.com wrote:
> From: Fan Ni
>
> v3[1]->v4:
>
> The code is rebased on mainstream QEMU with the following patch series:
>
> hw/cxl/mailbox: change CCI cmd set structure to be a member, not a reference
> hw/cxl/mailbox: interface to add CCI
Seen testing of CXL emulation on arm64 (currently out of tree).
CXL interleave occurs at subpage granularity so is emulated using an IO
Memory Region. The memory is general purpose and as such may contain page
tables. FEAT_HADFS using atomic accesses from the page table walkers to
update accessed
On 23/02/2024 13:09, Paolo Bonzini wrote:
The address translation logic in get_physical_address() will currently
truncate physical addresses to 32 bits unless long mode is enabled.
This is incorrect when using physical address extensions (PAE) outside
of long mode, with the result that a 32-bit o
On 23/2/24 09:56, Zhao Liu wrote:
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
On 11/1/24 11:29, Mark Cave-Ayland wrote:
Mark Cave-Ayland (3):
nubus-device: round Declaration ROM memory region address to
qemu_target_page_size()
nubus.h: increase maximum Declaration ROM size from 128k to 1Mb
nubus: add nubus-virtio-mmio device
Thanks, series queued.
On 22/2/24 16:28, Philippe Mathieu-Daudé wrote:
ga_get_win_name() iterates over all elements in the arrays by
checking the 'version' field is non-NULL. Since the arrays are
guarded by a NULL terminating element, we don't need to specify
their size:
static char *ga_get_win_name(...)
{
On Fri, Feb 23, 2024 at 6:33 PM Philippe Mathieu-Daudé
wrote:
>
> On 23/2/24 13:44, Paolo Bonzini wrote:
> > With --without-default-devices it is possible to build a binary that
> > does not include any USB host controller and therefore that does not
> > include the code guarded by CONFIG_USB. Wh
On 23/2/24 15:47, Laurent Vivier wrote:
Le 11/01/2024 à 11:29, Mark Cave-Ayland a écrit :
Mark Cave-Ayland (3):
nubus-device: round Declaration ROM memory region address to
qemu_target_page_size()
nubus.h: increase maximum Declaration ROM size from 128k to 1Mb
nubus: add nubus-v
On 23/2/24 15:01, Steven Sistare wrote:
On 2/23/2024 1:01 AM, Philippe Mathieu-Daudé wrote:
On 22/2/24 22:47, Steve Sistare wrote:
Generalize hmp_split_at_comma() to take any delimiter string, rename
as str_split(), and move it to util/strList.c.
No functional change.
Signed-off-by: Steve Sis
Hi Akihiko
I’ve re-worked the patch to match your suggestion. I have compiled
and tested it on Sonoma and Monterey and both builds worked correctly.
New patch is below. I’m new to sending patches to QEMU so please let
me know if I need to do anything else to get it incorporated into the
repo.
D
On 23/2/24 13:44, Paolo Bonzini wrote:
With --without-default-devices it should not be required to have
devices in the binary that are removed by -nodefaults. It should be
therefore possible to build a binary that does not include any USB
host controller or any of the code guarded by CONFIG_USB.
On 23/2/24 13:44, Paolo Bonzini wrote:
Because USB_EHCI_SYSBUS selects USB_EHCI, there is no need to include
hcd-ehci.c explicitly.
Signed-off-by: Paolo Bonzini
---
hw/usb/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 23/2/24 13:44, Paolo Bonzini wrote:
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
functions such as usb_create_simple can be inlined,
A small number of migration options are accessed by migration clients,
but to see them clients must include all of options.h, which is mostly
for migration core code. migrate_mode() in particular will be needed by
multiple clients.
Refactor the option declarations so clients can see the necessary
On 23/2/24 13:44, Paolo Bonzini wrote:
With --without-default-devices it is possible to build a binary that
does not include any USB host controller and therefore that does not
include the code guarded by CONFIG_USB. While the simpler creation
functions such as usb_create_simple can be inlined,
On 23/2/24 13:44, Paolo Bonzini wrote:
Split the sysbus version to a separate file so that it is not
included in PCI-only machines, and adjust Kconfig for machines
that do need sysbus-ohci. The copyrights are based on the
time and employer of balrog and Paul Brook's contributions.
While adjusti
On Mon, 19 Feb 2024 at 01:20, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 4 +
> hw/arm/bcm2838_peripherals.c | 14 +
> hw/arm/raspi4b.c | 1 -
> hw/misc/bcm2838_rng200.c | 405 +
On 23/2/24 13:44, Paolo Bonzini wrote:
Inline the sole remaining use, which is for the -usbdevice command line.
Signed-off-by: Paolo Bonzini
---
include/hw/usb.h | 1 -
hw/usb/bus.c | 15 +--
2 files changed, 1 insertion(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-D
On Fri, Feb 23, 2024 at 04:16:53PM +0900, Wonjae Lee wrote:
> On 2024-02-22 오전 3:16, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > Add dynamic capacity extent list representative to the definition of
> > CXLType3Dev and add get DC extent list mailbox command per
> > CXL.spec.3.1:.8.2.9.9.9.
On 23/2/24 13:43, Paolo Bonzini wrote:
object_resolve_type_unambiguous provides a useful functionality, that
is currently emulated for example by usb_bus_find(). Move it to core
code and add error reporting for increased generality.
Signed-off-by: Paolo Bonzini
---
include/qom/object.h | 13
On 23/2/24 15:26, BALATON Zoltan wrote:
Remove last two includes of hw/ide/intarnal.h outside of hw/ide and
replace them with newly added public header to allow moving internal.h
into hw/ide to really stop exposing it.
Fixes: a11f439a0e (hw/ide: Stop exposing internal.h to non-IDE files)
Signed-
On Mon, 19 Feb 2024 at 01:21, Sergey Kambalin wrote:
>
> This commit adds RPi4B device tree modifications:
> - disable pcie, rng200, thermal sensor and genet devices
> (they're going to be re-enabled in the following commits)
> - create additional memory region in device tree
> if RAM amount e
Alex Bennée writes:
> Peter Maydell writes:
>
>> The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
>> was unfortunately added with a license of GPL-v3-or-later, which is
>> not compatible with other QEMU code which has a GPL-v2-only license.
>>
>> Relicense the code in the .c
On Mon, 19 Feb 2024 at 01:23, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> docs/system/arm/raspi.rst | 11 +++
> 1 file changed, 7 insertions(+), 4 deletions(-)
Still has the typo in the commit message subject.
Otherwise
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:21, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 27 ++--
> hw/arm/raspi4b.c | 1 -
> hw/misc/bcm2838_thermal.c| 98
> hw/misc/meson.build
On Mon, 19 Feb 2024 at 01:23, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:23, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 3 +++
> include/hw/arm/bcm2838_peripherals.h | 2 ++
> include/hw/arm/raspi_platform.h | 2 +-
> 3 files changed, 6 insertions(+), 1 deletion(-)
Reviewed-
On Mon, 19 Feb 2024 at 01:18, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:20, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 167 ++-
> hw/arm/trace-events | 3 +
> include/hw/arm/bcm2838.h | 2 +
> include/hw/arm/bcm2838_periphe
On Mon, 19 Feb 2024 at 01:19, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/gpio/bcm2838_gpio.c | 153 +
> hw/gpio/meson.build| 5 +-
> include/hw/gpio/bcm2838_gpio.h | 40 +
> 3 files changed, 197 insertions(+
On Mon, 19 Feb 2024 at 01:22, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838_peripherals.c | 143 +++
> include/hw/arm/bcm2838_peripherals.h | 8 ++
> 2 files changed, 151 insertions(+)
Reviewed-by: Peter Maydell
thanks
-- PM
On Mon, 19 Feb 2024 at 01:18, Sergey Kambalin wrote:
>
> Pre setup for BCM2838 introduction
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:24, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:23, Sergey Kambalin wrote:
>
> Pre-setup for raspberry pi 4 introduction
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:19, Sergey Kambalin wrote:
>
> Pre-setup for BCM2838 introduction
>
> Signed-off-by: Sergey Kambalin
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, 19 Feb 2024 at 01:20, Sergey Kambalin wrote:
>
> Signed-off-by: Sergey Kambalin
> ---
> hw/arm/bcm2838.c | 98
> hw/arm/bcm2838_peripherals.c | 72
> hw/arm/meson.build | 2 +
> include/hw/ar
Peter Maydell writes:
> The sun4v RTC device model added under commit a0e893039cf2ce0 in 2016
> was unfortunately added with a license of GPL-v3-or-later, which is
> not compatible with other QEMU code which has a GPL-v2-only license.
>
> Relicense the code in the .c and the .h file to GPL-v2-or-
This makes them a bit more visible in the TCG emulation menu rather
than hiding them away bellow the ToC limit.
Message-Id: <20240103173349.398526-43-alex.ben...@linaro.org>
Reviewed-by: Pierrick Bouvier
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
docs/devel/tcg-plugins.
We can't directly save the ephemeral imatch from argv as that memory
will get recycled.
Message-Id: <20240103173349.398526-40-alex.ben...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
contrib/plugins/execlog.c | 2 +-
1 file
From: Akihiko Odaki
These members will be used to help plugins to identify registers.
The added members in instances of GDBFeature dynamically generated by
CPUs will be filled in later changes.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-36-alex.ben...@linaro.org>
Message-Id
With the new plugin register API we can now track changes to register
values. Currently the implementation is fairly dumb which will slow
down if a large number of register values are being tracked. This
could be improved by only instrumenting instructions which mention
registers we are interested
This ensure we at least read every register the plugin API reports at
least once during the check-tcg checks.
Signed-off-by: Alex Bennée
---
tests/plugin/insn.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/tests/plugin/insn.c b/tests/plugin/insn.c
index 5fd3017c2b3.
From: Akihiko Odaki
In preparation for a change to use GDBFeature as a parameter of
gdb_register_coprocessor(), convert the internal representation of
dynamic feature from plain XML to GDBFeature.
Signed-off-by: Akihiko Odaki
Message-Id: <20240103173349.398526-29-alex.ben...@linaro.org>
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