RE: [PATCH v2 3/3] hw: Set virtio-iommu aw-bits default value on pc_q35_9.0 and arm virt

Hi Eric, >-Original Message- >From: Eric Auger >pc_q35_9.0 and arm virt > >Currently the default input range can extend to 64 bits. On x86, >when the virtio-iommu protects vfio devices, the physical iommu >may support only 39 bits. Let's set the default to 39, as done >for the intel-iommu

RE: [PATCH v2 2/3] virtio-iommu: Trace domain range limits as unsigned int

>-Original Message- >From: Eric Auger >Subject: [PATCH v2 2/3] virtio-iommu: Trace domain range limits as >unsigned int > >Use %u format to trace domain_range limits. > >Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan Thanks Zhenzhong >--- > hw/virtio/trace-events | 2 +- > 1

RE: [PATCH v2 1/3] virtio-iommu: Add an option to define the input range width

>-Original Message- >From: Eric Auger >Subject: [PATCH v2 1/3] virtio-iommu: Add an option to define the input >range width > >aw-bits is a new option that allows to set the bit width of >the input address range. This value will be used as a default for >the device config input_range.en

[PULL 08/57] target/cris: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6349148b65..163fb05d58 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -56,6 +56,11 @@ static

[PULL 43/57] target/sparc: Use i128 for FqTOs, FqTOi

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-9-richard.hender...@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 target/sparc/translate.c | 7 --- 3 files changed, 10 in

[PULL 48/57] target/sparc: Use i128 for Fdmulq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-14-richard.hender...@linaro.org> --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 8 target/sparc/translate.c | 15 --- 3 files chan

[PULL 49/57] target/sparc: Remove qt0, qt1 temporaries

These are no longer used for passing data to/from helpers. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-15-richard.hender...@linaro.org> --- target/sparc/cpu.h | 2 -- target/sparc/fop_helper.c | 3 --- targe

[PATCH] linux-user/aarch64: Add padding before __kernel_rt_sigreturn

Without this padding, an unwind through the signal handler will pick up the unwind info for the preceding syscall. This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-sta...@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/bro

[PULL 37/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BFILL

Align the operation to the 32-byte cacheline. Use 2 i128 instead of 4 i64. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-3-richard.hender...@linaro.org> --- target/sparc/translate.c | 29 ++---

[PULL 21/57] target/ppc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu_init.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 86c8031765..9931372a08 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7

[PULL 05/57] target/arm: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6a96b245f2..1f9ea622bd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -133,6 +133,11 @@ static bo

[PULL 28/57] target/sh4: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/cpu.h | 16 ++-- target/sh4/cpu.c | 16 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9c5e2b349e 100644 --- a/

[PULL 54/57] target/sparc: Split cexc and ftt from env->fsr

These two fields are adjusted by all FPop insns. Having them separate makes it easier to set without masking. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-20-richard.hender...@linaro.org> --- target/sparc/cpu.h

[PULL 46/57] target/sparc: Use i128 for FsTOq, FiTOq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-12-richard.hender...@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 target/sparc/translate.c | 9 + 3 files changed, 11

[PULL 56/57] target/sparc: Split fcc out of env->fsr

Represent each fcc field separately from the rest of fsr. This vastly simplifies floating-point comparisons. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-22-richard.hender...@linaro.org> --- target/sparc/cpu.h

[PULL 51/57] target/sparc: Split ver from env->fsr

This field is read-only. It is easier to store it separately and merge it only upon read. While we're at it, use FSR_VER_SHIFT to initialize fpu_version. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <2

[PULL 41/57] target/sparc: Use i128 for FSQRTq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-7-richard.hender...@linaro.org> --- target/sparc/helper.h | 2 +- target/sparc/fop_helper.c | 26 -- target/sparc/translate.c | 12 +++-

[PULL 45/57] target/sparc: Use i128 for FCMPq, FCMPEq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-11-richard.hender...@linaro.org> --- target/sparc/helper.h | 16 ++-- target/sparc/fop_helper.c | 23 + target/sparc/translate.c | 54 ++

[PULL 42/57] target/sparc: Use i128 for FADDq, FSUBq, FMULq, FDIVq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-8-richard.hender...@linaro.org> --- target/sparc/helper.h | 12 +--- target/sparc/fop_helper.c | 29 ++--- target/sparc/translate.c | 13

[PULL 57/57] target/sparc: Remove FSR_FTT_NMASK, FSR_FTT_CEXC_NMASK

These macros are no longer used. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-23-richard.hender...@linaro.org> --- target/sparc/cpu.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/target/sparc/cpu.h b/targ

[PULL 53/57] target/sparc: Merge check_ieee_exceptions with FPop helpers

If an exception is to be raised, the destination fp register should be unmodified. The current implementation is incorrect, in that double results will be written back before calling gen_helper_check_ieee_exceptions, despite the placement of gen_store_fpr_D, since gen_dest_fpr_D returns cpu_fpr[].

[PULL 44/57] target/sparc: Use i128 for FqTOd, FqTOx

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-10-richard.hender...@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 target/sparc/translate.c | 7 --- 3 files changed, 10 i

[PULL 33/57] include/exec: Change cpu_mmu_index argument to CPUState

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-all.h| 2 +- include/exec/cpu-common.h | 3 +-- target/sparc/cpu.h| 2 +- accel/tcg/cputlb.c| 22 +--- semihosting/uaccess.c |

[PULL 47/57] target/sparc: Use i128 for FdTOq, FxTOq

Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-13-richard.hender...@linaro.org> --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 target/sparc/translate.c | 9 + 3 files changed, 11

[PULL 34/57] tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test

From: Ilya Leoshkevich The `if not probe_proc_self_mem` check never passes, because probe_proc_self_mem is a function object, which is a truthy value. Add parentheses in order to perform a function call. Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test") Signed-off-by: Ilya Leoshk

[PULL 52/57] target/sparc: Clear cexc and ftt in do_check_ieee_exceptions

Don't do the clearing explicitly before each FPop, rather do it as part of the rest of exception handling. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-18-richard.hender...@linaro.org> --- target/sparc/fop_helper.c |

[PULL 36/57] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for ASI_M_BCOPY

Align the operation to the 32-byte cacheline. Use 2 pair of i128 instead of 8 pair of i32. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-2-richard.hender...@linaro.org> --- target/sparc/translate.c | 43 +++

[PULL 55/57] target/sparc: Remove cpu_fsr

Drop this field as a tcg global, loading it explicitly in the few places required. This means that all FPop helpers may once again be TCG_CALL_NO_WG. Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-21-richard.hender...@l

[PULL 15/57] target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill

Rather than adjust env->hflags so that the value computed by cpu_mmu_index() changes, compute the mmu_idx that we want directly and pass it down. Introduce symbolic constants for MMU_{KERNEL,ERL}_IDX. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/cpu.h

[PULL 25/57] target/rx: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/rx/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 353132dac2..5205167da1 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -64,6 +64,11 @@ static bool rx_c

[PULL 20/57] target/ppc: Split out ppc_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu.h| 7 ++- target/ppc/cpu_init.c | 2 +- target/ppc/mem_helper.c | 10 +- target/ppc/mmu_common.c | 4 ++-- 4 files changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/c

[PULL 40/57] target/sparc: Inline FNEG, FABS

These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-6-richard.hender...@linaro.org> ---

[PULL 27/57] target/s390x: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7f123863dc..49a2341acc 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -142,6 +142,11 @@

[PULL 39/57] target/sparc: Introduce gen_{load,store}_fpr_Q

Use them for trans_FMOVq. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-5-richard.hender...@linaro.org> --- target/sparc/translate.c | 25 +++-- 1 file changed,

[PULL 06/57] target/avr: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/cpu.h | 4 +--- target/avr/cpu.c | 6 ++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..4595c6bb18 100644 --- a/target/avr/cpu.h +++ b/tar

[PULL 10/57] target/i386: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/i386/cpu.h | 13 ++--- target/i386/cpu.c | 10 ++ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..62bdb02378 100644 --- a/target

[PULL 50/57] target/sparc: Introduce cpu_get_fsr, cpu_put_fsr

Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-16-richard.hender...@linaro.org> --- target/sparc/cpu.h | 4 +++- target/sparc/helper.h | 1 + linux-user/sparc/cpu_loo

[PULL 30/57] target/tricore: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/tricore/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index e6d91c74b5..74e8a22b86 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -89,6 +

[PULL 31/57] target/xtensa: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/xtensa/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 62020b1f33..79f91819df 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -74,6 +74,11

[PULL 38/57] target/sparc: Remove gen_dest_fpr_F

Replace with tcg_temp_new_i32. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Message-Id: <20231103173841.33651-4-richard.hender...@linaro.org> --- target/sparc/translate.c | 17 ++--- 1 file changed, 6 i

[PULL 26/57] target/s390x: Split out s390x_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/cpu.h| 4 +++- target/s390x/tcg/mem_helper.c | 34 ++ 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index

[PULL 16/57] target/mips: Split out mips_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/cpu.h | 7 ++- target/mips/sysemu/physaddr.c | 2 +- target/mips/tcg/msa_helper.c| 10 +- target/mips/tcg/sysemu/cp0_helper.c | 2 +- target/mips/tc

[PULL 24/57] target/riscv: Populate CPUClass.mmu_index

Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbfc7e781..be21fa09c6 100644 --- a/target/riscv/cpu.c +++ b/target/r

[PULL 23/57] target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

Use the target-specific function name in preference to the generic name. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c| 4 ++-- target/riscv/op_helper.c | 4 ++-- target/riscv/vector_helper.c | 9 +--

[PULL 00/57] tcg patch queue

The following changes since commit 14639717bf379480e937716fcaf1e72b47fd4c5f: Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into staging (2024-01-31 19:53:45 +) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240202 for you

[PULL 13/57] target/m68k: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 44000f5869..8a8392e694 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -56,6 +56,11 @@ static

[PULL 29/57] target/sparc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 34 ++ target/sparc/cpu.c | 29 + 2 files changed, 35 insertions(+), 28 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h ind

[PULL 18/57] target/nios2: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 12 ++-- target/nios2/cpu.c | 7 +++ 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..9965ff74c1 100644 --- a/target

[PULL 19/57] target/openrisc: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/openrisc/cpu.h | 10 ++ target/openrisc/cpu.c | 13 + 2 files changed, 15 insertions(+), 8 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..7dbed8d8be 100

[PULL 17/57] target/mips: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index df544ab39b..d644adbc77 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -182,6 +182,11 @@ stat

[PULL 35/57] tcg/loongarch64: Set vector registers call clobbered

Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec op

[PULL 02/57] target/alpha: Split out alpha_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu.h | 7 ++- target/alpha/translate.c | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..3beff2738a 100644 --- a/target/

[PULL 11/57] target/loongarch: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 6 ++ target/loongarch/cpu.c | 11 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..5dfcfeb3a4 10064

[PULL 07/57] target/cris: Cache mem_index in DisasContext

Compute this value once for each translation. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/cris/translate.c | 14 +- target/cris/translate_v10.c.inc | 6 ++ 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/target/cris/tr

[PULL 22/57] target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index

Free up the riscv_cpu_mmu_index name for other usage; emphasize that the argument is 'env'. Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/riscv/cpu.h| 4 ++-- target/riscv/cpu_helper.c | 2 +- 2 files changed, 3 insertions

[PULL 12/57] target/loongarch: Rename MMU_IDX_*

The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 8 target/loongarch/cpu.c | 2 +- target/lo

[PULL 03/57] target/alpha: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/alpha/cpu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index de705c3703..bf70173a25 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -64,6 +64,11 @@ s

[PULL 32/57] include/exec: Implement cpu_mmu_index generically

For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-all.h| 4 include/exec/cpu-common.h | 22 ++ target/alpha/cpu.h| 5 - target/arm/cp

[PULL 14/57] target/microblaze: Populate CPUClass.mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 13 ++--- target/microblaze/cpu.c | 18 +- 2 files changed, 19 insertions(+), 12 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f

[PULL 01/57] include/hw/core: Add mmu_index to CPUClass

To be used after all targets have populated the hook. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2c284d6397..4385ce54c9 100644 --- a/inc

[PULL 04/57] target/arm: Split out arm_env_mmu_index

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 + target/arm/helper.c | 2 +- target/arm/tcg/helper-a64.c | 4 ++-- target/arm/tcg/mte_helper.c | 18 +- target/arm/tcg/sve_helper.c | 8 target/arm/

[PULL 09/57] target/hppa: Populate CPUClass.mmu_index

Reviewed-by: Helge Deller Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 7 ++- target/hppa/cpu.c | 12 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..04439f2

Re: [PATCH 00/22] target/sparc: floating-point cleanup

On 2/1/24 07:49, Mark Cave-Ayland wrote: I'm happy for you to take this via tcg-next if that's easiest for you. Yes, I can do that. r~

Re: [PATCH 05/22] target/sparc: Inline FNEG, FABS

On 1/30/24 18:40, Philippe Mathieu-Daudé wrote: Hi Richard, On 3/11/23 18:38, Richard Henderson wrote: These are simple bit manipulation insns. Begin using i128 for float128. Implement FMOVq with do_qq. Signed-off-by: Richard Henderson ---   target/sparc/helper.h |  6   target/sparc/

Re: [PULL 02/10] hw/hppa/machine: Disable default devices with --nodefaults option

Hi, On Sat, Jan 13, 2024 at 06:57:20AM +0100, del...@kernel.org wrote: > From: Helge Deller > > Recognize the qemu --nodefaults option, which will disable the > following default devices on hppa: > - lsi53c895a SCSI controller, > - artist graphics card, > - LASI 82596 NIC, > - tulip PCI NIC, > -

Re: [PATCH] tests/tcg: Fix the /proc/self/mem probing in the PROT_NONE gdbstub test

On 2/1/24 08:02, Ilya Leoshkevich wrote: The `if not probe_proc_self_mem` check never passes, because probe_proc_self_mem is a function object, which is a truthy value. Add parentheses in order to perform a function call. Fixes: dc84d50a7f9b ("tests/tcg: Add the PROT_NONE gdbstub test") Signed-o

Re: [PATCH 13/14] migration/multifd: Move header prepare/fill into send_prepare()

On Wed, Jan 31, 2024 at 06:31:10PM +0800, pet...@redhat.com wrote: > From: Peter Xu > > This patch redefines the interfacing of ->send_prepare(). It further > simplifies multifd_send_thread() especially on zero copy. > > Now with the new interface, we require the hook to do all the work for > p

[PATCH] linux-user/aarch64: Add padding before __kernel_rt_sigreturn

Without this padding, an unwind through the signal handler will pick up the unwind info for the preceding syscall. This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-sta...@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/bro

Re: [PATCH v3] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit

On Wed, Jan 31, 2024 at 10:37 PM Vadim Shakirov wrote: > > mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit > by privileged spec > > Signed-off-by: Vadim Shakirov Do you mind rebasing this on https://github.com/alistair23/qemu/tree/riscv-to-apply.next ? Alistair > ---

Re: [PATCH v3] target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit

On Wed, Jan 31, 2024 at 10:37 PM Vadim Shakirov wrote: > > mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit > by privileged spec > > Signed-off-by: Vadim Shakirov Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.h | 8 > target/riscv/mac

Re: [PATCH 3/6] target/riscv: add remaining named features

On Thu, Feb 1, 2024 at 5:15 AM Daniel Henrique Barboza wrote: > > > > On 1/29/24 22:10, Alistair Francis wrote: > > On Fri, Jan 26, 2024 at 5:54 AM Daniel Henrique Barboza > > wrote: > >> > >> The RVA22U64 and RVA22S64 profiles mandates certain extensions that, > >> until now, we were implying th

Re: [PATCH 00/14] migration/multifd: Refactor ->send_prepare() and cleanups

On Thu, Feb 01, 2024 at 06:46:35PM -0300, Fabiano Rosas wrote: > Avihai Horon writes: > > > On 01/02/2024 7:47, Peter Xu wrote: > >> External email: Use caution opening links or attachments > >> > >> > >> On Wed, Jan 31, 2024 at 07:49:51PM -0300, Fabiano Rosas wrote: > >>> pet...@redhat.com write

Re: [PATCH] RISC-V: Report the QEMU vendor/arch IDs on virtual CPUs

On Thu, Feb 1, 2024 at 5:33 AM Palmer Dabbelt wrote: > > Right now we just report 0 for marchid/mvendorid in QEMU. That's legal, > but it's tricky for users that want to check if they're running on QEMU > to do so. This sets marchid to 42, which I've proposed as the QEMU > architecture ID (mvend

Re: [PATCH v6 0/6] Pointer Masking update for Zjpm v0.8

On Fri, Feb 2, 2024 at 1:11 AM Alexey Baturo wrote: > > From: Alexey Baturo > > Hi, > > This patch series is rebased on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks! Applied to riscv-to-apply.next Alistair > > Thanks > > [v5]: > This patch series targets Zjpm v0.8 ext

Re: [PATCH] tcg/loongarch64: Set vector registers call clobbered

在 2024/2/2 上午7:34, Richard Henderson 写道: Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-sta...@nongnu.org Fixes: 16288ded94

Re: [PATCH 04/14] migration/multifd: Postpone reset of MultiFDPages_t

On Fri, Feb 02, 2024 at 08:28:47AM +0800, Peter Xu wrote: > > Pages allocated is nonsense. See if you agree with its removal: > > https://gitlab.com/farosas/qemu/-/commit/7cfff1a3e31b271e901a6c08d8b5d8c01b680e4d > > > > --- > > From 7cfff1a3e31b271e901a6c08d8b5d8c01b680e4d Mon Sep 17 00:00:00 2001

Re: [PATCH 04/14] migration/multifd: Postpone reset of MultiFDPages_t

On Thu, Feb 01, 2024 at 12:21:27PM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > > On Wed, Jan 31, 2024 at 12:27:51PM -0300, Fabiano Rosas wrote: > >> > +/* Reset a MultiFDPages_t* object for the next use */ > >> > +static void multifd_pages_reset(MultiFDPages_t *pages) > >> > +{ > >> > +

Re: [PATCH 03/14] migration/multifd: Drop MultiFDSendParams.quit, cleanup error paths

On Thu, Feb 01, 2024 at 10:30:19AM -0300, Fabiano Rosas wrote: > > @@ -586,7 +595,7 @@ void multifd_save_cleanup(void) > > if (!migrate_multifd()) { > > return; > > } > > -multifd_send_terminate_threads(NULL); > > +multifd_send_terminate_threads(); > > for (i = 0; i

Re: [PATCH] hw/pci: migration: Skip config space check for vendor specific capability during restore/load

On Thu, 1 Feb 2024 13:10:48 -0500 "Michael S. Tsirkin" wrote: > On Thu, Feb 01, 2024 at 11:08:58PM +0530, Vinayak Kale wrote: > > > > On 31/01/24 11:08 pm, Alex Williamson wrote: > > > > > > On Wed, 31 Jan 2024 15:22:59 +0530 > > > Vinayak Kale wrote: > > > > > > > On 31/01/24 12:28 am, A

Re: [PULL 06/15] tests/qtest/migration: Don't use -cpu max for aarch64

Fabiano, I think you forgot to reply-to-all.. adding back the list and people in the loop. On Thu, Feb 01, 2024 at 10:12:44AM -0300, Fabiano Rosas wrote: > Peter Xu writes: > > > On Wed, Jan 31, 2024 at 10:09:16AM -0300, Fabiano Rosas wrote: > >> If we ask for KVM and it falls back to TCG, we ne

[PATCH] tcg/loongarch64: Set vector registers call clobbered

Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-sta...@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec op

Re: [External] Re: [PATCH v3 03/20] multifd: Zero pages transmission

On Wed, Jan 31, 2024 at 9:22 PM Peter Xu wrote: > > On Thu, Jan 04, 2024 at 12:44:35AM +, Hao Xiang wrote: > > From: Juan Quintela > > > > This implements the zero page dection and handling. > > > > Signed-off-by: Juan Quintela > > --- > > migration/multifd.c | 41 ++

Re: [External] Re: [PATCH v3 15/20] migration/multifd: Add test hook to set normal page ratio.

On Wed, Jan 31, 2024 at 9:24 PM Peter Xu wrote: > > On Thu, Jan 04, 2024 at 12:44:47AM +, Hao Xiang wrote: > > +# @multifd-normal-page-ratio: Test hook setting the normal page ratio. > > +# (Since 8.2) > > Please remember to touch all of them to 9.0 when repost, thanks. > Will do. > -- >

[PATCH v3 07/20] qapi/schema: adjust type narrowing for mypy's benefit

We already take care to perform some type narrowing for arg_type and ret_type, but not in a way where mypy can utilize the result once we add type hints, e.g.: qapi/schema.py:833: error: Incompatible types in assignment (expression has type "QAPISchemaType", variable has type "Optional[QAPISchemaO

[PATCH v3 14/20] qapi/schema: Don't initialize "members" with `None`

Declare, but don't initialize the "members" field with type List[QAPISchemaObjectTypeMember]. This simplifies the typing from what would otherwise be Optional[List[T]] to merely List[T]. This removes the need to add assertions to several callsites that this value is not None - which it never will

[PATCH v3 06/20] qapi/schema: make c_type() and json_type() abstract methods

These methods should always return a str, it's only the default abstract implementation that doesn't. They can be marked "abstract", which requires subclasses to override the method with the proper return type. Signed-off-by: John Snow --- scripts/qapi/schema.py | 5 - 1 file changed, 4 inse

[PATCH v3 12/20] qapi/schema: assert info is present when necessary

QAPISchemaInfo arguments can often be None because built-in definitions don't have such information. The type hint can only be Optional[QAPISchemaInfo] then. But, mypy gets upset about all the places where we exploit that it can't actually be None there. Add assertions that will help mypy over t

[PATCH v3 02/20] qapi/schema: add pylint suppressions

With this patch, pylint is happy with the file, so enable it in the configuration. Signed-off-by: John Snow Reviewed-by: Markus Armbruster --- scripts/qapi/pylintrc | 5 - scripts/qapi/schema.py | 5 + 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/scripts/qapi/pylintrc

[PATCH v3 09/20] qapi/schema: assert resolve_type has 'info' and 'what' args on error

resolve_type() is generally used to resolve configuration-provided type names into type objects, and generally requires valid 'info' and 'what' parameters. In some cases, such as with QAPISchemaArrayType.check(), resolve_type may be used to resolve built-in types and as such will not have an 'info

[PATCH v3 19/20] qapi/schema: turn on mypy strictness

This patch can be rolled in with the previous one once the series is ready for merge, but for work-in-progress' sake, it's separate here. Signed-off-by: John Snow --- scripts/qapi/mypy.ini | 5 - 1 file changed, 5 deletions(-) diff --git a/scripts/qapi/mypy.ini b/scripts/qapi/mypy.ini index

[PATCH v3 04/20] qapi/schema: declare type for QAPISchemaObjectTypeMember.type

A QAPISchemaObjectTypeMember's type gets resolved only during .check(). We have QAPISchemaObjectTypeMember.__init__() initialize self.type = None, and .check() assign the actual type. Using .type before .check() is wrong, and hopefully crashes due to the value being None. Works. However, it make

[PATCH v3 15/20] qapi/schema: fix typing for QAPISchemaVariants.tag_member

There are two related changes here: (1) We need to perform type narrowing for resolving the type of tag_member during check(), and (2) tag_member is a delayed initialization field, but we can hide it behind a property that raises an Exception if it's called too early. This simplifies

[PATCH v3 13/20] qapi/schema: split "checked" field into "checking" and "checked"

Instead of using the None value for the members field, use a dedicated "checking" value to detect recursive misconfigurations. This is intended to assist with subsequent patches which will seek to remove the "None" value from the members field (which can never be set legally after the final call t

[PATCH v3 01/20] qapi: sort pylint suppressions

Suggested-by: Markus Armbruster Signed-off-by: John Snow --- scripts/qapi/pylintrc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/scripts/qapi/pylintrc b/scripts/qapi/pylintrc index 90546df5345..1342412c3cf 100644 --- a/scripts/qapi/pylintrc +++ b/scripts/qapi/pylintrc

[PATCH v3 18/20] qapi/schema: add type hints

This patch only adds type hints, which aren't utilized at runtime and don't change the behavior of this module in any way. In a scant few locations, type hints are removed where no longer necessary due to inference power from typing all of the rest of creation; and any type hints that no longer ne

[PATCH v3 05/20] qapi/schema: declare type for QAPISchemaArrayType.element_type

A QAPISchemaArrayType's element type gets resolved only during .check(). We have QAPISchemaArrayType.__init__() initialize self.element_type = None, and .check() assign the actual type. Using .element_type before .check() is wrong, and hopefully crashes due to the value being None. Works. However

[PATCH v3 20/20] qapi/schema: remove unnecessary asserts

With strict typing enabled, these runtime statements aren't necessary anymore; we can prove them statically. Signed-off-by: John Snow --- scripts/qapi/schema.py | 25 - 1 file changed, 25 deletions(-) diff --git a/scripts/qapi/schema.py b/scripts/qapi/schema.py index 319

[PATCH v3 03/20] qapi: create QAPISchemaDefinition

Include entities don't have names, but we generally expect "entities" to have names. Reclassify all entities with names as *definitions*, leaving the nameless include entities as QAPISchemaEntity instances. This is primarily to help simplify typing around expectations of what callers expect for pr

[PATCH v3 11/20] qapi/schema: fix QAPISchemaArrayType.check's call to resolve_type

Adjust the expression at the callsite to work around mypy's weak type introspection that believes this expression can resolve to QAPISourceInfo; it cannot. (Fundamentally: self.info only resolves to false in a boolean expression when it is None; therefore this expression may only ever produce Opti

[PATCH v3 10/20] qapi: use schema.resolve_type instead of schema.lookup_type

the function lookup_type() is capable of returning None, but some callers aren't prepared for that and assume it will always succeed. For static type analysis purposes, this creates problems at those callsites. Modify resolve_type() - which already cannot ever return None - to allow 'info' and 'wh

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