Am Wed, 27 Dec 2023 21:02:12 +
schrieb Mark Cave-Ayland :
> There is no need to dynamically allocate the memory region from the heap.
>
> Signed-off-by: Mark Cave-Ayland
> ---
> hw/m68k/q800.c | 7 +++
> include/hw/m68k/q800.h | 1 +
> 2 files changed, 4 insertions(+), 4 deletio
在 2023/12/27 下午4:52, Philippe Mathieu-Daudé 写道:
Hi,
On 27/12/23 09:08, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 71 -
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
在 2023/12/27 下午4:49, Philippe Mathieu-Daudé 写道:
Hi,
On 27/12/23 09:08, Song Gao wrote:
Add init_cmline and set boot_info->a0, a1
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 20
target/loongarch/cpu.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/hw
在 2023/12/27 下午5:02, Philippe Mathieu-Daudé 写道:
Hi,
On 27/12/23 09:08, Song Gao wrote:
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
drivers/irqchip/irq-loongson-eiointc.c
Better reference a fixed commit/tag, and mention Linux project.
Suggestion:
'Se
On 12/18/23 22:33, Peter Maydell wrote:
Enable FEAT_NV2 on the 'max' CPU, and stop filtering it out for
the Neoverse N2 and Neoverse V1 CPUs.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu.c | 5 -
target/arm/tcg/cpu64.c| 2 +-
On 12/18/23 22:33, Peter Maydell wrote:
We already print various lines of information when we take an
exception, including the ELR and (if relevant) the FAR. Now
that FEAT_NV means that we might report something other than
the old PSTATE to the guest as the SPSR, it's worth logging
this as well.
On 12/18/23 22:33, Peter Maydell wrote:
When interpreting CPU dumps where FEAT_NV and FEAT_NV2 are in use,
it's helpful to include the values of HCR_EL2.{NV,NV1,NV2} in the CPU
dump format, as a way of distinguishing when we are in EL1 as part of
executing guest-EL2 and when we are just in normal
On 12/18/23 22:33, Peter Maydell wrote:
Mark up the cpreginfo structs for the GIC CPU registers to indicate
the offsets from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ
in the Arm ARM.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_cpuif.c | 11 +++
1 file changed, 11 inse
On 12/18/23 22:33, Peter Maydell wrote:
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This covers all the remaining offsets at 0x200 and
above, except for the GIC ICH_* registers.
(Note that becaus
On 12/18/23 22:33, Peter Maydell wrote:
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets 0x168 to 0x1f8.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 18
On 12/18/23 22:32, Peter Maydell wrote:
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets 0x100 to 0x160.
Many (but not all) of the registers in this range have _EL12 aliases
On 12/18/23 22:32, Peter Maydell wrote:
Mark up the cpreginfo structs to indicate offsets for system
registers from VNCR_EL2, as defined in table D8-66 in rule R_CSRPQ in
the Arm ARM. This commit covers offsets below 0x100; all of these
registers are redirected to memory regardless of the value o
On 12/18/23 22:32, Peter Maydell wrote:
If FEAT_NV2 redirects a system register access to a memory offset
from VNCR_EL2, that access might fault. In this case we need to
report the correct syndrome information:
* Data Abort, from same-EL
* no ISS information
* the VNCR bit (bit 13) is set
On 12/18/23 22:32, Peter Maydell wrote:
+if (s->nv && s->nv2 && ri->nv2_redirect_offset) {
Again, s->nv test is redundant.
+/*
+ * Some registers always redirect to memory; some only do so if
+ * HCR_EL2.NV1 is 0, and some only if NV1 is 1 (these come in
+
On 12/18/23 22:32, Peter Maydell wrote:
@@ -2173,7 +2174,14 @@ static void handle_sys(DisasContext *s, bool isread,
* for registers accessible at EL1).
*/
skip_fp_access_checks = true;
-if (s->nv && arm_cpreg_traps_in_nv(ri)) {
+if (s->nv && s->nv2
On 12/18/23 22:32, Peter Maydell wrote:
With FEAT_NV2, the condition for when SPSR_EL1.M should report that
an exception was taken from EL2 changes.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/targ
On 12/18/23 22:32, Peter Maydell wrote:
For FEAT_NV2, a new system register VNCR_EL2 holds the base
address of the memory which nested-guest system register
accesses are redirected to. Implement this register.
Signed-off-by: Peter Maydell
---
target/arm/cpu.h| 3 +++
target/arm/helper.c
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV2 defines another new bit in HCR_EL2: NV2. When the
feature is enabled, allow this bit to be written in HCR_EL2.
Signed-off-by: Peter Maydell
---
target/arm/cpu-features.h | 5 +
target/arm/helper.c | 3 +++
2 files changed, 8 inserti
On 12/18/23 22:32, Peter Maydell wrote:
Enable FEAT_NV on the 'max' CPU, and stop filtering it out for the
Neoverse N2 and Neoverse V1 CPUs. We continue to downgrade FEAT_NV2
support to FEAT_NV for the latter two CPU types.
Signed-off-by: Peter Maydell
---
docs/system/arm/emulation.rst | 1 +
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,1} the handling
of some of the page table attribute bits changes for the EL1&0
translation regime:
* for block and page descriptors:
- bit [54] holds PXN, not UXN
- bit [53] is RES0, and the effecti
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV requires (per I_JKLJK) that when HCR_EL2.{NV,NV1} is {1,1} the
unprivileged-access instructions LDTR, STTR etc behave as normal
loads and stores. Implement the check that handles this.
Signed-off-by: Peter Maydell
---
target/arm/tcg/hflags.c | 6
On 12/18/23 22:32, Peter Maydell wrote:
For FEAT_NV, when HCR_EL2.{NV,NV1} is {1,1} PAN is always disabled
even when the PSTATE.PAN bit is set. Implement this by having
arm_pan_enabled() return false in this situation.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 3 +++
1 file chang
On 12/18/23 22:32, Peter Maydell wrote:
Currently the code in target/arm/helper.c mostly checks the PAN bits
in env->pstate or env->uncached_cpsr directly when it wants to know
if PAN is enabled, because in most callsites we know whether we are
in AArch64 or AArch32. We do have an arm_pan_enabled
On 12/18/23 22:32, Peter Maydell wrote:
When HCR_EL2.{NV,NV1} is {1,1} we must trap five extra registers to
EL2: VBAR_EL1, ELR_EL1, SPSR_EL1, SCXTNUM_EL1 and TFSR_EL1.
Implement these traps.
This trap does not apply when FEAT_NV2 is implemented and enabled;
include the check that HCR_EL2.NV2 is
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV requires that when HCR_EL2.{NV,NV1} == {1,0} and an exception
is taken from EL1 to EL1 then the reported EL in SPSR_EL1.M should be
EL2, not EL1. Implement this behaviour.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 6 ++
1 file
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV requires that when HCR_EL2.NV is set reads of the CurrentEL
register from EL1 always report EL2 rather than the real EL.
Implement this.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 9 +++--
1 file changed, 7 insertions(
On 12/18/23 22:32, Peter Maydell wrote:
For FEAT_NV, accesses to system registers and instructions from EL1
which would normally UNDEF there but which work in EL2 need to
instead be trapped to EL2. Detect this both for "we know this will
UNDEF at translate time" and "we found this UNDEFs at runti
On 12/18/23 22:32, Peter Maydell wrote:
In handle_sys() we don't do the check for whether the register is
marked as needing an FPU/SVE/SME access check until after we've
handled the special cases covered by ARM_CP_SPECIAL_MASK. This is
conceptually the wrong way around, because if for example we
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV and FEAT_NV2 will allow EL1 to attempt to access cpregs that
only exist at EL2. This means we're going to want to run their
accessfns when the CPU is at EL1. In almost all cases, the behaviour
we want is "the accessfn returns OK if at EL1".
Mostly
On 12/18/23 22:32, Peter Maydell wrote:
The alias registers like SCTLR_EL12 only exist when HCR_EL2.E2H
is 1; they should UNDEF otherwise. We weren't implementing this.
Add an intercept of the accessfn for these aliases, and implement
the UNDEF check.
Signed-off-by: Peter Maydell
---
target/ar
On 12/18/23 22:32, Peter Maydell wrote:
For FEAT_VHE, we define a set of register aliases, so that for instance:
* the SCTLR_EL1 either accesses the real SCTLR_EL1, or (if E2H is 1)
SCTLR_EL2
* a new SCTLR_EL12 register accesses SCTLR_EL1 if E2H is 1
However when we create the 'new_reg'
On 12/18/23 22:32, Peter Maydell wrote:
The TBFLAG_A64 TB flag bits go in flags2, which for AArch64 guests
we know is 64 bits. However at the moment we use FIELD_EX32() and
FIELD_DP32() to read and write these bits, which only works for
bits 0 to 31. Since we're about to add a flag that uses bit
On 12/18/23 22:32, Peter Maydell wrote:
The HCR_EL2.TSC trap for trapping EL1 execution of SMC instructions
has a behaviour change for FEAT_NV when EL3 is not implemented:
* in older architecture versions TSC was required to have no
effect (i.e. the SMC insn UNDEFs)
* with FEAT_NV, when
On 12/18/23 22:32, Peter Maydell wrote:
When FEAT_NV is turned on via the HCR_EL2.NV bit, ERET instructions
are trapped, with the same syndrome information as for the existing
FEAT_FGT fine-grained trap (in the pseudocode this is handled in
AArch64.CheckForEretTrap()).
Rename the DisasContext an
On 12/18/23 22:32, Peter Maydell wrote:
The FEAT_NV HCR_EL2.AT bit enables trapping of some address
translation instructions from EL1 to EL2. Implement this behaviour.
Signed-off-by: Peter Maydell
---
target/arm/helper.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletio
On 12/18/23 22:32, Peter Maydell wrote:
FEAT_NV defines three new bits in HCR_EL2: NV, NV1 and AT. When the
feature is enabled, allow these bits to be written, and flush the
TLBs for the bits which affect page table interpretation.
Signed-off-by: Peter Maydell
---
target/arm/cpu-features.h |
On 12/18/23 22:32, Peter Maydell wrote:
The hypervisor can deliver (virtual) LPIs to a guest by setting up a
list register to have an intid which is an LPI. The GIC has to treat
these a little differently to standard interrupt IDs, because LPIs
have no Active state, and so the guest will only EO
On 12/18/23 22:32, Peter Maydell wrote:
The CTR_EL0 register has some bits which allow the implementation to
tell the guest that it does not need to do cache maintenance for
data-to-instruction coherence and instruction-to-data coherence.
QEMU doesn't emulate caches and so our cache maintenance i
On 12/27/23 02:04, Philippe Mathieu-Daudé wrote:
Some header and source file names use common prefix / suffix
but we never really ruled a convention. Start doing so with
the current patterns from the tree.
Suggested-by: Alex Bennée
Signed-off-by: Philippe Mathieu-Daudé
---
docs/devel/style.r
There is no need to dynamically allocate the memory region from the heap.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 7 +++
include/hw/m68k/q800.h | 1 +
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 83d1571d02..b80a3b6
On 12/7/23 21:54, Philippe Mathieu-Daudé wrote:
Extract helper_load_pcc() to clk_helper.c so we can
restrict sys_helper.c to system emulation.
Philippe Mathieu-Daudé (2):
target/alpha: Extract clk_helper.c from sys_helper.c
target/alpha: Only build sys_helper.c on system emulation
Review
On Wed, Dec 27, 2023 at 05:26:30PM +0100, Uwe Kleine-König wrote:
> The .remove() callback for a platform driver returns an int which makes
> many driver authors wrongly assume it's possible to do error handling by
> returning an error code. However the value returned is ignored (apart
> from emitt
On 12/22/23 00:43, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
tcg/i386/tcg-target.c.inc | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index a83f8aab304..4e9f372d4fd 100644
--- a/tcg/i386/tcg-target.c.i
On 26/12/2023 12:08, Philippe Mathieu-Daudé wrote:
Cc'ing Mark for the logical change (should we rather assert?).
On 18/12/23 16:02, Alexandra Diupina wrote:
Add a 'current_lun' check for a null value
to avoid null pointer dereferencing
Found by Linux Verification Center (linuxtesting.org) wi
On 21/12/2023 12:29, Thomas Huth wrote:
There's no need to explicitely allocate the memory here, we can
simply embed it into the m5206_mbar_state instead.
Signed-off-by: Thomas Huth
---
hw/m68k/mcf5206.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git
Am 27.12.23 um 10:12 schrieb Philippe Mathieu-Daudé:
On 27/12/23 10:09, Michael Tokarev wrote:
27.12.2023 11:59, Philippe Mathieu-Daudé:
Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email")
corrected authorship for patch received at qemu-devel@nongnu.org,
correct now for patch received
On 27/12/23 17:26, Uwe Kleine-König wrote:
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typic
Hello,
this series converts all platform drivers below drivers/firmware that
make use of .remove() to use .remove_new() instead.
See commit 5c5a7680e67b ("platform: Provide a remove callback that
returns no value") for an extended explanation and the eventual goal.
The TL;DR; is to make it harder
The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is ignored (apart
from emitting a warning) and this typically results in resource leaks.
To improve h
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On Wed, Dec 27, 2023 at 06:03:46PM +0700, Bui Quang Minh wrote:
> On 12/26/23 16:21, Michael S. Tsirkin wrote:
> > On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
> > > Hi everyone,
> > >
> > > This series implements x2APIC mode in userspace local APIC and the
> > > RDMSR/WRMSR hel
Enable CPU cluster support on SbsaQemu platform, so that users can
specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this
topology can be passed to the firmware through DT cpu-map.
xiongyining1480 (2):
hw/arm/sbsa-ref:Enable CPU cluster on ARM sbsa machine
hw/arm/sbsa-ref: Ad
From: xiongyining1480
Enable the CPU cluster on ARM sbsa machine, so user can configure the
cluster hierarchy.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
hw/arm/sbsa-ref.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index f3c9704693
From: xiongyining1480
Support CPU topology description through device tree.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
hw/arm/sbsa-ref.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index e6cd612b
For those encountered this problem:
This is not a bug. Instead, it is the exepected behaviour.
Refer to:
https://github.com/virtio-win/kvm-guest-drivers-windows/issues/1017
** Bug watch added: github.com/virtio-win/kvm-guest-drivers-windows/issues #1017
https://github.com/virtio-win/kvm-guest-d
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any
user-visible changes.
signature.asc
Description: PGP signature
On 12/22/23 09:22, Daniel Henrique Barboza wrote:
The same rework did in 'priv_spec' is done for 'vext_spec'. This time is
simpler, since we only accept one value ("v1.0") and we'll always have
env->vext_ver set to VEXT_VERSION_1_00_0, thus we don't need helpers to
convert string to 'vext_ver'
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to su
From: Carlos Santos
It is not useful when configuring with --enable-trace-backends=nop.
Signed-off-by: Carlos Santos
Signed-off-by: Stefan Hajnoczi
Message-ID: <20230408010410.281263-1-casan...@redhat.com>
---
trace/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
The following changes since commit 455f4440687fcee03e62d9b17b28162b638458af:
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging (2023-12-26 06:07:16 -0500)
are available in the Git repository at:
https://gitlab.com/stefanha/qemu.git tags/tracing-pull-r
Hi Markus, Kevin,
On 18/12/23 08:26, Markus Armbruster wrote:
Peter Maydell writes:
On Thu, 14 Dec 2023 at 17:14, Philippe Mathieu-Daudé wrote:
QOM properties are added on the ARM vCPU object when a
feature is present. Rather than checking the property
is present, check the feature.
Sugge
27.12.2023 12:21, Philippe Mathieu-Daudé wrote:
..
A more useful use of our time would be a git pre-merge hook on
our CI, but that won't work because PR aren't merged on the CI
but externally, and the final commit is pushed.
The only place I can think of to automate that is to have a
script on t
On 27/12/23 10:12, Philippe Mathieu-Daudé wrote:
On 27/12/23 10:09, Michael Tokarev wrote:
27.12.2023 11:59, Philippe Mathieu-Daudé:
Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email")
corrected authorship for patch received at qemu-devel@nongnu.org,
correct now for patch received at qe
On 27/12/23 10:09, Michael Tokarev wrote:
27.12.2023 11:59, Philippe Mathieu-Daudé:
Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email")
corrected authorship for patch received at qemu-devel@nongnu.org,
correct now for patch received at qemu-triv...@nongnu.org.
Fixes: d819fc9516 ("virtio
27.12.2023 11:59, Philippe Mathieu-Daudé:
Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email")
corrected authorship for patch received at qemu-devel@nongnu.org,
correct now for patch received at qemu-triv...@nongnu.org.
Fixes: d819fc9516 ("virtio-blk: Fix potential nullptr read access")
Hi,
On 27/12/23 08:12, Zhao Liu wrote:
Hi Philippe,
On Tue, Dec 26, 2023 at 04:04:41PM +0100, Philippe Mathieu-Daudé wrote:
Date: Tue, 26 Dec 2023 16:04:41 +0100
From: Philippe Mathieu-Daudé
Subject: [PATCH] docs/devel: Document conventional file prefixes and
suffixes
X-Mailer: git-send-ema
Hi,
On 27/12/23 09:08, Song Gao wrote:
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
drivers/irqchip/irq-loongson-eiointc.c
Better reference a fixed commit/tag, and mention Linux project.
Suggestion:
'See
https://github.com/torvalds/linux/blob/v6.6/dr
Commit 5204b499a6 ("mailmap: Fix Stefan Weil author email")
corrected authorship for patch received at qemu-devel@nongnu.org,
correct now for patch received at qemu-triv...@nongnu.org.
Fixes: d819fc9516 ("virtio-blk: Fix potential nullptr read access")
Signed-off-by: Philippe Mathieu-Daudé
---
.
Hi,
On 27/12/23 09:08, Song Gao wrote:
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 71 -
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 3075c276d4..faff880153 100644
--- a/hw/loon
Hi,
On 27/12/23 09:08, Song Gao wrote:
Add init_cmline and set boot_info->a0, a1
Signed-off-by: Song Gao
---
hw/loongarch/boot.c| 20
target/loongarch/cpu.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index faf
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 24 ++--
include/hw/loongarch/boot.h | 9 +
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 4103fb2781..387602d669 100644
--- a/hw/loongarch/boot.
rtc node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 04ce6a95aa..9b82b59263 100644
--- a/hw/loongarch/virt.c
+++ b/hw/l
fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'.
See:
drivers/irqchip/irq-loongson-pch-msi.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 33 -
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 33 insertions(+), 1 deletion(-)
diff --gi
uart node need interrupts and interrupt-parent cells.
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e839efa097..04ce6a95aa 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loon
Add init_systab and set boot_info->a2
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 22 +
include/hw/loongarch/boot.h | 48 +
2 files changed, 70 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 27eae6f0cb
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 71 -
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 3075c276d4..faff880153 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -1
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 40 +
hw/loongarch/virt.c | 11 ++
include/hw/loongarch/boot.h | 27 +
include/hw/loongarch/virt.h | 11 ++
4 files changed, 80 insertions(+), 9 deletions(
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 73 ++---
1 file changed, 69 insertions(+), 4 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 3b300187b2..f12791036c 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -
fdt adds Extend I/O Interrupt Controller,
we use 'loongson,ls2k2000-eiointc'.
See:
drivers/irqchip/irq-loongson-eiointc.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 30 +-
include/hw/intc/loongarch_extioi.h | 1 +
2 files changed, 30 insertio
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 11 +++
include/hw/loongarch/boot.h | 4
2 files changed, 15 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 387602d669..087cb850b2 100644
--- a/hw/loongarch/boot.c
+++ b/hw/loongarch/boot.c
@@ -11
The right fdt memory node like [1], not [2]
[1]
memory@0 {
device_type = "memory";
reg = <0x00 0x00 0x00 0x1000>;
};
[2]
memory@0 {
device_type = "memory";
reg = <0x02 0x00 0x02 0x1000>;
};
fdt adds pch pic controller, we use 'loongson,pch-pic-1.0'
See:
drivers/irqchip/irq-loongson-pch-pic.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c| 30 +-
include/hw/pci-host/ls7a.h | 1 +
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 31 +--
1 file changed, 1 insertion(+), 30 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index f12791036c..e839efa097 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -410,34 +410,6 @
we load initrd ramdisk after kernel_high address
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 29 -
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index 0f2bc15fdf..3075c276d4 100644
--- a/hw/loongarch/boot
Hi, All
We already support boot efi kernel with bios, but not support boot elf kernel.
This series adds boot elf kernel with FDT.
'LoongArch supports ACPI and FDT. The information that needs to be passed
to the kernel includes the memmap, the initrd, the command line, optionally
the ACPI/FDT ta
Move some boot functions to boot.c and struct
loongarch_boot_info into struct LoongArchMachineState.
Signed-off-by: Song Gao
---
hw/loongarch/boot.c | 125
hw/loongarch/meson.build| 1 +
hw/loongarch/virt.c | 123 +++-
Add init_cmline and set boot_info->a0, a1
Signed-off-by: Song Gao
---
hw/loongarch/boot.c| 20
target/loongarch/cpu.h | 2 ++
2 files changed, 22 insertions(+)
diff --git a/hw/loongarch/boot.c b/hw/loongarch/boot.c
index faff880153..27eae6f0cb 100644
--- a/hw/loongarch
fdt adds cpu interrupt controller node,
we use 'loongson,cpu-interrupt-controller'.
See:
drivers/irqchip/irq-loongarch-cpu.c
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
ind
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