On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
When an Error** reference is available, it is better to
propagate local errors, rather then using generic ones,
which might terminate the whole QEMU process.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/pci-host/raven.c | 6 --
1 file
Initialize the machine specific max_cpus limit to a usable limit 4096.
Keeping between 4096 to 8192 will throw IRQ not free error due to XIVE
limitation and keeping beyond 8192 will hit assert in tcg_region_init
or spapr_xive_claim_irq.
Logs:
Without patch fix:
[root@host build]# qemu-system-ppc
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, arg5, arg6, errp;
@@
- memory_region_init_rom_device(mr, owner, arg3, arg4, arg5, arg6, &errp);
if (
- errp
+ !memory_region_in
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, arg5, arg6, arg7, errp;
@@
- memory_region_init_ram_from_fd(mr, owner, arg3, arg4, arg5, arg6, arg7,
&errp);
if (
- errp
+ !me
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, errp;
@@
- memory_region_init_rom(mr, owner, arg3, arg4, &errp);
if (
- errp
+ !memory_region_init_rom(mr, owner, arg3, arg4, &
Adding Reza.
On 11/21/23 21:03, Miles Glenn wrote:
On Tue, 2023-11-21 at 19:36 +0100, Cédric Le Goater wrote:
On 11/21/23 00:51, Glenn Miles wrote:
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time a
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, errp;
@@
- memory_region_init_ram(mr, owner, arg3, arg4, &errp);
if (
- errp
+ !memory_region_init_ram(mr, owner, arg3, arg4, &
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
Commit message missing but indeed there's not much to say
Reviewed-by: Manos Pitsidianakis
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Reduce the &local_err variable use and remove the 'out:' label.
Signed-off-by: Philippe Mathieu-Daudé
---
backends/hostmem.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/backends/hostmem.c b/backends/hostmem
Extend the existing watchpoint facility from TCG DAWR0 emulation
to DAWR1 on POWER10.
As per the PAPR, bit 0 of byte 64 in pa-features property
indicates availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to find
whethe
The generated qapi_event_send_FOO() call an event emitter function.
It's test_qapi_event_emit() in this test. It compares the actual
event to the expected event, and sets a flag to record it was called.
The test functions set expected data and clear the flag before calling
qapi_event_send_FOO(), a
Mutex @test_event_lock is held from fixture setup to teardown,
protecting global variable @test_event_data. But tests always run one
after the other, so this is superfluous. It also confuses Coverity.
Drop the mutex.
Fixes: CID 1527425
Signed-off-by: Markus Armbruster
---
tests/unit/test-qmp-e
The fixture buys us exactly nothing, as we need a global variable
anyway, for test_qapi_event_emit(). Drop it.
Signed-off-by: Markus Armbruster
---
tests/unit/test-qmp-event.c | 91 -
1 file changed, 30 insertions(+), 61 deletions(-)
diff --git a/tests/unit/
Markus Armbruster (3):
tests/unit/test-qmp-event: Drop superfluous mutex
tests/unit/test-qmp-event: Simplify event emission check
tests/unit/test-qmp-event: Replace fixture by global variables
tests/unit/test-qmp-event.c | 108 +++-
1 file changed, 31 inserti
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have cpu_exec_realizefn()
return a boolean indicating whether an error is set or not.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewe
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
Return early if bc->alloc is NULL. De-indent the if() ladder.
Note, this avoids a pointless call to error_propagate() with
errp=NULL at the 'out:' label.
Change trivial when reviewed with 'git-diff --ignore-all-space'.
Signed-off-by: Ph
On Mon, 20 Nov 2023 23:32, Philippe Mathieu-Daudé wrote:
In preparation of having HostMemoryBackendClass::alloc() handlers
return a boolean, have them use g_autofree.
Signed-off-by: Philippe Mathieu-Daudé
---
Reviewed-by: Manos Pitsidianakis
On Tue, Oct 31, 2023 at 6:35 AM ~lbryndza wrote:
>
> From: Lucjan Bryndza
>
> The current implementation of timers does not work properly
> even in basic functionality. A counter configured to report
> an interrupt every 10ms reports the first interrupts after a
> few seconds. There are also no
On Fri, Nov 10, 2023 at 1:24 AM Peter Maydell wrote:
>
> On Tue, 7 Nov 2023 at 02:36, Alistair Francis wrote:
> >
> > From: Rob Bradford
> >
> > Check the PMU available bitmask when checking if a counter is valid
> > rather than comparing the index against the number of PMUs.
> >
> > Signed-off-
From: Ivan Klokov
According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation
Process
access-fault exceptions may raise only after PMA/PMP check. Current
implementation
generates an access-fault for mbare mode even if there were no PMA/PMP errors.
This patch removes the erroneous
From: Román Cárdenas
If you check the manual of SiFive E310
(https://cdn.sparkfun.com/assets/7/f/0/2/7/fe310-g002-manual-v19p05.pdf),
you can see in Figure 1 that the CLINT is connected to the real time clock,
which also feeds the AON peripheral (they share the same clock).
In page 43, the docs
From: Clément Chigot
The extensions zicntr and zihpm were officially added in the privilege
instruction set specification 1.12. However, QEMU has been implemented
them long before it and thus they are forced to be on during the cpu
initialization to ensure compatibility (see riscv_cpu_init).
risc
From: Daniel Henrique Barboza
Commit 49554856f0 fixed a problem, where TPM devices were not appearing
in the FDT, by delaying the FDT creation up until virt_machine_done().
This create a side effect (see gitlab #1925) - devices that need access
to the '/chosen' FDT node during realize() stopped w
From: Ivan Klokov
According to RISCV Specification sect 9.5 on two stage translation when
V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes
execute-only pages readable, only overrides VS-stage page protection.
Setting MXR at HS-level(mstatus_hs), however, overrides both VS-stage
an
The following changes since commit 8fa379170c2a12476021f5f50d6cf3f672e79e7b:
Update version for v8.2.0-rc1 release (2023-11-21 13:56:12 -0500)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20231122
for you to fetch changes up to 6bca
From: Palmer Dabbelt
Support for probing the Zicboz block size landed in Linux 6.6, which was
released a few weeks ago. This provides the user-configured block size
when Zicboz is enabled.
Signed-off-by: Palmer Dabbelt
Reviewed-by: Alistair Francis
Reviewed-by: Daniel Henrique Barboza
Messag
If a source device is connected to the IOPMP device, its memory access will be
checked by the IOPMP rule.
- Add 'iopmp=on' option to add an iopmp device and a dma device which is
connected to the iopmp to machine. This option is assumed to be "off"
- Add 'iopmp_cascade=on' option to add second i
Make other device can use /hw/core/stream.c by select this config.
Signed-off-by: Ethan Chen
---
hw/Kconfig | 1 +
hw/core/Kconfig | 3 +++
hw/core/meson.build | 2 +-
3 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/Kconfig b/hw/Kconfig
index 9ca7b38c31..e4d153dce7
ATCDMAC300 is a direct memory access controller (DMAC) which transfers data
efficiently between devices on the AMBA AXI4 bus.
ATCDMAC300 supports up to 8 DMA channels. Each DMA channel provides a set of
registers to describe the intended data transfers
To support RISC-V IOPMP, a memory access dev
Support specification Version 1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
IOPMP check memory access from deivce is valid or not. This implementation uses
IOMMU to change address space that device access. The
This series implements IOPMP specification v1.0.0-draft4 rapid-k model.
The specification url:
https://github.com/riscv-non-isa/iopmp-spec/blob/main/riscv_iopmp_specification.pdf
When IOPMP is enabled, a DMA device ATCDMAC300 is added to RISC-V virt
platform. This DMA device is connected to the IO
>-Original Message-
>From: Nicolin Chen
>Sent: Wednesday, November 22, 2023 6:56 AM
>Subject: Re: [PATCH v7 00/27] vfio: Adopt iommufd
>
>On Tue, Nov 21, 2023 at 04:43:59PM +0800, Zhenzhong Duan wrote:
>
>> qemu code:
>https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_cdev_v7
Hi Philippe,
>-Original Message-
>From: Philippe Mathieu-Daudé
>Sent: Wednesday, November 22, 2023 2:39 AM
>Subject: Re: [PATCH v7 08/27] vfio/pci: Introduce a vfio pci hot reset
>interface
>
>Hi Zhenzhong,
>
>On 21/11/23 09:44, Zhenzhong Duan wrote:
>> Legacy vfio pci and iommufd cdev h
>-Original Message-
>From: Cédric Le Goater
>Sent: Wednesday, November 22, 2023 1:23 AM
>Subject: Re: [PATCH v7 00/27] vfio: Adopt iommufd
>
>Hello Zhenzhong
>
>On 11/21/23 09:43, Zhenzhong Duan wrote:
>> Hi,
>>
>> Thanks all for giving guides and comments on previous series, this is
>>
On Tue, Nov 21, 2023 at 5:19 PM Ivan Klokov wrote:
>
> A series of patches that correct the conversion of virtual addresses
> to physical ones. Correct exception for mbare mode and fix MXR bit
> behavior with MPV\MPRV bits.
> ---
> v2:
>- Fix typo, specify the fixed commits
> ---
>
> Ivan Klok
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
second release candidate for the QEMU 8.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.2.0-rc1.tar.xz
http://download.qemu
On Tue, Nov 21, 2023 at 6:53 PM Ivan Klokov wrote:
>
> According to RISCV Specification sect 9.5 on two stage translation when
> V=1 the vsstatus(mstatus in QEMU's terms) field MXR, which makes
> execute-only pages readable, only overrides VS-stage page protection.
> Setting MXR at HS-level(mstatu
On Tue, Nov 21, 2023 at 6:51 PM Ivan Klokov wrote:
>
> According to RISCV privileged spec sect. 5.3.2 Virtual Address Translation
> Process
> access-fault exceptions may raise only after PMA/PMP check. Current
> implementation
> generates an access-fault for mbare mode even if there were no PMA/
bump
On Sat, Nov 18, 2023 at 5:13 PM Daniel Hoffman wrote:
>
> This conversion is pretty straight-forward. Standardized some formatting
> so the +0 and +4 offset cases can recycle the same message.
>
> Signed-off-by: Daniel Hoffman
> ---
> hw/timer/hpet.c | 55 +---
>From their Discord server in reply to a question about whether such a
patch would be upstreamed: "I suspect this only works in gcc -O0
because of its AST-level "fold", which clang intentionally doesn't
implement. So probably not."
I hope that's enough information to resolve this patch. If any of
On 11/20/23 19:42, Cornelia Huck wrote:
Add 9.0 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 17 +
On Tue, Nov 21, 2023 at 04:43:59PM +0800, Zhenzhong Duan wrote:
> qemu code: https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_cdev_v7
> Based on vfio-next, commit id: c487fb8a50
I've tested with an aarch64-softmmu build using both legacy VFIO
passthrough and IOMMUFD+cdev, although thi
On Tue, Nov 21, 2023 at 04:21:18PM -0500, Steven Sistare wrote:
> On 11/20/2023 4:44 PM, Peter Xu wrote:
> > On Mon, Nov 20, 2023 at 03:55:54PM -0500, Steven Sistare wrote:
> >> If we drop force, then all calls to vm_stop will completely stop the
> >> suspended state, eg an hmp "stop" command. This
From: Helge Deller
The following changes since commit ea6a33e776f0a4bda94460ab0945d953fc801dd1:
Revert "tests/avocado: Enable reverse_debugging.py tests in gitlab CI"
(2023-11-21 10:28:55 -0500)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git tags/seabios-
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
From: Oleksandr Tyshchenko
The bridge is needed for virtio-pci support, as QEMU can emulate the
whole bridge with any virtio-pci devices connected to it.
This patch provides a flexible way to configure PCIe brige resources
with xenstore. We made this for several reasons:
- We don't want to clas
From: David Woodhouse
This allows a XenDevice implementation to know whether it was created
by QEMU, or merely discovered in XenStore after the toolstack created
it. This will allow us to create frontend/backend nodes only when we
should, rather than unconditionally attempting to overwrite them f
From: Oleksandr Tyshchenko
Instead of forcing the owner to domid 0, use XS_PRESERVE_OWNER to
inherit the owner of the directory.
Note that for other than Dom0 domain (non toolstack domain) the
"driver_domain" property should be set in domain config file for the
toolstack to create required direc
From: Oleksandr Tyshchenko
The number of vCPUs used for the IOREQ configuration (machine->smp.cpus)
should really match the system value as for each vCPU we setup a dedicated
evtchn for the communication with Xen at the runtime. This is needed
for the IOREQ to be properly configured and work if t
Hello,
This patch series adds the basic support for virtio-pci for xen-arm
guests. The main changes are in "xen_arm: Add virtual PCIe host bridge
support", while most of other patches are required to make QEMU work
as device model in a non-privileged domains like driver domain.
Changes v1->v2:
Add option to preserve owner when creating an entry in Xen Store. This
may be needed in cases when Qemu is working as device model in a
domain that is Domain-0, e.g. in driver domain.
"owner" parameter for qemu_xen_xs_create() function can have special
value XS_PRESERVE_OWNER, which will make spec
was created by QEMU
Xen PV devices in QEMU can be created in two ways: either by QEMU
itself, if they were passed via command line, or by Xen toolstack. In
the latter case, QEMU scans XenStore entries and configures devices
accordingly.
In the second case we don't want QEMU to write/delete front-
On 11/20/2023 4:44 PM, Peter Xu wrote:
> On Mon, Nov 20, 2023 at 03:55:54PM -0500, Steven Sistare wrote:
>> If we drop force, then all calls to vm_stop will completely stop the
>> suspended state, eg an hmp "stop" command. This causes two problems.
>> First, that is a change in user-visible behavio
Hi Arnaud,
On 11/11/23 15:33, ~aminier wrote:
From: Arnaud Minier
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/Kconfig| 1 +
hw/arm/stm32l4x5_soc.c| 65 +-
hw/misc/Kconfig | 3 +
hw/misc/meson.build
From: Helge Deller
Please pull an update of SeaBIOS-hppa to v13 to fix
a system reboot crash in qemu-system-hppa as reported in
https://gitlab.com/qemu-project/qemu/-/issues/1991
Helge Deller (1):
target/hppa: Update SeaBIOS-hppa to version 13
pc-bios/hppa-firmware.img | Bin 681332 -> 681388
Allow building a qemu-system-foo binary with target-agnostic
only HW models.
Signed-off-by: Philippe Mathieu-Daudé
---
Although this is for 9.0, I wanted to post it today to celebrate :)
Once reviewed I plan to queue it via my heterogenenous-cpus tree.
---
meson.build | 8 +---
1 file chan
On Tue, 2023-11-21 at 19:36 +0100, Cédric Le Goater wrote:
> On 11/21/23 00:51, Glenn Miles wrote:
> > For power10-rainier, a pca9552 device is used for PCIe slot hotplug
> > power control by the Power Hypervisor code. The code expects that
> > some time after it enables power to a PCIe slot by as
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good" signal asserted
on one of pca9552 GPIO p
Tests the following for both P9 and P10:
- I2C master POR status
- I2C master status after immediate reset
Tests the following for powernv10-ranier only:
- Config pca9552 hotplug device pins as inputs then
Read the INPUT0/1 registers to verify all pins are high
- Connected GPIO pin tes
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
Signed-off-by: Glenn Miles
---
Changes from previous version:
- Formatting changes
- Capitalized "Rainier" in machine description string
- Changed powernv10-rainier parent to MACHINE_TYPE_NAME
Specs are available here:
https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
This is a simple model supporting the basic registers for GPIO
mode. The device also supports an interrupt output line but the
model does not yet support this.
Reviewed-by: Cédric Le Goater
Signed-off-by: Gl
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices wired
to the PNV I2C controller from bein
The Power Hypervisor code expects to see a pca9552 device connected
to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
justified address of 0xC6). This is used by hypervisor code to
control PCIe slot power during hotplug events.
Reviewed-by: Cédric Le Goater
Signed-off-by: Glenn M
Allow external devices to drive pca9552 input pins by adding
input GPIO's to the model. This allows a device to connect
its output GPIO's to the pca9552 input GPIO's.
In order for an external device to set the state of a pca9552
pin, the pin must first be configured for high impedance (LED
is off
The pca9552 INPUT0 and INPUT1 registers are supposed to
hold the logical values of the LED pins. A logical 0
should be seen in the INPUT0/1 registers for a pin when
its corresponding LSn bits are set to 0, which is also
the state needed for turning on an LED in a typical
usage scenario. Existing
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present.
Signed-off-by: Glenn Miles
---
No c
This series of patches includes support, tests and fixes for
adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
The PCA9552 device is used for PCIe slot hotplug power control
and monitoring, while the PCA9554 device is used for presence
detection of IBM CableCard devices. Both devices
On 11/21/23 12:50, Richard Henderson wrote:
On 11/20/23 15:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, errp;
@@
- memory_region_init_rom_nomigrate(mr, owner, arg3, arg4, &errp);
if (
- errp
+
On 11/20/23 15:32, Philippe Mathieu-Daudé wrote:
Mechanical change using the following coccinelle script:
@@
expression mr, owner, arg3, arg4, errp;
@@
- memory_region_init_rom_nomigrate(mr, owner, arg3, arg4, &errp);
if (
- errp
+ !memory_region_init_rom_nomigrate(mr, owner,
On 21/11/2023 18.34, Kevin Wolf wrote:
Kevin Wolf (2):
qdev: Fix crash in array property getter
string-output-visitor: Support lists for non-integer types
hw/core/qdev-properties.c| 33 ++---
qapi/string-output-visitor.c | 24
2
On 11/21/23 08:46, Peter Maydell wrote:
The system registers DBGVCR32_EL2, FPEXC32_EL2, DACR32_EL2 and
IFSR32_EL2 are present only to allow an AArch64 EL2 or EL3 to read
and write the contents of an AArch32-only system register. The
architecture requires that they are present only when EL1 can b
Hi Zhenzhong,
On 21/11/23 09:44, Zhenzhong Duan wrote:
Legacy vfio pci and iommufd cdev have different process to hot reset
vfio device, expand current code to abstract out pci_hot_reset callback
for legacy vfio, this same interface will also be used by iommufd
cdev vfio device.
Rename vfio_pci
On 11/21/23 00:51, Glenn Miles wrote:
For power10-rainier, a pca9552 device is used for PCIe slot hotplug
power control by the Power Hypervisor code. The code expects that
some time after it enables power to a PCIe slot by asserting one of
the pca9552 GPIO pins 0-4, it should see a "power good"
On Tue, 2023-11-21 at 19:26 +0100, Cédric Le Goater wrote:
> On 11/21/23 17:36, Miles Glenn wrote:
> > On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
> > > On 11/21/23 02:33, Nicholas Piggin wrote:
> > > > On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
> > > > > Create a new po
Hi Phil,
On 11/21/23 18:40, Philippe Mathieu-Daudé wrote:
> Commit 0be6bfac62 ("qdev: Implement variable length array properties")
> added the DEFINE_PROP_ARRAY() macro with the following comment:
>
> * It is the responsibility of the device deinit code to free the
> * @_arrayfield memory.
>
>
I'm writing a patch to clang's constant folding to address this case
(doesn't seem too difficult). I'll either follow up with a link to
some submissions I've made or a bug report on the project describing
the issue.
On Tue, Nov 21, 2023 at 10:15 AM Eric Blake wrote:
>
> On Mon, Nov 20, 2023 at
On 11/21/23 17:36, Miles Glenn wrote:
On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
On 11/21/23 02:33, Nicholas Piggin wrote:
On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
On 11/21/23 00:51, Glenn Miles wrote:
The QEMU I2C buses and devices use the resettable
interface for resetting while the PNV I2C controller
and parent buses and devices have not yet transitioned
to this new interface and use the old reset strategy.
This was preventing the I2C buses and devices w
On 11/21/23 00:51, Glenn Miles wrote:
The PNV I2C Controller was clearing the status register
after a reset without repopulating the "upper threshold
for I2C ports", "Command Complete" and the SCL/SDA input
level fields.
Fixed this for resets caused by a system reset as well
as from writing to t
On 11/21/23 00:51, Glenn Miles wrote:
The PNV I2C engines for power9 and power10 were being assigned a base
XSCOM address that was off by one I2C engine's address range such
that engine 0 had engine 1's address and so on. The xscom address
assignment was being based on the device tree engine num
On 11/21/23 00:51, Glenn Miles wrote:
For powernv10-rainier, the Power Hypervisor code expects to see a
pca9554 device connected to the 3rd PNV I2C engine on port 1 at I2C
address 0x25 (or left-justified address of 0x4A). This is used by
the hypervisor code to detect if a "Cable Card" is present
On 11/21/23 17:36, Miles Glenn wrote:
On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
On 11/21/23 02:33, Nicholas Piggin wrote:
On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
Create a new powernv machine type, powernv10-rainier, that
will contain rainier-specific devices.
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi everyone,
The QEMU v8.1.3 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v8.1.3 is now tagged in the official qemu.git repository, and the
stable-8.1 branch has be
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi everyone,
The QEMU v7.2.7 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v7.2.7 is now tagged in the official qemu.git repository, and the
stable-7.2 branch has be
On Tue, 2023-11-21 at 07:46 +0100, Cédric Le Goater wrote:
> On 11/21/23 00:51, Glenn Miles wrote:
> > Create a new powernv machine type, powernv10-rainier, that
> > will contain rainier-specific devices.
> >
> > Signed-off-by: Glenn Miles
> > ---
> > hw/ppc/pnv.c | 29 +
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 4fb013afcc added:
DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_o
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit a75f336b97 added:
DEFINE_PROP_ARRAY("keycodes", StellarisGam
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 68fbcc344e added:
DEFINE_PROP_ARRAY("read-only", XlnxEFuse,
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 9e4aa1fafe added:
DEFINE_PROP_ARRAY("pg0-lock",
The VirtioPCIDeviceTypeInfo structure, added in commit a4ee4c8baa
("virtio: Helper for registering virtio device types") got extended
in commit 8ea90ee690 ("virtio: add class_size") with the @class_size
field. Do similarly with the @instance_finalize field.
Signed-off-by: Philippe Mathieu-Daudé
-
In few places we forget to free the array allocated by the
DEFINE_PROP_ARRAY() macro handlers. Fix that.
Philippe Mathieu-Daudé (6):
hw/virtio: Add VirtioPCIDeviceTypeInfo::instance_finalize field
hw/virtio: Free VirtIOIOMMUPCI::vdev.reserved_regions[] on finalize()
hw/misc/mps2-scc: Free MP
Commit 0be6bfac62 ("qdev: Implement variable length array properties")
added the DEFINE_PROP_ARRAY() macro with the following comment:
* It is the responsibility of the device deinit code to free the
* @_arrayfield memory.
Commit 8077b8e549 added:
DEFINE_PROP_ARRAY("reserved-regions", Virt
Kevin Wolf (2):
qdev: Fix crash in array property getter
string-output-visitor: Support lists for non-integer types
hw/core/qdev-properties.c| 33 ++---
qapi/string-output-visitor.c | 24
2 files changed, 46 insertions(+), 11 deletions(
Passing an uninitialised list to visit_start_list() happens to work for
the QObject output visitor because it treats the pointer as an opaque
value and never dereferences it, but the string output visitor expects a
valid list to check if it has more than one element.
The existing code crashes with
With the introduction of list-based array properties in qdev, the string
output visitor has to deal with lists of non-integer elements now ('info
qtree' prints all properties with the string output visitor).
Currently there is no explicit support for such lists, and the resulting
output is only th
On Tue, 21 Nov 2023 at 17:05, Paolo Bonzini wrote:
>
> The URL to the Coverity tools download has changed; the old one points
> to an obsolete version that is not supported anymore. Adjust to point
> to the correct and supported tools.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Paolo Bonzi
Mikhail Tyutin writes:
>> >> > I suspect it is because of memory mappings by guest OS that changes
>> >> > virtual addresses for that block.
>> >> >
>> >> > I also looked at gen_empty_udata_cb() function and considered to extend
>> >> > plugin API to pass a program counter
>> >> > value as addi
Hello Zhenzhong
On 11/21/23 09:43, Zhenzhong Duan wrote:
Hi,
Thanks all for giving guides and comments on previous series, this is
the remaining part of the iommufd support.
Besides suggested changes in v6, I'd like to highlight two changes
for final review:
1. Instantiate can_be_deleted callb
Peter Maydell writes:
> QEMU Summit Minutes 2023
>
>
> As usual, we held a QEMU Summit meeting at KVM Forum. This is an
> invite-only meeting for the most active maintainers and submaintainers
> in the project, and we discuss various project-wide issues, usually
> proces
The URL to the Coverity tools download has changed; the old one points
to an obsolete version that is not supported anymore. Adjust to point
to the correct and supported tools.
Suggested-by: Peter Maydell
Signed-off-by: Paolo Bonzini
---
scripts/coverity-scan/run-coverity-scan | 4 ++--
1 file
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