Re: [PATCH 1/3] hw/arm/virt: Add serial aliases in DTB

On 23/10/23 18:15, Peter Maydell wrote: If there is more than one UART in the DTB, then there is no guarantee on which order a guest is supposed to initialise them. The standard solution to this is "serialN" entries in the "/aliases" node of the dtb which give the nodename of the UARTs. At the

Re: [PATCH 2/3] hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]

On 23/10/23 18:15, Peter Maydell wrote: We're going to make the second UART not always a secure-only device. Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0 and VIRT_UART1 accordingly. Signed-off-by: Peter Maydell --- include/hw/arm/virt.h| 4 ++-- hw/arm/virt-acpi-bui

Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and targetted interface

Hello Zhenzhong, you would need to do that for all types for vfio devices, ap, ccw, platform. Looks heavy to me. Why would we need to use a different vfio-pci-* device while we could switch the iommu backend according to the "iommufd" prop presence. The initial discussion was about QOMyfying the

Re: [PATCH v1] virtio-mem: fix division by zero in virtio_mem_activate_memslots_to_plug()

This patch has been successfully tested by QE. With a debug QEMU build, start a VM with a virtio-mem device and 'dynamic-memslots=off', this one can be resized seamlessly, no floating point exception found. Tested-by: Mario Casquero On Mon, Oct 23, 2023 at 1:13 PM David Hildenbrand wrote: >

Re: [PULL v3 21/62] hw/display: fix memleak from virtio_add_resource

22.10.2023 12:23, Michael S. Tsirkin: ... Signed-off-by: Matheus Tavares Bernardino Message-Id: Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Albert Esteve Signed-off-by: Matheus Tavares Bernardino quic_ma

Re: [PATCH v3 1/2] target/s390x/kvm: Turn KVM_CAP_SYNC_REGS into a hard requirement

On 10/11/23 10:05, Thomas Huth wrote: Since we already require at least kernel 3.15 in the s390x KVM code, we can assume that the KVM_CAP_SYNC_REGS capability is always there. Thus turn this into a hard requirement now. Reviewed-by: Christian Borntraeger Signed-off-by: Thomas Huth Reviewed-

Re: [PATCH v3 2/2] target/s390x/kvm: Simplify the GPRs, ACRs, CRs and prefix synchronization code

On 10/11/23 10:05, Thomas Huth wrote: KVM_SYNC_GPRS, KVM_SYNC_ACRS, KVM_SYNC_CRS and KVM_SYNC_PREFIX are available since kernel 3.10. Since we already require at least kernel 3.15 in the s390x KVM code, we can also assume that the KVM_CAP_SYNC_REGS sync code is always possible for these registers

Re: [PATCH 0/5] Add LoongArch v1.1 instructions

On 2023/10/24 07:26, Richard Henderson wrote: On 10/23/23 08:29, Jiajie Chen wrote: This patch series implements the new instructions except sc.q, because I do not know how to match a pair of ll.d to sc.q. There are a couple of examples within the tree. See target/arm/tcg/translate-a64.c, g

RE: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and targetted interface

>-Original Message- >From: Cédric Le Goater >Sent: Monday, October 23, 2023 11:29 PM > >Subject: Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and >targetted interface > >On 10/20/23 10:19, Eric Auger wrote: >> Hi, >> On 10/20/23 07:48, Duan, Zhenzhong wrote: >>> Hi

Re: [PATCH v5] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps

Michael, On 10/23/23 10:24, Cédric Le Goater wrote: From: Yi Liu This patch modifies pci_setup_iommu() to set PCIIOMMUOps instead of setting PCIIOMMUFunc. PCIIOMMUFunc is used to get an address space for a PCI device in vendor specific way. The PCIIOMMUOps still offers this functionality. But

Re: [PATCH v15 10/14] fixup! migration: New migrate and migrate-incoming argument 'channels'

Fabiano Rosas writes: > Signed-off-by: Fabiano Rosas > Reviewed-by: Daniel P. Berrangé > --- > qapi/migration.json | 8 > 1 file changed, 8 insertions(+) > > diff --git a/qapi/migration.json b/qapi/migration.json > index fa9534a661..2cfdae894a 100644 > --- a/qapi/migration.json > +++

Re: [PATCH v15 02/14] fixup! migration: New QAPI type 'MigrateAddress'

Fabiano Rosas writes: > Signed-off-by: Fabiano Rosas > Reviewed-by: Daniel P. Berrangé > --- > qapi/migration.json | 20 ++-- > 1 file changed, 18 insertions(+), 2 deletions(-) > > diff --git a/qapi/migration.json b/qapi/migration.json > index c352c7ac52..abebe23523 100644 > --

Re: [PATCH] ppc/pnv: Fix number of I2C engines and ports for power9/10

Hello Glenn, On 10/23/23 18:52, Glenn Miles wrote: Power9 is supposed to have 4 PIB-connected I2C engines with the following number of ports on each engine: 0: 2 1: 13 2: 2 3: 2 Power10 also has 4 engines but has the following number of ports on each engine: 0: 14

Re: [PATCH v2 28/29] migration: Add direct-io parameter

Fabiano Rosas writes: > Add the direct-io migration parameter that tells the migration code to > use O_DIRECT when opening the migration stream file whenever possible. > > This is currently only used for the secondary channels of fixed-ram > migration, which can guarantee that writes are page ali

Re: [PATCH v2 14/29] migration/ram: Introduce 'fixed-ram' migration capability

Fabiano Rosas writes: > Add a new migration capability 'fixed-ram'. > > The core of the feature is to ensure that each ram page has a specific > offset in the resulting migration stream. The reason why we'd want > such behavior are two fold: > > - When doing a 'fixed-ram' migration the resulting

Re: [PATCH v2 06/29] migration: Add auto-pause capability

Fabiano Rosas writes: > Add a capability that allows the management layer to delegate to QEMU > the decision of whether to pause a VM and perform a non-live > migration. Depending on the type of migration being performed, this > could bring performance benefits. > > Note that the capability is en

Re: [PATCH] migration/ram: Fix compilation with -Wshadow=local

Markus Armbruster writes: > Thomas Huth writes: > >> No need for a new variable here, especially not for one that shadows >> a variable from the beginning of the function scope. With this change >> the code now successfully compiles with -Wshadow=local. >> >> Signed-off-by: Thomas Huth >> --- >

Re: [PATCH v2] block/snapshot: Fix compiler warning with -Wshadow=local

Thomas Huth writes: > No need to declare a new variable in the the inner code block > here, we can re-use the "ret" variable that has been declared > at the beginning of the function. With this change, the code > can now be successfully compiled with -Wshadow=local again. > > Fixes: a32e781838 ("

Re: [PATCH v2 0/2] igb: Add FLR support

On 2023/10/24 0:45, Cédric Le Goater wrote: From: Cédric Le Goater Hello, Here is a little series adding FLR to the new IGB models. Thanks, C. Changes in v2: - add a "x-pcie-flr-init" compat property for pre 8.2 machines Cédric Le Goater (2): igb: Add a VF reset handler igb: Add Fun

Re: [PULL v3 00/38] tcg patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL v3 00/46] Misc HW/UI patches for 2023-10-19

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL v3 00/62] virtio,pc,pci: features, cleanups

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PULL 00/17] Trivial patches for 2023-10-21

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [RFC PATCH 9/9] target/ppc: Use tcg_gen_sextract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- RFC: Please double-check 32/64 & bits --- target/ppc/translate.c | 22 -- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/target/ppc/tr

RE: [PATCH v4] target/riscv: update checks on writing pmpcfg for Smepmp to version 1.0

> On Mon, Sep 25, 2023 at 2:11 AM Alvin Chang > wrote: > > > > Current checks on writing pmpcfg for Smepmp follows Smepmp version > > 0.9.1. However, Smepmp specification has already been ratified, and > > there are some differences between version 0.9.1 and 1.0. In this > > commit we update

Re: [PATCH v4 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro

On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote: > > A 32-bit mask can be trivially created using the 64-bit macro so make > use of that instead. > > Signed-off-by: Rob Bradford > Reviewed-by: Alistair Francis > --- > target/riscv/pmu.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions

Re: [PATCH v4 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation

On Sun, Oct 22, 2023 at 7:04 PM Alistair Francis wrote: > > On Thu, Oct 19, 2023 at 1:47 AM Rob Bradford wrote: > > > > This has been replaced by a "pmu-mask" property that provides much more > > flexibility. > > > > Signed-off-by: Rob Bradford > > Acked-by: LIU Zhiwei > > Reviewed-by: Alistair

Re: [RFC PATCH 8/9] target/cris: Use tcg_gen_sextract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- RFC: please double-check bits --- target/cris/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/cris/translate.c b/target/cris/tran

Re: [PATCH 7/9] target/mips: Use tcg_gen_sextract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/mxu_translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.

Re: [PATCH v3 07/12] hw/riscv/virt-acpi-build.c: Add CMO information in RHCT

On Fri, Oct 20, 2023 at 12:59 AM Sunil V L wrote: > > When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the > block size for those extensions need to be communicated via CMO node in > RHCT. Add CMO node in RHCT if any of those CMO extensions are detected. > > Signed-off-by: S

Re: [PATCH v3 06/12] hw/riscv/virt-acpi-build.c: Add APLIC in the MADT

On Thu, Oct 19, 2023 at 11:29 PM Sunil V L wrote: > > Add APLIC structures for each socket in the MADT when system is configured > with APLIC as the external wired interrupt controller. > > Signed-off-by: Sunil V L > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair >

Re: [PATCH v3 05/12] hw/riscv/virt-acpi-build.c: Add IMSIC in the MADT

On Thu, Oct 19, 2023 at 11:28 PM Sunil V L wrote: > > Add IMSIC structure in MADT when IMSIC is configured. > > Signed-off-by: Sunil V L > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/virt-acpi-build.c | 34 ++ > 1

Re: [PATCH v3 04/12] hw/riscv/virt-acpi-build.c: Add AIA support in RINTC

On Thu, Oct 19, 2023 at 11:28 PM Sunil V L wrote: > > Update the RINTC structure in MADT with AIA related fields. > > Signed-off-by: Sunil V L > Reviewed-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > hw/riscv/virt-acpi-build.c | 66 +

Re: [PATCH v4 3/6] target/riscv: Use existing PMU counter mask in FDT generation

On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote: > > During the FDT generation use the existing mask containing the enabled > counters rather then generating a new one. Using the existing mask will > support the use of discontinuous counters. > > Signed-off-by: Rob Bradford > Reviewed-by: LIU

Re: [PATCH v4 2/6] target/riscv: Don't assume PMU counters are continuous

On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote: > > Check the PMU available bitmask when checking if a counter is valid > rather than comparing the index against the number of PMUs. > > Signed-off-by: Rob Bradford > Reviewed-by: LIU Zhiwei > Reviewed-by: Alistair Francis > --- > target/ris

Re: [PATCH v4 1/6] target/riscv: Propagate error from PMU setup

On Wed, Oct 18, 2023 at 8:44 AM Rob Bradford wrote: > > More closely follow the QEMU style by returning an Error and propagating > it there is an error relating to the PMU setup. > > Further simplify the function by removing the num_counters parameter as > this is available from the passed in cpu

Re: [PATCH v3 0/8] PMBus fixes and new functions

On Mon, 23 Oct 2023 at 12:16, Alex Bennée wrote: > You seem to have missed a number of tags from previous postings: > > > https://qemu.readthedocs.io/en/master/devel/submitting-a-patch.html#proper-use-of-reviewed-by-tags-can-aid-review > > (although I notice we only mention Reviewed-by in the

[PATCH v4 3/8] hw/i2c: pmbus: add fan support

PMBus devices may integrate fans whose operation is configurable over PMBus. This commit allows the driver to read and write the fan control registers but does not model the operation of fans. Reviewed-by: Stephen Longfield Acked-by: Corey Minyard Signed-off-by: Titus Rwantare --- hw/i2c/pmbus

[PATCH v4 7/8] hw/i2c: pmbus: immediately clear faults on request

The probing process of the generic pmbus driver generates faults to determine if functions are available. These faults were not always cleared resulting in probe failures. Reviewed-by: Patrick Venture Signed-off-by: Titus Rwantare --- hw/i2c/pmbus_device.c | 5 + 1 file changed, 5 insertion

[PATCH v4 2/8] hw/i2c: pmbus: add vout mode bitfields

The VOUT_MODE command is described in the PMBus Specification, Part II, Ver 1.3 Section 8.3 VOUT_MODE has a three bit mode and 4 bit parameter, the three bit mode determines whether voltages are formatted as uint16, uint16, VID, and Direct modes. VID and Direct modes use the remaining 5 bits to sc

[PATCH v4 4/8] hw/i2c: pmbus: add VCAP register

VCAP is a register for devices with energy storage capacitors. Reviewed-by: Benjamin Streb Acked-by: Corey Minyard Signed-off-by: Titus Rwantare --- hw/i2c/pmbus_device.c | 8 include/hw/i2c/pmbus_device.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/i2c/pmbus_devi

[PATCH v4 5/8] hw/sensor: add ADM1266 device model

The ADM1266 is a cascadable super sequencer with margin control and fault recording. This commit adds basic support for its PMBus commands and models the identification registers that can be modified in a firmware update. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus

[PATCH v4 8/8] hw/i2c: pmbus: reset page register for out of range reads

The linux pmbus driver scans all possible pages and does not reset the current page after the scan, making all future page reads fail as out of range on devices with a single page. This change resets out of range pages immediately on write. Also added a qtest for simultaneous writes to all pages.

[PATCH v4 1/8] hw/i2c: pmbus add support for block receive

PMBus devices can send and receive variable length data using the block read and write format, with the first byte in the payload denoting the length. This is mostly used for strings and on-device logs. Devices can respond to a block read with an empty string. Reviewed-by: Hao Wu Acked-by: Corey

[PATCH v4 0/8] PMBus fixes and new functions

: 384dbdda94c0bba55bf186cccd3714bbb9b737e9 change-id: 20231023-staging-pmbus-v3-62de60bff397 Best regards, -- Titus Rwantare

[PATCH v4 6/8] tests/qtest: add tests for ADM1266

The ADM1266 can have string fields written by the driver, so it's worth specifically testing. Reviewed-by: Hao Wu Acked-by: Corey Minyard Signed-off-by: Titus Rwantare --- tests/qtest/adm1266-test.c | 123 + tests/qtest/meson.build| 1 + 2

Re: [PATCH v2 1/3] misc/pca9552: Fix inverted input status

On Fri, 2023-10-20 at 13:23 -0500, Glenn Miles wrote: > The pca9552 INPUT0 and INPUT1 registers are supposed to > hold the logical values of the LED pins. A logical 0 > should be seen in the INPUT0/1 registers for a pin when > its corresponding LSn bits are set to 0, which is also > the state need

Re: [PATCH v2 3/3] misc/pca9552: Only update output GPIOs if state changed

On Fri, 2023-10-20 at 13:23 -0500, Glenn Miles wrote: > The pca9552 code was updating output GPIO states whenever > the pin state was updated even if the state did not change. > This commit adds a check so that we only update the GPIO > output when the pin state actually changes. Given this is int

Re: [PATCH 5/9] target/sparc: Use tcg_gen_extract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f92ff80ac8..1

Re: [PATCH 4/9] target/ppc: Use tcg_gen_extract_i32

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/ppc/translate.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d518..c6e1f7c

Re: [PATCH 3/9] target/mips: Use tcg_gen_extract_i32

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/translate.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 2/9] target/cris: Use tcg_gen_extract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/cris/translate.c | 3 +-- target/i386/tcg/translate.c | 9 +++-- 2 files changed, 4 insertions(+), 8 deletions(-) Accidental merge of two patches, but t

Re: [PATCH 1/2] misc/pca9552: Fix inverted input status

On Fri, 2023-10-20 at 11:32 -0500, Miles Glenn wrote: > On Fri, 2023-10-20 at 11:42 +0200, Philippe Mathieu-Daudé wrote: > > On 20/10/23 04:51, Andrew Jeffery wrote: > > > On Thu, 2023-10-19 at 15:40 -0500, Glenn Miles wrote: > > > > > The pca9552 INPUT0 and INPUT1 registers are supposed to > > > >

Re: [PATCH 1/9] target/avr: Use tcg_gen_extract_tl

On 10/23/23 09:09, Philippe Mathieu-Daudé wrote: Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/avr/translate.c | 18 ++ 1 file changed, 6 insertions(+), 12 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH 0/5] Add LoongArch v1.1 instructions

On 10/23/23 08:29, Jiajie Chen wrote: This patch series implements the new instructions except sc.q, because I do not know how to match a pair of ll.d to sc.q. There are a couple of examples within the tree. See target/arm/tcg/translate-a64.c, gen_store_exclusive, TCGv_i128 block. See target/p

Re: [PATCH 5/5] target/loongarch: Add llacq/screl instructions

On 10/23/23 08:29, Jiajie Chen wrote: --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -17,6 +17,14 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) return true; } +static bool gen_llacq(DisasContext *ctx, arg_

Re: State of contrib/vhost-user-input?

On Mon, 23 Oct 2023 at 09:29, Alex Bennée wrote: > > > Hi, CCing Gerd for vhost-user-input. > > I'm trying to get the contrib/vhost-user-input working but it exits > during the boot up sequence: > > ➜ gdb --args ./vhost-user-input -p /dev/input/event22 -s /tmp/mouse.sock > GNU gdb (GDB) 15.

Re: [PATCH 4/5] target/loongarch: Add estimated reciprocal instructions

On 10/23/23 08:29, Jiajie Chen wrote: Add the following new instructions in LoongArch v1.1: - frecipe.s - frecipe.d - frsqrte.s - frsqrte.d - vfrecipe.s - vfrecipe.d - vfrsqrte.s - vfrsqrte.d - xvfrecipe.s - xvfrecipe.d - xvfrsqrte.s - xvfrsqrte.d They are guarded by CPUCFG2.FRECIPE. Altought t

Re: [PATCH 3/5] target/loongarch: Add amcas[_db].{b/h/w/d}

On 10/23/23 08:35, Jiajie Chen wrote: +static bool gen_cas(DisasContext *ctx, arg_rrr *a, +    void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp), +    MemOp mop) +{ +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); +    TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); + 

Re: [PATCH 3/5] target/loongarch: Add amcas[_db].{b/h/w/d}

On 10/23/23 08:29, Jiajie Chen wrote: +static bool gen_cas(DisasContext *ctx, arg_rrr *a, +void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp), +MemOp mop) +{ +TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); +TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); +

Re: [PATCH 2/5] target/loongarch: Add am{swap/add}[_db].{b/h}

On 10/23/23 08:29, Jiajie Chen wrote: The new instructions are introduced in LoongArch v1.1: - amswap.b - amswap.h - amadd.b - amadd.h - amswap_db.b - amswap_db.h - amadd_db.b - amadd_db.h The instructions are gated by CPUCFG2.LAM_BH. Signed-off-by: Jiajie Chen Except for the use of MO_TESB

Re: [PATCH v5 00/94] target/sparc: Convert to decodetree

On 10/23/23 11:04, Mark Cave-Ayland wrote: On 23/10/2023 00:27, Richard Henderson wrote: Changes for v5:    * Add Mark's a-b and t-b.    * Fixes to features: - Use CPU_FEATURE_BIT_* in feature_name[] (patch 7). - Don't allow features to be set/unset in nonsensical ways (new patch 8).

Re: [PATCH 2/2] hw/ide/via: implement legacy/native mode switching

On Mon, 23 Oct 2023, Mark Cave-Ayland wrote: On 20/10/2023 00:09, BALATON Zoltan wrote: On Thu, 19 Oct 2023, Mark Cave-Ayland wrote: Allow the VIA IDE controller to switch between both legacy and native modes by calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_PROG i

Re: [PATCH 2/2] hw/ide/via: implement legacy/native mode switching

On 20/10/2023 00:09, BALATON Zoltan wrote: On Thu, 19 Oct 2023, Mark Cave-Ayland wrote: Allow the VIA IDE controller to switch between both legacy and native modes by calling pci_ide_update_mode() to reconfigure the device whenever PCI_CLASS_PROG is updated. This patch also moves the setting o

Re: [PATCH v6 9/9] drm: Introduce documentation for hotspot properties

Albert Esteve writes: > From: Michael Banack > > To clarify the intent and reasoning behind the hotspot properties > introduce userspace documentation that goes over cursor handling > in para-virtualized environments. > > The documentation is generic enough to not special case for any > specific

Re: [PATCH 1/2] ide/pci.c: introduce pci_ide_update_mode() function

On 23/10/2023 18:19, Bernhard Beschow wrote: Am 22. Oktober 2023 22:06:30 UTC schrieb Bernhard Beschow : Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland : This function reads the value of the PCI_CLASS_PROG register for PCI IDE controllers and configures the PCI BARs and/or IDE io

[PATCH v2 29/29] tests/qtest: Add a test for migration with direct-io and multifd

Signed-off-by: Fabiano Rosas --- tests/qtest/migration-test.c | 25 + 1 file changed, 25 insertions(+) diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index c74c911283..30e70c0e4e 100644 --- a/tests/qtest/migration-test.c +++ b/tests/qtest/migrati

[PATCH v2 02/29] tests/qtest: Move QTestMigrationState to libqtest

Move the QTestMigrationState into QTestState so we don't have to pass it around to the wait_for_* helpers anymore. Since QTestState is private to libqtest.c, move the migration state struct to libqtest.h and add a getter. Signed-off-by: Fabiano Rosas --- tests/qtest/libqtest.c | 14

[PATCH v2 10/29] io: Add generic pwritev/preadv interface

From: Nikolay Borisov Introduce basic pwritev/preadv support in the generic channel layer. Specific implementation will follow for the file channel as this is required in order to support migration streams with fixed location of each ram page. Signed-off-by: Nikolay Borisov Signed-off-by: Fabia

[PATCH v2 24/29] migration/ram: Ignore multifd flush when doing fixed-ram migration

Some functionalities of multifd are incompatible with the 'fixed-ram' migration format. The MULTIFD_FLUSH flag in particular is not used because in fixed-ram there is no sinchronicity between migration source and destination so there is not need for a sync packet. In fact, fixed-ram disables packe

[PATCH v2 08/29] tests/qtest: File migration auto-pause tests

Adapt the file migration tests to take into account the auto-pause feature. The test currently has a flag 'stop_src' that is used to know if the test itself should stop the VM. Add a new flag 'auto_pause' to enable QEMU to stop the VM instead.. The two in combination allow us to migrate a already

[PATCH v2 28/29] migration: Add direct-io parameter

Add the direct-io migration parameter that tells the migration code to use O_DIRECT when opening the migration stream file whenever possible. This is currently only used for the secondary channels of fixed-ram migration, which can guarantee that writes are page aligned. However the parameter coul

[PATCH v2 14/29] migration/ram: Introduce 'fixed-ram' migration capability

Add a new migration capability 'fixed-ram'. The core of the feature is to ensure that each ram page has a specific offset in the resulting migration stream. The reason why we'd want such behavior are two fold: - When doing a 'fixed-ram' migration the resulting file will have a bounded size, s

[PATCH v2 27/29] tests/qtest: Add a multifd + fixed-ram migration test

Signed-off-by: Fabiano Rosas --- tests/qtest/migration-test.c | 45 1 file changed, 45 insertions(+) diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index bd4e866e67..c74c911283 100644 --- a/tests/qtest/migration-test.c +++ b/tests/qt

[PATCH v2 20/29] migration/multifd: Add incoming QIOChannelFile support

On the receiving side we don't need to differentiate between main channel and threads, so whichever channel is defined first gets to be the main one. And since there are no packets, use the atomic channel count to index into the params array. Signed-off-by: Fabiano Rosas --- migration/file.c

[PATCH v2 03/29] tests/qtest: Allow waiting for migration events

Add support for waiting for a migration state change event to happen. This can help disambiguate between runstate changes that happen during VM lifecycle. Specifically, the next couple of patches want to know whether STOP events happened at the migration start or end. Add the "setup" and "active"

[PATCH v2 26/29] migration/multifd: Support incoming fixed-ram stream format

For the incoming fixed-ram migration we need to read the ramblock headers, get the pages bitmap and send the host address of each non-zero page to the multifd channel thread for writing. To read from the migration file we need a preadv function that can read into the iovs in segments of contiguous

[PATCH v2 23/29] migration/ram: Add a wrapper for fixed-ram shadow bitmap

We'll need to set the shadow_bmap bits from outside ram.c soon and TARGET_PAGE_BITS is poisoned, so add a wrapper to it. Signed-off-by: Fabiano Rosas --- migration/ram.c | 5 + migration/ram.h | 1 + 2 files changed, 6 insertions(+) diff --git a/migration/ram.c b/migration/ram.c index cea69

[PATCH v2 18/29] migration/multifd: Allow multifd without packets

For the upcoming support to the new 'fixed-ram' migration stream format, we cannot use multifd packets because each write into the ramblock section in the migration file is expected to contain only the guest pages. They are written at their respective offsets relative to the ramblock section header

[PATCH v2 13/29] migration: fixed-ram: Add URI compatibility check

The fixed-ram migration format needs a channel that supports seeking to be able to write each page to an arbitrary offset in the migration stream. Signed-off-by: Fabiano Rosas --- migration/migration.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/mi

[PATCH v2 22/29] io: Add a pwritev/preadv version that takes a discontiguous iovec

For the upcoming support to fixed-ram migration with multifd, we need to be able to accept an iovec array with non-contiguous data. Add a pwritev and preadv version that splits the array into contiguous segments before writing. With that we can have the ram code continue to add pages in any order

[PATCH v2 07/29] migration: Run "file:" migration with a stopped VM

The file migration is asynchronous, so it benefits from being done with a stopped VM. Allow the file migration to take benefit of the auto-pause capability. Signed-off-by: Fabiano Rosas --- migration/migration.c | 4 1 file changed, 4 insertions(+) diff --git a/migration/migration.c b/migr

[PATCH v2 16/29] migration/ram: Add support for 'fixed-ram' migration restore

From: Nikolay Borisov Add the necessary code to parse the format changes for the 'fixed-ram' capability. One of the more notable changes in behavior is that in the 'fixed-ram' case ram pages are restored in one go rather than constantly looping through the migration stream. Signed-off-by: Nikol

[PATCH v2 11/29] io: implement io_pwritev/preadv for QIOChannelFile

From: Nikolay Borisov The upcoming 'fixed-ram' feature will require qemu to write data to (and restore from) specific offsets of the migration file. Add a minimal implementation of pwritev/preadv and expose them via the io_pwritev and io_preadv interfaces. Signed-off-by: Nikolay Borisov Signed

[PATCH v2 15/29] migration/ram: Add support for 'fixed-ram' outgoing migration

From: Nikolay Borisov Implement the outgoing migration side for the 'fixed-ram' capability. A bitmap is introduced to track which pages have been written in the migration file. Pages are written at a fixed location for every ramblock. Zero pages are ignored as they'd be zero in the destination m

[PATCH v2 17/29] tests/qtest: migration-test: Add tests for fixed-ram file-based migration

From: Nikolay Borisov Add basic tests for 'fixed-ram' migration. Signed-off-by: Nikolay Borisov Signed-off-by: Fabiano Rosas --- tests/qtest/migration-test.c | 39 1 file changed, 39 insertions(+) diff --git a/tests/qtest/migration-test.c b/tests/qtest/mi

[PATCH v2 25/29] migration/multifd: Support outgoing fixed-ram stream format

The new fixed-ram stream format uses a file transport and puts ram pages in the migration file at their respective offsets and can be done in parallel by using the pwritev system call which takes iovecs and an offset. Add support to enabling the new format along with multifd to make use of the thr

[PATCH v2 21/29] migration/multifd: Add pages to the receiving side

Currently multifd does not need to have knowledge of pages on the receiving side because all the information needed is within the packets that come in the stream. We're about to add support to fixed-ram migration, which cannot use packets because it expects the ramblock section in the migration fi

[PATCH v2 05/29] migration: Introduce global_state_store_once

There are some situations during migration when we want to change the runstate of the VM, but don't actually want the new runstate to be put on the wire to be restored on the destination VM. In those cases, the pattern is to use global_state_store() to save the state for migration before changing i

[PATCH v2 19/29] migration/multifd: Add outgoing QIOChannelFile support

Allow multifd to open file-backed channels. This will be used when enabling the fixed-ram migration stream format which expects a seekable transport. The QIOChannel read and write methods will use the preadv/pwritev versions which don't update the file offset at each call so we can reuse the fd wi

[PATCH v2 12/29] migration/qemu-file: add utility methods for working with seekable channels

From: Nikolay Borisov Add utility methods that will be needed when implementing 'fixed-ram' migration capability. qemu_file_is_seekable qemu_put_buffer_at qemu_get_buffer_at qemu_set_offset qemu_get_offset Signed-off-by: Nikolay Borisov Signed-off-by: Fabiano Rosas --- fixed total_transferred

[PATCH v2 00/29] migration: File based migration with multifd and fixed-ram

Hi, Here's the migration to file using fixed offsets for each RAM page. We're calling it fixed-ram migration. There's 3 big pieces in this series: 1) Fixed-ram: The single-threaded (no multifd) implementation of the fixed-ram migration. This adds: - infrastructure for preadv/pwritev; - a bit

[PATCH v2 09/29] io: add and implement QIO_CHANNEL_FEATURE_SEEKABLE for channel file

From: Nikolay Borisov Add a generic QIOChannel feature SEEKABLE which would be used by the qemu_file* apis. For the time being this will be only implemented for file channels. Signed-off-by: Nikolay Borisov Signed-off-by: Fabiano Rosas Reviewed-by: Daniel P. Berrangé --- include/io/channel.h

[PATCH v2 01/29] tests/qtest: migration events

From: Steve Sistare Define a state object to capture events seen by migration tests, to allow more events to be captured in a subsequent patch, and simplify event checking in wait_for_migration_pass. No functional change. Signed-off-by: Steve Sistare --- tests/qtest/migration-helpers.c | 24 +

[PATCH v2 06/29] migration: Add auto-pause capability

Add a capability that allows the management layer to delegate to QEMU the decision of whether to pause a VM and perform a non-live migration. Depending on the type of migration being performed, this could bring performance benefits. Note that the capability is enabled by default but at this moment

[PATCH v2 04/29] migration: Return the saved state from global_state_store

There is a pattern of calling runstate_get() to store the current runstate and calling global_state_store() to save the current runstate for migration. Since global_state_store() also calls runstate_get(), make it return the runstate instead. Signed-off-by: Fabiano Rosas --- include/migration/gl

Re: [PATCH 1/2] ide/pci.c: introduce pci_ide_update_mode() function

Am 22. Oktober 2023 22:06:30 UTC schrieb Bernhard Beschow : > > >Am 19. Oktober 2023 13:04:51 UTC schrieb Mark Cave-Ayland >: >>This function reads the value of the PCI_CLASS_PROG register for PCI IDE >>controllers and configures the PCI BARs and/or IDE ioports accordingly. >> >>In the case whe

Re: [PATCH V1 4/4] cpr: reboot mode

On 10/23/2023 3:05 PM, Peter Xu wrote: > On Mon, Oct 23, 2023 at 02:51:50PM -0400, Steven Sistare wrote: >> On 10/23/2023 2:29 PM, Steven Sistare wrote: >>> On 10/23/2023 11:39 AM, Peter Xu wrote: On Thu, Oct 19, 2023 at 01:47:46PM -0700, Steve Sistare wrote: > Add the cpr-reboot migration

Re: [PATCH v3 0/8] PMBus fixes and new functions

Titus Rwantare writes: > This patch series contains fixes and improvements to PMBus support in QEMU. > > The following has been added: >- Support for block receive >- Support for devices with fans >- Support for the VCAP register for devices with onboard energy storage >- A bitf

Re: [PATCH V1 4/4] cpr: reboot mode

On Mon, Oct 23, 2023 at 02:51:50PM -0400, Steven Sistare wrote: > On 10/23/2023 2:29 PM, Steven Sistare wrote: > > On 10/23/2023 11:39 AM, Peter Xu wrote: > >> On Thu, Oct 19, 2023 at 01:47:46PM -0700, Steve Sistare wrote: > >>> Add the cpr-reboot migration mode. Usage: > >>> > >>> $ qemu-system-$

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