[PATCH v3 70/90] target/sparc: Move gen_fop_FF insns to decodetree

Move FSQRTs, FiTOs, FsTOi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 47 --- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index

[PATCH v3 78/90] target/sparc: Move gen_fop_FD insns to decodetree

Move FdTOs, FdTOi, FxTOs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 51 +-- 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index

[PATCH v3 79/90] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree

Note that gen_ne_fop_DF was incorrectly named and does pass env. The two sets of helpers should have been unified. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 67 --- 2 files changed, 30 insertions(+), 40

[PATCH v3 89/90] target/sparc: Convert FZERO, FONE to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 +++ 2 files changed, 45 insertions(+), 29 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d03bddc689..955647db71 1006

[PATCH v3 75/90] target/sparc: Move gen_fop_QQQ insns to decodetree

Move FADDq, FSUBq, FMULq, FDIVq. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 52 +++ 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode

[PATCH v3 23/90] target/sparc: Move RDWIM, RDPR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 360 +++--- 2 files changed, 244 insertions(+), 138 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index ac545c6821..99e4f8f671 1

[PATCH v3 22/90] target/sparc: Move RDPSR, RDHPR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 target/sparc/translate.c | 112 -- 2 files changed, 80 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1b084c5b97..ac545c6821 10

[PATCH v3 74/90] target/sparc: Move gen_fop_DDD insns to decodetree

Move FADDd, FSUBd, FMULd, FDIVd. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 55 --- 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode

[PATCH v3 83/90] target/sparc: Move FdTOq, FxTOq to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 47 ++- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a444819d6c..41bf7a2a33 10064

[PATCH v3 86/90] target/sparc: Convert FCMP, FCMPE to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++ target/sparc/translate.c | 145 +++--- 2 files changed, 96 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 646acad75d..1af7bb05b3 1006

[PATCH v3 12/90] target/sparc: Move BPcc and Bicc to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 117 +++--- 2 files changed, 61 insertions(+), 60 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a5f5d2681e..15cd975f4e 1006

[PATCH v3 30/90] target/sparc: Move ADDC to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 162 -- 2 files changed, 105 insertions(+), 58 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index abfcaeb692..959397e62f 1006

[PATCH v3 34/90] target/sparc: Move UDIVX, SDIVX to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 23 ++- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index ca54a090a3..94a85e488a 100644 --- a/target/s

[PATCH v3 24/90] target/sparc: Move RDTBR, FLUSHW to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 + target/sparc/translate.c | 23 +++ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 99e4f8f671..7fb5fa3b3a 100644 --- a/targe

[PATCH v3 60/90] target/sparc: Move ARRAY* to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 --- 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 04715cf068..1262b5c7bb 1006

[PATCH v3 14/90] target/sparc: Move FBPfcc and FBfcc to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 102 +++--- 2 files changed, 43 insertions(+), 63 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 838f4cdb1d..9ab3f2eb82 1006

[PATCH v3 84/90] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 140 +- 2 files changed, 50 insertions(+), 93 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 41bf7a2a33..1b14a49850 10064

[PATCH v3 55/90] target/sparc: Move simple fp load/store to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 19 target/sparc/translate.c | 194 ++ 2 files changed, 113 insertions(+), 100 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 96c6e19fc9..30eeed84c2

[PATCH v3 57/90] target/sparc: Move LDFSR, STFSR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 + target/sparc/translate.c | 152 +++--- 2 files changed, 64 insertions(+), 92 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6e8416520a..850b1a3845 10064

[PATCH v3 64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 91 +-- 2 files changed, 56 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 63fbc19fc9..4e4336a4c5 1006

[PATCH v3 11/90] target/sparc: Move CALL to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 34 +- 2 files changed, 18 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5811a679db..a5f5d2681e 100644 ---

[PATCH v3 51/90] target/sparc: Move SWAP, SWAPA to decodetree

Remove gen_swap_asi. Rename gen_swap_asi0 to gen_swap_asi. Merge gen_swap into gen_swap_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 58 +-- 2 files changed, 29 insertions(+), 33 deletions(-) diff -

[PATCH v3 69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree

Move FPACK32, FALIGNDATA, BSHUFFLE. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 101 -- 2 files changed, 55 insertions(+), 49 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.dec

[PATCH v3 77/90] target/sparc: Move FDMULQ to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +-- 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 54c9c38736..aafbd68867 100644

[PATCH v3 80/90] target/sparc: Move FqTOs, FqTOi to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 48 +-- 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 3ad598a08b..431152dde9 10064

[PATCH v3 85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 192 -- 2 files changed, 91 insertions(+), 113 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1b14a49850..646acad75d 10

[PATCH v3 53/90] target/sparc: Move PREFETCH, PREFETCHA to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 8 ++-- target/sparc/translate.c | 14 ++ 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f4c55db313..96c6e19fc9 100644 --- a/target/sparc

[PATCH v3 49/90] target/sparc: Move asi integer load/store to decodetree

Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 + target/sparc/translate.c | 128 +- 2 files changed, 48 insertions(+), 111 deletions(-) di

[PATCH v3 88/90] target/sparc: Move FPACK16, FPACKFIX to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 55 --- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f557371e56..d03bddc689 10064

[PATCH v3 63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 ++ target/sparc/translate.c | 92 +-- 2 files changed, 62 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9ea5e09dfc..63fbc19fc9 1

[PATCH v3 76/90] target/sparc: Move FSMULD to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 43 +-- 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0753bbef2d..54c9c38736 100644

[PATCH v3 62/90] target/sparc: Move BMASK to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 +- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 855627b55e..9ea5e09dfc 100644 --- a/target/spa

[PATCH v3 35/90] target/sparc: Move UDIV, SDIV to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/helper.c | 4 --- target/sparc/translate.c | 55 ++- 3 files changed, 28 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decod

[PATCH v3 43/90] target/sparc: Move DONE, RETRY to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 99 +++ 2 files changed, 40 insertions(+), 62 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 629547326b..bbddae6ce0 10064

[PATCH v3 45/90] target/sparc: Drop ifdef around get_asi and friends

Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 187 +++ 1 file changed, 70 insertions(+), 117 deletions(-) diff --git a/target/sparc/tran

[PATCH v3 81/90] target/sparc: Move FqTOd, FqTOx to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 49 +-- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 431152dde9..908b2ba408 10064

[PATCH v3 65/90] target/sparc: Use tcg_gen_vec_{add,sub}*

Replace the local helpers for the same integer operations. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 12 target/sparc/translate.c | 15 +- target/sparc/vis_helper.c | 59 --- 3 files changed, 7 insertions(+), 79 deletio

[PATCH v3 73/90] target/sparc: Move gen_fop_FFF insns to decodetree

Move FADDs, FSUBs, FMULs, FDIVs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 +++ 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode

[PATCH v3 50/90] target/sparc: Move LDSTUB, LDSTUBA to decodetree

Remove gen_ldstub_asi. Rename gen_ldstub_asi0 to gen_ldstub_asi. Merge gen_ldstub into gen_ldstub_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 target/sparc/translate.c | 46 +++ 2 files changed, 26 insertions(+), 24 deletions

[PATCH v3 66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree

Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s, FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 16 ++ target/sparc/translate.c | 116 ++ 2 files changed,

[PATCH v3 46/90] target/sparc: Split out ldst functions with asi pre-computed

As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 215 ++- 1 file changed, 123 insertions(+), 92 deletions(-) diff --git a/target/sparc/tran

[PATCH v3 33/90] target/sparc: Move SUBC to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 147 +- 2 files changed, 98 insertions(+), 50 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f214baf465..ca54a090a3 10064

[PATCH v3 52/90] target/sparc: Move CASA, CASXA to decodetree

Remove gen_cas_asi, gen_casx_asi. Rename gen_cas_asi0 to gen_cas_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 target/sparc/translate.c | 71 +++ 2 files changed, 35 insertions(+), 43 deletions(-) diff --git a/target/sparc/in

[PATCH v3 54/90] target/sparc: Split out fp ldst functions with asi precomputed

Take the operation size from the MemOp instead of a separate parameter. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 136 ++- 1 file changed, 78 insertions(+), 58 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c

[PATCH v3 08/90] target/sparc: Remove sparcv7 cpu features

The oldest supported cpu is the microsparc 1; all other cpus use CPU_DEFAULT_FEATURES. Remove the features that must always be present for sparcv7: FLOAT, SWAP, FLUSH, FSQRT, FMUL. Signed-off-by: Richard Henderson --- linux-user/sparc/target_syscall.h | 6 +- target/sparc/cpu.h

[PATCH v3 39/90] target/sparc: Move POPC to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 +++ 2 files changed, 12 insertions(+), 47 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8f4881a776..667067822f 1006

[PATCH v3 58/90] target/sparc: Merge LDFSR, LDXFSR implementations

Combine the helper to a single set_fsr(). Perform the mask and merge inline. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 3 +-- target/sparc/fop_helper.c | 17 ++-- target/sparc/translate.c | 42 --- 3 files changed, 16 inser

[PATCH v3 48/90] target/sparc: Move simple integer load/store to decodetree

Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 + target/sparc/translate.c | 196 +++--- 2 files changed, 142 insertions(+), 76 deletions(-) diff --git a/target

[PATCH v3 87/90] target/sparc: Move FPCMP* to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 target/sparc/translate.c | 94 +-- 2 files changed, 50 insertions(+), 53 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1af7bb05b3..f557371e56 100

[PATCH v3 61/90] target/sparc: Move ADDRALIGN* to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 ++- 2 files changed, 34 insertions(+), 25 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1262b5c7bb..855627b55e 1006

[PATCH v3 82/90] target/sparc: Move FiTOq, FsTOq to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 44 +-- 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 908b2ba408..a444819d6c 10064

[PATCH v3 44/90] target/sparc: Split out resolve_asi

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 25 + 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2e2df42c53..f71c70a897 100644 --- a/target/sparc/translate.c +++ b/target/sparc/tr

[PATCH v3 10/90] target/sparc: Define AM_CHECK for sparc32

Define as false, which allows some ifdef removal. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 21 + 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 080bc5f8a2..9eb2b7e52f 100644 --- a

[PATCH v3 47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX

Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 48 +--- 1 file changed, 40 insertions(+), 8 deletions(-) diff --git a/target/sparc/translate.c b/targe

[PATCH v3 90/90] target/sparc: Remove disas_sparc_legacy

All instructions are now converted. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 145 +-- 1 file changed, 1 insertion(+), 144 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 922d9e6021..c71fb64aaa 100644

[PATCH v3 71/90] target/sparc: Move gen_fop_DD insns to decodetree

Move FSQRTd, FxTOd, FdTOx. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 50 +-- 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index

[PATCH v3 59/90] target/sparc: Move EDGE* to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++- target/sparc/translate.c | 269 -- 2 files changed, 131 insertions(+), 160 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 850b1a3845..04715cf068

[PATCH v3 67/90] target/sparc: Move gen_ne_fop_DDD insns to decodetree

Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16, FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d, FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d, FPSUB16d, FPSUB32d, FXNORd, FXORd. Signed-off-by: Richard Henderson --- target/sparc/insns.decode |

[PATCH v3 72/90] target/sparc: Move FSQRTq to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 39 +++ 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d8a49838a0..6994312909 100644

[PATCH v3 21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 356 -- 2 files changed, 249 insertions(+), 129 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0517f5591b..1b084c5b97 1

[PATCH v3 42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 target/sparc/translate.c | 35 +-- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c2bf5f78e3..629547326b 100644

[PATCH v3 68/90] target/sparc: Move PDIST to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +-- 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 75832ea503..9ac2a715c0 100644

[PATCH v3 40/90] target/sparc: Convert remaining v8 coproc insns to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 11 +++ target/sparc/translate.c | 32 ++-- 2 files changed, 17 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 667067822f..1303df92a7 100

[PATCH v3 41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 126 -- 2 files changed, 88 insertions(+), 45 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1303df92a7..c2bf5f78e3 100

[PATCH v3 26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 +++ target/sparc/translate.c | 61 ++- 2 files changed, 38 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d7e7f0c577..5ba71c3d84

[PATCH v3 56/90] target/sparc: Move asi fp load/store to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 51 ++-- target/sparc/translate.c | 169 -- 2 files changed, 79 insertions(+), 141 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 30eeed84c2..6e84

[PATCH v3 37/90] target/sparc: Move SLL, SRL, SRA to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 14 +++ target/sparc/translate.c | 182 -- 2 files changed, 92 insertions(+), 104 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 39099ae14b..c2a44e0130 10

[PATCH v3 01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC

With pairs of jmp+rett, pc == DYNAMIC_PC_LOOKUP and npc == DYNAMIC_PC. Make sure that we exit for interrupts. Cc: qemu-sta...@nongnu.org Fixes: 633c42834c7 ("target/sparc: Introduce DYNAMIC_PC_LOOKUP") Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/translate.c |

[PATCH v3 31/90] target/sparc: Move MULX to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 6 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 959397e62f..694d2c3648 100644 --- a/target/sparc/insns.decode ++

[PATCH v3 29/90] target/sparc: Move basic arithmetic to decodetree

Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 178 -- 2 files changed, 87 insertions(+), 103 deletions(-) diff --git a/target/sparc/insns.decode b/target/spa

[PATCH v3 20/90] target/sparc: Move Tcc to decodetree

Use the new delay_exceptionv function in the implementation. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 target/sparc/translate.c | 155 +++--- 2 files changed, 89 insertions(+), 79 deletions(-) diff --git a/target/sparc/insns.deco

[PATCH v3 36/90] target/sparc: Move TADD, TSUB, MULS to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++ target/sparc/helper.c | 4 target/sparc/translate.c | 48 ++- 3 files changed, 29 insertions(+), 30 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.

[PATCH v3 02/90] target/sparc: Implement check_align inline

Emit the exception at the end of the translation block, so that the non-exception case can fall through. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 1 - target/sparc/ldst_helper.c | 7 ++-- target/sparc/translate.c | 68 +- 3 files c

[PATCH v3 19/90] target/sparc: Move SETHI to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 6 + target/sparc/translate.c | 50 --- 2 files changed, 21 insertions(+), 35 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9ab3f2eb82..f6f5401b10 10

[PATCH v3 28/90] target/sparc: Move WRTBR, WRHPR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 target/sparc/translate.c | 110 +++--- 2 files changed, 65 insertions(+), 54 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d7bd6cd718..0c02a269e2 10

[PATCH v3 17/90] target/sparc: Merge gen_branch_[an] with only caller

Signed-off-by: Richard Henderson --- target/sparc/translate.c | 73 +--- 1 file changed, 30 insertions(+), 43 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b8d51d6d64..503598ed93 100644 --- a/target/sparc/translate.c +++ b

[PATCH v3 16/90] target/sparc: Merge gen_fcond with only caller

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 22 -- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2664db302d..b8d51d6d64 100644 --- a/target/sparc

[PATCH v3 13/90] target/sparc: Move BPr to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 63 ++- 2 files changed, 25 insertions(+), 41 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 15cd975f4e..838f4cdb1d 10064

[PATCH v3 07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties

Use symbols not integer constants for the bit positions. Signed-off-by: Richard Henderson --- target/sparc/cpu.c | 42 -- 1 file changed, 28 insertions(+), 14 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ba96ae225..e4d1c552e5 1

[PATCH v3 04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO

Always use TSO, per the Oracle 2015 manual. This is slightly less restrictive than the TCG_MO_ALL default, and happens to match the i386 model, which will eliminate a few extra barriers on that host. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2

[PATCH v3 27/90] target/sparc: Move WRWIM, WRPR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 21 +++ target/sparc/translate.c | 350 +++--- 2 files changed, 235 insertions(+), 136 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5ba71c3d84..d7bd6cd718 1

[PATCH v3 25/90] target/sparc: Move WRASR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 target/sparc/translate.c | 353 +- 2 files changed, 225 insertions(+), 159 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7fb5fa3b3a..d7e7f0c577

[PATCH v3 06/90] target/sparc: Define features via cpu-feature.h.inc

Manage feature bits automatically. Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 32 +--- target/sparc/cpu-feature.h.inc | 19 +++ 2 files changed, 32 insertions(+), 19 deletions(-) create mode 100644 target/sparc/cpu-feature.h

[PATCH v3 05/90] configs: Enable MTTCG for sparc, sparc64

This will be of small comfort to sparc64, because both sun4u and sun4v board models force max_cpus = 1. But it does enable actual smp for sparc32 sun4m. Signed-off-by: Richard Henderson --- configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + 2 files changed, 2 i

[PATCH v3 38/90] target/sparc: Move MOVcc, MOVR to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 116 -- 2 files changed, 64 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c2a44e0130..8f4881a776 1006

[PATCH v3 18/90] target/sparc: Pass DisasCompare to advance_jump_cond

Fold the condition into the branch or movcond when possible. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 31 +-- 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 503598ed93..d

[PATCH v3 15/90] target/sparc: Merge gen_cond with only caller

Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sparc/translate.c | 23 --- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 69e85b1842..2664db302d 100644 --- a/target/spar

[PATCH v3 09/90] target/sparc: Add decodetree infrastructure

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 ++- target/sparc/meson.build | 3 ++ 3 files changed, 55 insertions(+), 22 deletions(-) create mode 100644 target/sparc/insns.decode diff --git a/target

[PATCH v3 00/90] target/sparc: Convert to decodetree

Changes for v3: * Relax v8 simm13 checking for Tcc. * Split gen_op_addx_int and reorganize to not clobber current cc_op. * Do not replicate decoding for insns that can set cc_op. Changes for v2: * Fixes for JMPL, RETT, SAVE and RESTORE. * Fixes for FMOV etc, which had lost gen_op_clear_i

[PATCH v3 32/90] target/sparc: Move UMUL, SMUL to decodetree

Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 21 +++-- 2 files changed, 5 insertions(+), 18 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 694d2c3648..f214baf465 100644 --- a/target/spar

[PATCH v3 03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi

Always use cpu_raise_exception_ra with GETPC for unwind. Signed-off-by: Richard Henderson --- target/sparc/ldst_helper.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 246de86c98..09066d5487 100644 ---

Re: [PULL v2 29/53] hw/i386: Remove now redundant TYPE_ACPI_GED_X86

Hi Bernhard, On 19/10/2023 11:33, Bernhard Beschow wrote: Am 18. Oktober 2023 17:38:33 UTC schrieb Salil Mehta : Hello, Hi Salil, Can we assume that every machine type will have all the features which a GED Device can multiplex present together? like will Memory and CPU Hotplug makes se

[PATCH v3 6/6] target/riscv/tcg: handle profile MISA bits

The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the user set the bit, doesn't matter if to 'true' or 'false', ignore it. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set o

[PATCH v3 5/6] target/riscv/tcg: add riscv_cpu_write_misa_bit()

We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cp

[PATCH v3 0/6] riscv: RVA22U64 profile support

Based-on: 20231017221226.136764-1-dbarb...@ventanamicro.com ("[PATCH v2 0/6] riscv: zicntr/zihpm flags and disable support") Hi, The most notable change in this new version is that we're back to enabling/disabling profile extensions during the property set() callback, instead of doing an extra st

[PATCH v3 4/6] target/riscv/tcg: add MISA user options hash

We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice f

[PATCH v3 1/6] target/riscv: add rva22u64 profile definition

The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of fe

[PATCH v3 2/6] target/riscv/kvm: add 'rva22u64' flag as unavailable

KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this

[PATCH v3 3/6] target/riscv/tcg: add user flag for profile support

The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG w

Re: [PATCH V1 1/4] migration: mode parameter

Hi Daniel, does the addition of MigMode in qdev below look OK to you? It exactly mirrors qdev_prop_blockdev_on_error + DEFINE_PROP_BLOCKDEV_ON_ERROR. I realize I need to add: QEMU_BUILD_BUG_ON(sizeof(MigMode) != sizeof(int)); and I need to delete "exec" from the .description. I will cc you wh

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