On 18/10/2023 21.27, Fabiano Rosas wrote:
Accept the QTEST_QEMU_MACHINE_TYPE environment variable to take a
machine type to use in the tests.
The full machine type is recognized (e.g. pc-q35-8.2). Aliases
(e.g. pc) are also allowed and resolve to the latest machine version
for that alias, or, if
As per the Priv spec: "The R, W, and X fields form a collective WARL
field for which the combinations with R=0 and W=1 are reserved."
However currently such writes are not ignored as ought to be. The
combinations with RW=01 are allowed only when the Smepmp extension
is enabled and mseccfg.MML is se
As per the Priv and Smepmp specifications, certain bits such as the 'L'
bit of pmp entries and mseccfg.MML can only be cleared upon reset and it
is necessary to do so to allow 'M' mode firmware to correctly reinitialize
the pmp/smpemp state across reboots. As required by the spec, also clear
the 'A
Victor Toso writes:
> Hi,
>
> On Wed, Oct 18, 2023 at 01:47:56PM +0200, Markus Armbruster wrote:
>> Victor Toso writes:
>>
>> > The goal of this patch is converge discussions into a documentation,
>> > to make it easy and explicit design decisions, known issues and what
>> > else might help a p
From: Himanshu Chauhan
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan
Signed-off-by: Mayuresh Chitale
Reviewed-by: Daniel Henrique Barboza
---
Changes in v2:
On 10/18/23 15:28, Eric Auger wrote:
Hi Cédric,
On 10/17/23 18:14, Cédric Le Goater wrote:
From: Liu Yi L
This patch modifies pci_setup_iommu() to set PCIIOMMUOps
instead of setting PCIIOMMUFunc. PCIIOMMUFunc is used to
get an address space for a PCI device in vendor specific
way. The PCIIOMM
On 18/10/2023 21.27, Fabiano Rosas wrote:
We have strict rules around migration compatibility between different
QEMU versions but no test to validate the migration state between
different binaries.
Add infrastructure to allow running the migration tests with two
different QEMU binaries as migrat
Hi Alex,
On 10/18/23 23:42, Alex Williamson wrote:
> On Wed, 11 Oct 2023 19:52:29 +0200
> Eric Auger wrote:
>
>> Now we retrieve the usable IOVA ranges from the host,
>> we now the physical IOMMU aperture and we can remove
> s/now/use/?
>
>> the assumption of 64b IOVA space when calling
>> vfio_h
Hi Alex,
On 10/18/23 21:07, Alex Williamson wrote:
> On Wed, 11 Oct 2023 19:52:19 +0200
> Eric Auger wrote:
>
>> Collect iova range information if VFIO_IOMMU_TYPE1_INFO_CAP_IOVA_RANGE
>> capability is supported.
>>
>> This allows to propagate the information though the IOMMU MR
>> set_iova_ranges
On 18/10/2023 21.27, Fabiano Rosas wrote:
Change the x86_64 to use the q35 machines in tests from now on. Keep
testing the pc macine on 32bit.
Signed-off-by: Fabiano Rosas
---
this could affect bisecting, so I put it in separate patch to be
easier to revert
---
tests/qtest/migration-test.c |
On 18/10/2023 21.27, Fabiano Rosas wrote:
We're about to enable the x86_64 tests to run with the q35 machine,
but that machine does not work with the program we use to dirty the
memory for the tests.
The issue is that QEMU needs to guess the geometry of the "disk" we
give to it and the guessed g
Victor Toso writes:
> Hi Markus,
>
> Sorry the delay on reply here.
>
> On Thu, Sep 21, 2023 at 01:06:01PM +0200, Markus Armbruster wrote:
>> Victor Toso writes:
>>
>> > This generator has two goals:
>> > 1. Mechanical validation of QAPI examples
>> > 2. Generate the examples in a JSON format
On 18/10/2023 21.27, Fabiano Rosas wrote:
Stop relying on defaults and select a machine explicitly for every
architecture.
This is a prerequisite for being able to select machine types for
migration using different QEMU binaries for source and destination.
Signed-off-by: Fabiano Rosas
---
te
On 18/10/2023 21.27, Fabiano Rosas wrote:
When using two different QEMU binaries for migration testing, we'll
need to find what is the machine version that will work with both
binaries. Add a helper for that.
Reviewed-by: Juan Quintela
Signed-off-by: Fabiano Rosas
---
tests/qtest/migration-h
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/spapr_xive.c | 12 ++--
1
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
In order to make the next commit trivial, move sysbus_init_mmio()
calls just before the corresponding sysbus_mmio_map() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/intc/spapr_xive.c | 6 +++---
1 file changed, 3 insertions(+), 3 dele
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/pnv.c | 5 ++---
1 file changed, 2
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
Just map it without using the SysBus API.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ppc/pnv_xscom.c | 4 +---
1 file change
Victor Toso writes:
> On Wed, Oct 18, 2023 at 01:00:07PM +0200, Markus Armbruster wrote:
>> Victor Toso writes:
>>
>> > flake8 complained:
>> > ./main.py:60:1: E302 expected 2 blank lines, found 1
>> >
>> > Which is simple enough. My vim has black [0] enabled by default, so it
>> > did some
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
In order to make the next commit trivial, move sysbus_init_mmio()
calls just before the corresponding sysbus_mmio_map() calls.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/pnv_xscom.h | 2 +-
hw/ppc/pnv.c | 9 +++---
On 18/10/2023 15.30, Philippe Mathieu-Daudé wrote:
pnv_xscom_realize() is not used to *realize* QDev object, rename
it as pnv_xscom_init(). The Error** argument is unused: remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
include/hw/ppc/pnv_xscom.h | 2 +-
hw/ppc/pnv.c | 18
Philippe Mathieu-Daudé writes:
> On 18/10/23 15:02, Daniel P. Berrangé wrote:
>> On Wed, Oct 18, 2023 at 02:37:45PM +0200, Markus Armbruster wrote:
>>> Daniel P. Berrangé writes:
>>>
If printing a QAPI schema object for debugging we get the classname and
a hex value for the instance:
>
On 18/10/23 7:58 pm, Fabiano Rosas wrote:
Het Gala writes:
Fabiano, would your below commits impact this patchset 'make check'
tests ? Because you have added tests for file based migration, which is
still not included in this patchset.
AFAICS, the tests shouldn't break.
I tried two builds
On 18/10/2023 21.11, Vladimir Sementsov-Ogievskiy wrote:
We open ipv4 listening socket. But "localhost" in qemu parameters may
load to Qemu trying to connect with ipv6 and fail with "Connection
refused". Force ipv4 by using ipv4 ip address.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
test
On 10/14/23 03:01, Paolo Bonzini wrote:
@@ -179,6 +180,9 @@
#define p_66_f3_f2.valid_prefix = P_66 | P_F3 | P_F2,
#define p_00_66_f3_f2 .valid_prefix = P_00 | P_66 | P_F3 | P_F2,
+static X86OpEntry illegal_opcode =
+X86_OP_ENTRY0(illegal);
const.
+static void gen_ARPL(DisasContex
On 10/14/23 03:01, Paolo Bonzini wrote:
The new x86 decoder wants to compute EFLAGS before writeback, which
can be an issue for some instructions such as ARPL. Extract code
to compute the EFLAGS without clobbering CC_SRC, in case the ARPL
memory write causes a fault.
Signed-off-by: Paolo Bonzin
在 2023/10/19 上午7:47, Richard Henderson 写道:
On 10/18/23 01:59, Song Gao wrote:
Some users may not need LSX/LASX, this patch allows the user
enable/disable LSX/LASX features.
e.g
'-cpu max,lsx=on,lasx=on' (default);
'-cpu max,lsx=on,lasx=off' (enabled LSX);
'-cpu max,lsx=off,lasx=on'
On 10/14/23 03:01, Paolo Bonzini wrote:
gen_jcc() has been changed to accept a relative offset since the
new decoder was written. Adjust the J operand, which is meant
to be used with jump instructions such as gen_jcc(), to not
include the program counter and to not truncate the result, as
both o
On 10/14/23 03:01, Paolo Bonzini wrote:
+[0x28] = X86_OP_ENTRY2(SUB, E,b, G,b),
+[0x29] = X86_OP_ENTRY2(SUB, E,v, G,v),
+[0x2A] = X86_OP_ENTRY2(SUB, G,b, E,b),
+[0x2B] = X86_OP_ENTRY2(SUB, G,v, E,v),
+[0x2C] = X86_OP_ENTRY2(SUB, 0,b, I,b), /* AL, Ib */
+[0x2D] = X86_OP_E
>-Original Message-
>From: Cédric Le Goater
>Sent: Wednesday, October 18, 2023 4:04 PM
>Subject: Re: [PATCH v2 02/27] vfio: Introduce base object for VFIOContainer and
>targetted interface
>
>On 10/18/23 04:41, Duan, Zhenzhong wrote:
>> Hi Cédric,
>>
>>> -Original Message-
>>> From
From: Matheus Tavares Bernardino
As docs/devel/loads-stores.rst states:
``GETPC()`` should be used with great care: calling
it in other functions that are *not* the top level
``HELPER(foo)`` will cause unexpected behavior. Instead, the
value of ``GETPC()`` should be read from the helper
The following changes since commit deaca3fd30d3a8829160f8d3705d65ad83176800:
Merge tag 'pull-vfio-20231018' of https://github.com/legoater/qemu into
staging (2023-10-18 06:21:15 -0400)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20231018
Of the changes in this commit, the changes in `HELPER(commit_hvx_stores)()`
are less obvious. They are required because of some macro invocations like
SCATTER_OP_WRITE_TO_MEM().
e.g.:
In file included from ../target/hexagon/op_helper.c:31:
../target/hexagon/mmvec/macros.h:205:18: error:
On Wed, 18 Oct 2023 21:40:23 +0900,
Geert Uytterhoeven wrote:
>
> The new Linux SH7750 clock driver uses the registers for power-down
> mode control, causing a crash:
>
> byte read to SH7750_STBCR_A7 (0x1fc4) not supported
> Aborted (core dumped)
>
> Fix this by adding suppor
On Wed, 18 Oct, 2023, 11:14 pm Michael S. Tsirkin, wrote:
> On Wed, Oct 18, 2023 at 11:08:11PM +0530, Ani Sinha wrote:
> >
> >
> > On Wed, 18 Oct, 2023, 5:35 pm Michael S. Tsirkin,
> wrote:
> >
> > On Tue, Sep 12, 2023 at 05:36:50PM +0530, Ani Sinha wrote:
> > > PAE mode in x86 supports
On 10/14/23 03:01, Paolo Bonzini wrote:
+static void gen_CMPccXADD(DisasContext *s, CPUX86State *env, X86DecodedInsn
*decode)
+{
+TCGv z_tl = tcg_constant_tl(0);
+TCGLabel *label_top = gen_new_label();
+TCGLabel *label_bottom = gen_new_label();
+TCGv oldv = tcg_temp_new();
+T
On 10/18/2023 9:27 PM, Michael S. Tsirkin wrote:
On Sat, Oct 07, 2023 at 02:58:19AM -0400, Xiaoyao Li wrote:
pc_machine_kvm_type() was introduced by commit e21be724eaf5 ("i386/xen:
add pc_machine_kvm_type to initialize XEN_EMULATE mode") to do Xen
specific initialization by utilizing kvm_type me
On 10/14/23 03:01, Paolo Bonzini wrote:
The implementation was validated with OpenSSL and with the test vectors in
https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs.
The instructions provide a ~25% improvement on hashing a 64 MiB file:
runtime goes down from 1.8 se
On 10/15/23 23:31, Paolo Bonzini wrote:
Make all items of config-host.h consistent. To keep the
--disable-coroutine-pool
code visible to the compiler, mutuate the IS_ENABLED() macro from Linux.
Signed-off-by: Paolo Bonzini
---
include/qemu/compiler.h | 15 +++
meson.build
From: David Woodhouse
The interrupt from timer 0 in legacy mode is supposed to go to IRQ 0 on
the i8259 and IRQ 2 on the I/O APIC. The generic x86 GSI handling can't
cope with IRQ numbers differing between the two chips (despite it also
being the case for PCI INTx routing), so add a special case
On 10/18/23 06:30, Philippe Mathieu-Daudé wrote:
Hi,
There is no point in exposing an internal MMIO region via
SysBus and directly mapping it in the very same device.
This series replaces a sequence of:
- sysbus_init_mmio()
- sysbus_mmio_map()
by a single call to memory_region_add_subregion().
On 10/18/23 01:59, Song Gao wrote:
Some users may not need LSX/LASX, this patch allows the user
enable/disable LSX/LASX features.
e.g
'-cpu max,lsx=on,lasx=on' (default);
'-cpu max,lsx=on,lasx=off' (enabled LSX);
'-cpu max,lsx=off,lasx=on' (error, need lsx=on);
'-cpu max,lsx=off'
From: Mikulas Patocka
QEMU mips userspace emulation crashes with "qemu: unhandled CPU exception
0x15 - aborting" when one of the integer arithmetic instructions detects
an overflow.
This patch fixes it so that it delivers SIGFPE with FPE_INTOVF instead.
Cc: qemu-sta...@nongnu.org
Signed-off-by:
The previous change, 2d385be6152, assumed !PAGE_VALID meant that
the page would be unmapped by the elf image. However, since we
reserved the entire image space via mmap, PAGE_VALID will always
be set. Instead, assume PROT_NONE for the same condition.
Furthermore, assume bss is only ever present
Do not return a valid signal number in one domain
when given an invalid signal number in the other domain.
Acked-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 72 -
1 file changed, 38 insertions(+), 34 deletions(-)
diff
Do not assert success, but return any failure received.
Additionally, fix the method of earlier error return in target_munmap.
Reported-by: Andreas Schwab
Signed-off-by: Richard Henderson
---
linux-user/mmap.c | 30 +-
1 file changed, 17 insertions(+), 13 deletions(-
Install the host signal handler at the same time we are
probing the target signals for SIG_IGN/SIG_DFL. Ignore
unmapped target signals.
Acked-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 42 ++
1 file changed, 22 insertions
The set of fatal signals is really immaterial. If one arrives,
and is unhandled, then the qemu process dies and the parent gets
the correct signal.
It is only for those signals which we would like to perform a
guest core dump instead of a host core dump that we need to catch.
Acked-by: Helge Del
From: Jiajie Chen
Since support for LSX and LASX is landed in QEMU recently, we can update
HWCAPS accordingly.
Signed-off-by: Jiajie Chen
Reviewed-by: Richard Henderson
Message-Id: <20231001085315.1692667-...@jia.je>
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 8
1 f
From: Helge Deller
If there is an internal program error in the qemu source code which
raises SIGSEGV or SIGBUS, we currently assume the signal belongs to
the guest. With an artificial error introduced, we will now print
QEMU internal SIGSEGV {code=MAPERR, addr=(nil)}
Signed-off-by: Helge D
Distinguish host SIGABRT from guest SIGABRT by mapping
the guest signal onto one of the host RT signals.
This prevents a cycle by which a host assertion failure
is caught and handled by host_signal_handler, queued for
the guest, and then we attempt to continue past the
host abort. What happens ne
Make host_signal_handler slightly easier to read.
Acked-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 145 ++--
1 file changed, 85 insertions(+), 60 deletions(-)
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 0
From: Mikulas Patocka
sh4 uses gUSA (general UserSpace Atomicity) to provide atomicity on CPUs
that don't have atomic instructions. A gUSA region that adds 1 to an
atomic variable stored in @R2 looks like this:
4004b6: 03 c7 mova4004c4 ,r0
4004b8: f3 61 mo
tags/pull-lu-20231018
for you to fetch changes up to 38ee0a7dfb4b15407678df26448e4a18fd9a51d4:
linux-user: Remap guest SIGABRT (2023-10-18 16:25:06 -0700)
linux-user/mips: fix abort on integer overflow
linux-user/sh4: Fix crashes
This line is supposed to be unreachable, but if we're going to
have it at all, SIGABRT via abort() is subject to the same signal
peril that created this function in the first place.
We can _exit immediately without peril.
Acked-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
These signals, when not spoofed via kill(), are always bugs.
Use die_from_signal to report this sensibly.
Acked-by: Helge Deller
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --gi
Because we trap so many signals for use by the guest,
we have to take extra steps to exit properly.
Acked-by: Helge Deller
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/signal.c | 52 -
1 file changed, 28 inserti
On Wed, 2023-10-18 at 10:52 +0200, Kevin Wolf wrote:
> Am 16.10.2023 um 17:19 hat David Woodhouse geschrieben:
> > From: David Woodhouse
> >
> > There's no need to force the user to assign a vdev. We can automatically
> > assign one, starting at xvda and searching until we find the first disk
> >
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Fixes: 92c041c59b ("tcg/riscv: Add the prologue generation and register the
JIT")
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d6dbcaf3cb..dc
From: Mike Frysinger
Use of the API was removed a while back, but the define wasn't.
Signed-off-by: Mike Frysinger
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20231015010046.16020-1-vap...@gentoo.org>
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 2 --
1 file changed, 2 de
Fix TCG_GUEST_BASE_REG to use 'TCG_REG_R30' instead of '30'.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 284 ---
1 file changed, 143 insertions(+), 141 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.in
PADDI can load 34-bit immediates and 34-bit pc-relative addresses.
Reviewed-by: Jordan Niethe
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 51
1 file changed, 51 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target
With ISA v3.0, we can use ADDPCIS instead of BCL+MFLR to load NIA.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 25 ++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index aafbf2db4e..b0
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 126 +++
1 file changed, 61 insertions(+), 65 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 801302d85d..c
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target.c.inc | 185 +++--
1 file changed, 94 insertions(+), 91 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index dc71f829d1..34e10e77d9 100644
--- a/tcg/riscv/tcg-target.c.inc
tags/pull-tcg-20231018
for you to fetch changes up to b540757b7f711eaf069f530916005cf8cfe7c00f:
target/i386: Use i128 for 128 and 256-bit loads and stores (2023-10-18
12:33:08 -0700)
tcg: Drop unused tcg_temp_free define
tcg:
Provide a define to allow !tcg_use_softmmu code paths to
compile in system mode, but require elimination.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4
1 file changed, 4 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index d3a4a17ef2..35158a0846
This appears to slightly improve performance on power9/10.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 6496f76e41..c31da4da9d 100644
--- a/tcg/ppc/tcg-t
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/arm/tcg-target.c.inc | 203 +++
1 file changed, 97 insertions(+), 106 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 0d9c2d157b..fc78566494 10064
Begin disconnecting CONFIG_SOFTMMU from !CONFIG_USER_ONLY.
Introduce a variable which can be set at startup to select
one method or another for user-only.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 8 ++--
tcg/tcg-op-ldst.c | 14 +++
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index db3212083b..6496f76e41 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2753,6 +2753,9 @@ static v
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 161 ++---
1 file changed, 79 insertions(+), 82 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 4ef9ac3d5b..fbee43d3b0 10
It saves one insn to load the address of TB+4 instead of TB.
Adjust all of the indexing to match.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 177 +--
1 file changed, 88 insertions(+), 89 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 3afb896a3a..a3efa1e67
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 720f92ff33..6337b1e8be 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 231 +++---
1 file changed, 113 insertions(+), 118 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index e2892edc6a..328984ccff 10
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 393dbcd01c..c29355b67b 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -342,8 +342,8 @@ void tcg_gen_divu_i32(TCGv_i32 ret, TCGv
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 12
1 file changed, 12 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 226b5598ac..720f92ff33 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1081,6 +1081,12
We already register allocate through extended basic blocks,
optimize through extended basic blocks as well.
Signed-off-by: Richard Henderson
---
tcg/optimize.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3013eb04e6..2db5177c32
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 184 ++
1 file changed, 89 insertions(+), 95 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 788d608150..a3c0473395 1006
From: Jordan Niethe
Direct branch patching was disabled when using TCG_REG_TB in commit
736a1588c1 ("tcg/ppc: Fix race in goto_tb implementation").
The issue with direct branch patching with TCG_REG_TB is the lack of
synchronization between the new TCG_REG_TB being established and the
direct bra
Do not require the translators to jump through concat and
extract of i64 in order to move values to and from env.
Tested-by: Song Gao
Reviewed-by: Song Gao
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op-common.h | 3 +++
tcg/tcg-op.c
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 13 +
1 file changed, 13 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index b0b8cd2390..226b5598ac 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -1055,6 +1055,1
The prefixed instructions have a pc-relative form to use here.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 79e82d2f94..db3212083b 100644
--- a/tcg/ppc/tcg-targ
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 63 +
1 file changed, 29 insertions(+), 34 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index d2061ec44a..0c81e066de 100644
--- a/target/i386/tcg/translat
When the offset is out of range of the non-prefixed insn, but
fits the 34-bit immediate of the prefixed insn, use that.
Reviewed-by: Jordan Niethe
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 66
1 file changed, 66 insertions(+)
diff
The prefixed instruction has a pc-relative form to use here.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 24
1 file changed, 24 insertions(+)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 34df9144cc..79e82d2f94 100644
--- a/t
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 5c873b2161..5cecc6ed95 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -221,7 +
On Wed, Oct 11, 2023 at 07:52:18PM +0200, Eric Auger wrote:
> This helper will allow to convey information about valid
> IOVA ranges to virtual IOMMUS.
>
> Signed-off-by: Eric Auger
Acked-by: Peter Xu
--
Peter Xu
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 6 ++-
target/hppa/translate.c | 79
2 files changed, 60 insertions(+), 25 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 7b51f39b9e..6f0c3f6ea5 100644
Manipulate the shift count so that the bit to be tested
is always placed at the MSB.
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 4 ++--
target/hppa/translate.c | 6 ++
2 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/
With pa2.0, absolute addresses are not the same as physical addresses,
and undergo a transformation based on PSW_W.
Signed-off-by: Richard Henderson
---
target/hppa/cpu.h| 3 +++
target/hppa/helper.c | 4 ++--
target/hppa/mem_helper.c | 47 ++--
Signed-off-by: Richard Henderson
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 4
target/hppa/op_helper.c | 32
target/hppa/translate.c | 15 +++
4 files changed, 53 insertions(+)
diff --git a/target/hppa/helper.h b/target/h
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 14 +++---
target/hppa/translate.c | 25 -
2 files changed, 19 insertions(+), 20 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 26ca9f1063..03b1a11cac 100644
---
Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.
Signed-off-by: Richard Henderson
---
target/hppa/translate.c | 20 +++-
1 file chang
Signed-off-by: Richard Henderson
---
target/hppa/helper.h | 2 ++
target/hppa/insns.decode | 12 ++--
target/hppa/op_helper.c | 32
target/hppa/translate.c | 32
4 files changed, 76 insertions(+), 2 deletions(-)
dif
From: Helge Deller
The default PSW is set by the operating system with the PDC_PSW firmware
call. Use that setting to decide if wide mode is to be enabled for
interruptions and EIRR usage.
Signed-off-by: Helge Deller
Reviewed-by: Richard Henderson
Signed-off-by: Richard Henderson
---
target/
Signed-off-by: Richard Henderson
---
target/hppa/insns.decode | 6 --
target/hppa/translate.c | 11 +--
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 03b1a11cac..d4a03b0299 100644
--- a/target/hppa/insns.deco
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