Hi!Thanks for your advice! I made the following changes from v2 to v3:
1. Merge the submissions of patch1 and patch2 in v2, and add the fixes tag
2. Fixed typos
3. patch3:
3.1 Simplified the judgment logic of buffer organization.
3.2 Change the buffer organization field to a shared field, and m
Fixed inconsistency between the regisiter bit field definition header file
and the ast2600 datasheet. The reg name is I2CD1C:Pool Buffer Control
Register in old register mode and I2CC0C: Master/Slave Pool Buffer Control
Register in new register mode. They share bit field
[12:8]:Transmit Data Byte
According to the ast2600 datasheet and the linux aspeed i2c driver,
the TXBUF transmission start position should be TXBUF[0] instead
of TXBUF[1],so the arg pool_start is useless,and the address is not
included in TXBUF.So even if Tx Count equals zero,there is at least
1 byte data needs to be transm
Added support for the buffer organization option in pool buffer control
register.when set to 1,The buffer is split into two parts: Lower 16 bytes
for Tx and higher 16 bytes for Rx.
Signed-off-by: Hang Yu
---
v2-->v3:
1. Fixed typos
2. Simplified the judgment logic of buffer organization.
3. Chang
At 2023-08-11 22:31:36, "Peter Xu" wrote:
>On Fri, Aug 11, 2023 at 01:49:52PM +0800, ThinerLogoer wrote:
>> At 2023-08-11 05:24:43, "Peter Xu" wrote:
>> >On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
>> >> >I think we have the following options (there might be more)
>> >> >
>> >>
The arguments in MESONINTROSPECT are quoted with shlex.quote() so it
must be parsed with shlex.split().
Fixes: cf60ccc330 ("cutils: Introduce bundle mechanism")
Reported-by: Michael Tokarev
Signed-off-by: Akihiko Odaki
---
scripts/symlink-install-tree.py | 3 ++-
1 file changed, 2 insertions(+)
This bug was also in 8.0.
Jason
On Fri, Aug 11, 2023 at 10:07 PM Peter Maydell
wrote:
> On Fri, 11 Aug 2023 at 10:55, Peter Maydell
> wrote:
> >
> > On Thu, 10 Aug 2023 at 18:51, Michael S. Tsirkin wrote:
> > >
> > > On Wed, Aug 09, 2023 at 10:22:50AM +, Jason Chien wrote:
> > > > In pcie
At 2023-08-12 03:00:54, "David Hildenbrand" wrote:
>On 11.08.23 07:49, ThinerLogoer wrote:
>> At 2023-08-11 05:24:43, "Peter Xu" wrote:
>>> On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
> I think we have the following options (there might be more)
>
> 1) This patch.
>>
-apply-20230811-3
for you to fetch changes up to b274c2388e9fcde75d60c6e7c7d8f74b61b7:
hw/riscv/virt.c: change 'aclint' TCG check (2023-08-11 14:16:26 -0400)
Sixth RISC-V PR for 8.1
This is a last minute PR for RISC-V.
On 8/11/23 10:41, Peter Maydell wrote:
On Fri, 11 Aug 2023 at 17:18, Michael S. Tsirkin wrote:
The following changes since commit 15b11a1da6a4b7c6b8bb37883f52b544dee2b8fd:
cryptodev: Handle unexpected request to avoid crash (2023-08-03 16:16:17
-0400)
are available in the Git repository
On 8/11/23 09:17, Michael S. Tsirkin wrote:
The following changes since commit 15b11a1da6a4b7c6b8bb37883f52b544dee2b8fd:
cryptodev: Handle unexpected request to avoid crash (2023-08-03 16:16:17
-0400)
are available in the Git repository at:
https://git.kernel.org/pub/scm/virt/kvm/mst/qe
The cortex-a710 is a first generation ARMv9.0-A processor.
Signed-off-by: Richard Henderson
---
docs/system/arm/virt.rst | 1 +
hw/arm/virt.c| 1 +
target/arm/tcg/cpu64.c | 234 +++
3 files changed, 236 insertions(+)
diff --git a/docs/system
This is one of the first generation Armv9 cores, and gives us something
concrete to test in that area. Notably, it supports MTE.
Changes for v2:
* Check GMBS during realize.
* Fix access checks for neoverse implementation registers.
Mostly just traps EL1/EL2 if EL2/EL3 enabled.
* Add ma
Do not hard-code the constants for Neoverse V1.
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c | 48 --
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 4cd73779c8..00f39d42a
Like FEAT_TRF (Self-hosted Trace Extension), suppress tracing
external to the cpu, which is out of scope for QEMU.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 85c02308e4..43c5ac6456 100644
This value is only 4 bits wide.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88e5accda6..7fedbb34ba 100644
--- a/target/arm/cpu.h
+++ b/target/arm/
There is only one additional EL1 register modeled, which
also needs to use access_actlr_w.
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index bc3db798f0..b0cac05be
When the cpu support MTE, but the system does not, reduce cpu
support to user instructions at EL0 instead of completely
disabling MTE. If we encounter a cpu implementation which does
something else, we can revisit this setting.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 7 ---
Support all of the easy GM block sizes.
Use direct memory operations, since the pointers are aligned.
While BS=2 (16 bytes, 1 tag) is a legal setting, that requires
an atomic store of one nibble. This is not difficult, but there
is also no point in supporting it until required.
Note that cortex-
Access to many of the special registers is enabled or disabled
by ACTLR_EL[23], which we implement as constant 0, which means
that all writes outside EL3 should trap.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h| 2 ++
target/arm/helper.c| 4 ++--
target/arm/tcg/cpu64.c | 4
Previously we hard-coded the blocksize with GMID_EL1_BS.
But the value we choose for -cpu max does not match the
value that cortex-a710 uses.
Mirror the way we handle dcz_blocksize.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 ++
target/a
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index b0cac05be6..0054bb6dfa 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -573,6 +573,18 @@ static
This feature allows the operating system to set TCR_ELx.HWU*
to allow the implementation to use the PBHA bits from the
block and page descriptors for for IMPLEMENTATION DEFINED
purposes. Since QEMU has no need to use these bits, we may
simply ignore them.
Signed-off-by: Richard Henderson
---
do
On 8/11/23 10:18, Pawan Gupta wrote:
> This is just compile tested.
I used this patch when testing the GDS Linux patches, so you can add a T-B from
me.
On Fri, Aug 11, 2023 at 07:39:37PM +0200, David Hildenbrand wrote:
> On 11.08.23 18:54, Peter Xu wrote:
> > On Fri, Aug 11, 2023 at 06:25:14PM +0200, David Hildenbrand wrote:
> > > On 11.08.23 18:22, Peter Xu wrote:
> > > > On Fri, Aug 11, 2023 at 06:17:05PM +0200, David Hildenbrand wrote:
> > > >
On 11.08.23 07:49, ThinerLogoer wrote:
At 2023-08-11 05:24:43, "Peter Xu" wrote:
On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
I think we have the following options (there might be more)
1) This patch.
2) New flag for memory-backend-file. We already have "readonly" and
"share
Hi,
I found that in the guest Linux OS. The IVSHMEM device is set with 3 MTRR
regions.
reg00: base=0x0c000 ( 3072MB), size= 1024MB, count=1: uncachable
reg01: base=0x0b000 ( 2816MB), size= 256MB, count=1: uncachable
reg02: base=0x8 (32768MB), size=32768MB, count=1: uncachable
Ba
Hi everyone,
The QEMU v7.2.5 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v7.2.5 is now tagged in the official qemu.git repository, and the
stable-7.2 branch has been updated accordingly:
https://gitlab.com/qem
Hi everyone,
The QEMU v8.0.4 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
v8.0.4 is now tagged in the official qemu.git repository, and the
stable-8.0 branch has been updated accordingly:
https://gitlab.com/qem
The following changes since commit 3944e93af06f06eb07316e0bef46b007573e0309:
Update version for v8.1.0-rc3 release (2023-08-10 12:49:56 -0700)
are available in the Git repository at:
https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230811-3
for you to fetch changes up to
From: Daniel Henrique Barboza
cpu->cfg.mvendorid is a 32 bit field and kvm_set_one_reg() always write
a target_ulong val, i.e. a 64 bit field in a 64 bit host.
Given that we're passing a pointer to the mvendorid field, the reg is
reading 64 bits starting from mvendorid and going 32 bits in the n
From: Daniel Henrique Barboza
The 'aclint' property is being conditioned with tcg acceleration in
virt_machine_class_init(). But acceleration code starts later than the
class init of the board, meaning that tcg_enabled() will be always be
false during class_init(), and the option is never being d
On Fri, Aug 11, 2023 at 12:03 PM Daniel Henrique Barboza
wrote:
>
> Richard, Alistair,
>
> I came across this gitlab bug earlier today. The bug itself was opened
> yesterday:
>
> https://gitlab.com/qemu-project/qemu/-/issues/1823
>
> And turns out that this is a regression in the 'aclint' option t
On Fri, Aug 11, 2023 at 12:03 PM Daniel Henrique Barboza
wrote:
>
> The 'aclint' property is being conditioned with tcg acceleration in
> virt_machine_class_init(). But acceleration code starts later than the
> class init of the board, meaning that tcg_enabled() will be always be
> false during cl
From: Philippe Mathieu-Daudé
Use autofree heap allocation instead of variable-length array on the
stack. Here we don't expect the bitmap size to be enormous, and
since we're about to read/write it to disk the overhead of the
allocation should be fine.
The codebase has very few VLAs, and if we ca
The QEMU codebase has very few C variable length arrays, and if we can
get rid of them all we can make the compiler error on new additions.
This is a defensive measure against security bugs where an on-stack
dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527).
We last had a go at
From: Philippe Mathieu-Daudé
In nvme_map_sgl() we create an array segment[] whose size is the
'const int SEG_CHUNK_SIZE'. Since this is C, rather than C++, a
"const int foo" is not a true constant, it's merely a variable with a
constant value, and so semantically segment[] is a variable-length
a
Instead of using a variable-length array in nvme_map_prp(),
allocate on the stack with a g_autofree pointer.
The codebase has very few VLAs, and if we can get rid of them all we
can make the compiler error on new additions. This is a defensive
measure against security bugs where an on-stack dynam
On Fri, 11 Aug 2023 at 17:18, Michael S. Tsirkin wrote:
>
> The following changes since commit 15b11a1da6a4b7c6b8bb37883f52b544dee2b8fd:
>
> cryptodev: Handle unexpected request to avoid crash (2023-08-03 16:16:17
> -0400)
>
> are available in the Git repository at:
>
> https://git.kernel.org
On 11.08.23 18:54, Peter Xu wrote:
On Fri, Aug 11, 2023 at 06:25:14PM +0200, David Hildenbrand wrote:
On 11.08.23 18:22, Peter Xu wrote:
On Fri, Aug 11, 2023 at 06:17:05PM +0200, David Hildenbrand wrote:
We wouldn't touch "-mem-path".
But still the same issue when someone uses -object memory
Hi!
8.1.0-rc3, trying to build (in a subdir of the source dir), and getting an
interesting
error message:
../../configure ... --disable-download ...
...
Found ninja-1.11.1 at /usr/bin/ninja
Running postconf script
'/build/pkg/qemu-8.1.0~rc3+dfsg/b/qemu/pyvenv/bin/python3
/build/pkg/qemu-8.1.0
On 11/8/23 18:02, Daniel Henrique Barboza wrote:
The 'aclint' property is being conditioned with tcg acceleration in
virt_machine_class_init(). But acceleration code starts later than the
class init of the board, meaning that tcg_enabled() will be always be
false during class_init(), and the opti
On 11/8/23 18:18, Michael S. Tsirkin wrote:
From: Jason Chien
In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCI
Gather Data Sampling (GDS) is a side-channel attack using Gather
instructions. Some Intel processors will set ARCH_CAP_GDS_NO bit in
MSR IA32_ARCH_CAPABILITIES to report that they are not vulnerable to
GDS.
Make this bit available to guests.
Signed-off-by: Pawan Gupta
---
This is just compile te
On Fri, Aug 11, 2023 at 06:25:14PM +0200, David Hildenbrand wrote:
> On 11.08.23 18:22, Peter Xu wrote:
> > On Fri, Aug 11, 2023 at 06:17:05PM +0200, David Hildenbrand wrote:
> > > We wouldn't touch "-mem-path".
> >
> > But still the same issue when someone uses -object memory-backend-file for
> >
Change parse_elf_properties as well, as the bprm_buf argument
ties the two functions closely.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 128 +--
1 file changed, 49 insertions(+), 79 deletions(-)
diff --git a/linux-user/elfload.c b/linux-
The vdso image will be pre-processed into a C data array, with
a simple list of relocations to perform, and identifying the
location of signal trampolines.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 87 +++-
1 file changed, 78 insertions(+
There are only a couple of uses of bprm->fd remaining.
Migrate to the other field.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/loader.h| 1 -
linux-user/flatload.c | 8
linux-user/linuxload.c | 5 ++---
3 files changed, 6 insertions(+), 8 de
Aside from the section headers, we're unlikely to hit the
ImageSource cache on guest executables. But the interface
for imgsrc_read_* is better.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 87
1 file changed, 48 insertions(+), 39 dele
Building the vdso itself is not actually wired up to anything, since
we require a cross-compiler. Just check in that file for now.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 16 ++-
linux-user/i386/Makefile.vdso | 5 +
linux-user/i386/meson.build | 7 ++
linux-u
This tool will be used for post-processing the linked vdso image,
turning it into something that is easy to include into elfload.c.
Signed-off-by: Richard Henderson
---
linux-user/gen-vdso.c | 223
linux-user/gen-vdso-elfn.c.inc | 306 +++
Building of the vdsos are not actually wired up to anything, since
we require a cross-compiler. Just check in the files for now.
The thumb vdso will only be used for m-profile, as all of our
a-profile cpus support arm mode.
Signed-off-by: Richard Henderson
---
linux-user/arm/signal.c |
Building the vdso itself is not actually wired up to anything, since
we require a cross-compiler. Just check in that file for now.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c| 4 +-
linux-user/x86_64/Makefile.vdso | 5 ++
linux-user/x86_64/meson.build | 6 ++
l
Reorg the if cases to reduce indentation.
Test for 4 bytes in the file before checking the signatures.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/linuxload.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(
Building the vdso itself is not actually wired up to anything, since
we require a cross-compiler. Just check in that file for now.
Drop the now-unused 9 trampoline words, and describe the frame
without the trampoline in __kernel_rt_sigreturn.
Signed-off-by: Richard Henderson
---
linux-user/elf
Rearrange the allocation of storage for ehdr between load_elf_image
and load_elf_binary. The same set of copies are done, but we don't
modify bprm_buf, which will be important later.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 25
It's time for another round on implementing the VDSO for linux-user.
We are now seeing applications built that absolutely require it,
and have no fallback for the VDSO to be absent.
For instance,
https://gitlab.com/qemu-project/qemu/-/issues/1267
uses musl and will currently branch to NULL ex
Building the vdso itself is not actually wired up to anything, since
we require a cross-compiler. Just check in those files for now.
This fixes a bug wrt libgcc fallback unwinding. It expects the stack
pointer to point to the siginfo_t, whereas we had inexplicably placed
our private signal tramp
Add a probe for whether A32 mode is supported.
Fill in the field for the pre-v5 cpus.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
target/arm/tcg/cpu32.c | 7 +++
2 files changed, 12 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 88e5accda6..4
Introduced and initialized, but not yet really used.
These will tidy the current tests vs BPRM_BUF_SIZE.
Signed-off-by: Richard Henderson
---
linux-user/loader.h| 61 +++-
linux-user/linuxload.c | 90 ++
2 files changed, 142 ins
Building of the vdsos are not actually wired up to anything, since
we require a cross-compiler. Just check in the files for now.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 4 ++
linux-user/aarch64/Makefile.vdso | 11 +
linux-user/aarch64/meson.build | 11 +
On Fri, Aug 11, 2023 at 07:52:25AM +0530, Maverickk 78 wrote:
> Thanks Fan,
>
> cxl create-region works like a charm :)
>
> Since this gets listed as "System Ram(kmem)", I guess the kernel
> treats it as regular memory and
> allocates it to the applications when needed?
> or is there an extra effor
This implements a simple extension to dfilter so we can use pathnames
as a proxy for address ranges such that:
./qemu-x86_64 -d page,in_asm,op,op_opt,out_asm \
--dfilter libnative \
--native-bypass common-user/native/x86_64-linux-user/libnative.so \
/usr/bin/tar xvf audacity-sources-
This will be useful in later patches for tracking the paths associated
with mmap operations. This will be useful to the upcoming -dfilter
changes to track execution only certain libraries.
Signed-off-by: Alex Bennée
---
linux-user/syscall.c | 59
1 fi
I was getting lost on debugging output and I couldn't get the mapped
address of libnative to be stable. So to help I hacked up this
extension which may or may not be worth developing further.
Consider this a debugging RFC tool for now.
Alex Bennée (2):
linux-user: implement some basic FD<->path
On 11.08.23 18:22, Peter Xu wrote:
On Fri, Aug 11, 2023 at 06:17:05PM +0200, David Hildenbrand wrote:
We wouldn't touch "-mem-path".
But still the same issue when someone uses -object memory-backend-file for
hugetlb, mapping privately, expecting ram discard to work?
Basically I see that examp
On Fri, Aug 11, 2023 at 06:17:05PM +0200, David Hildenbrand wrote:
> We wouldn't touch "-mem-path".
But still the same issue when someone uses -object memory-backend-file for
hugetlb, mapping privately, expecting ram discard to work?
Basically I see that example as, "hugetlb" in general made the
From: Guoyi Tu
The PCI_COMMAND register is located at offset 4 within
the PCI configuration space and occupies 2 bytes. The
interrupt disable bit is at the 10th bit, which corresponds
to the byte at offset 5 in the PCI configuration space.
In our testing environment, the guest driver may directl
From: Jason Chien
In pcie_bus_realize(), a root bus is realized as a PCIe bus and a non-root
bus is realized as a PCIe bus if its parent bus is a PCIe bus. However,
the child bus "dw-pcie" is realized before the parent bus "pcie" which is
the root PCIe bus. Thus, the extended configuration space
The following changes since commit 15b11a1da6a4b7c6b8bb37883f52b544dee2b8fd:
cryptodev: Handle unexpected request to avoid crash (2023-08-03 16:16:17
-0400)
are available in the Git repository at:
https://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream
for you to fetch chang
On 8/11/23 03:02, Song Gao wrote:
Signed-off-by: Song Gao
---
.../loongarch/insn_trans/trans_privileged.c.inc | 16
target/loongarch/translate.h | 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Richard Henderson
r~
On 11.08.23 18:16, Peter Xu wrote:
On Fri, Aug 11, 2023 at 05:26:24PM +0200, David Hildenbrand wrote:
I just started looking into the origins of "-mem-path".
Originally c902760fb2 ("Add option to use file backed guest memory"):
* Without MAP_POPULATE support, we use MAP_PRIVATE
* With MAP_POPU
On Fri, Aug 11, 2023 at 05:26:24PM +0200, David Hildenbrand wrote:
> I just started looking into the origins of "-mem-path".
>
> Originally c902760fb2 ("Add option to use file backed guest memory"):
>
> * Without MAP_POPULATE support, we use MAP_PRIVATE
> * With MAP_POPULATE support we use MAP_PR
On 8/11/23 03:02, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++-
target/loongarch/translate.h|2 +
2 files changed, 823 insertions(+), 661 deletions(-)
Reviewed-by: Richard Henderson
r~
On Fri, Aug 11, 2023 at 10:46:51PM +0800, Guoyi Tu wrote:
> The PCI_COMMAND register is located at offset 4 within
> the PCI configuration space and occupies 2 bytes. The
> interrupt disable bit is at the 10th bit, which corresponds
> to the byte at offset 5 in the PCI configuration space.
>
> In
On 8/11/23 03:02, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_atomic.c.inc | 12
target/loongarch/translate.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc
b/target/loon
On 8/11/23 03:02, Song Gao wrote:
Signed-off-by: Song Gao
---
target/loongarch/insn_trans/trans_privileged.c.inc | 8
target/loongarch/translate.h | 1 +
2 files changed, 9 insertions(+)
Reviewed-by: Richard Henderson
r~
On 8/11/23 03:02, Song Gao wrote:
Signed-off-by: Song Gao
---
.../loongarch/insn_trans/trans_farith.c.inc | 96 ---
target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++
target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +--
.../loongarch/insn_trans/trans_fmemory.
On Thu, Aug 10, 2023 at 6:18 AM Jonathan Cameron
wrote:
>
> On Wed, 9 Aug 2023 12:45:35 -0400
> Alistair Francis wrote:
>
> > On Wed, Aug 9, 2023 at 8:11 AM Jonathan Cameron
> > wrote:
> > >
> > > On Tue, 8 Aug 2023 11:51:21 -0400
> > > Alistair Francis wrote:
> > >
> > > > The Security Protoc
Richard, Alistair,
I came across this gitlab bug earlier today. The bug itself was opened
yesterday:
https://gitlab.com/qemu-project/qemu/-/issues/1823
And turns out that this is a regression in the 'aclint' option that was
introduced in 8.1.
I'm aware that we're already in rc3 and kind of late
The 'aclint' property is being conditioned with tcg acceleration in
virt_machine_class_init(). But acceleration code starts later than the
class init of the board, meaning that tcg_enabled() will be always be
false during class_init(), and the option is never being declared even
when declaring TCG
On 8/11/23 03:02, Song Gao wrote:
The la32 manual from [1], and it is not the final version.
[1]:
https://www.loongson.cn/uploads/images/2023041918122813624.%E9%BE%99%E8%8A%AF%E6%9E%B6%E6%9E%8432%E4%BD%8D%E7%B2%BE%E7%AE%80%E7%89%88%E5%8F%82%E8%80%83%E6%89%8B%E5%86%8C_r1p03.pdf
I really hope t
On Fri, Aug 11, 2023 at 04:59:56PM +0200, David Hildenbrand wrote:
> On 10.08.23 23:24, Peter Xu wrote:
> > On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
> > > > I think we have the following options (there might be more)
> > > >
> > > > 1) This patch.
> > > >
> > > > 2) New flag
Enable SVQ with VIRTIO_NET_F_RSS feature.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c
index 7870cbe142..eb08530396 100644
--- a/net/vhost-vdpa.c
+++ b/net/vhost-vdpa.c
@@ -119,6 +119,7 @@ static const
This patch reuses vhost_vdpa_net_load_rss() with some
refactorings to restore the receive-side scaling state
at device's startup.
Signed-off-by: Hawkins Jiawei
---
net/vhost-vdpa.c | 53
1 file changed, 35 insertions(+), 18 deletions(-)
diff --gi
This series enables shadowed CVQ to intercept RSS command
through shadowed CVQ, update the virtio NIC device model
so qemu send it in a migration, and the restore of that
RSS state in the destination.
Note that this patch should be based on
patch "Vhost-vdpa Shadow Virtqueue Hash calculation Suppo
At present, to enable the VIRTIO_NET_F_RSS feature, eBPF must
be loaded for the vhost backend.
Given that vhost-vdpa is one of the vhost backend, we need to
implement the SetSteeringEBPF method to support RSS for vhost-vdpa,
even if vhost-vdpa calculates the rss hash in the hardware device
instead
On 11.08.23 16:59, David Hildenbrand wrote:
On 10.08.23 23:24, Peter Xu wrote:
On Fri, Aug 11, 2023 at 01:06:12AM +0800, ThinerLogoer wrote:
I think we have the following options (there might be more)
1) This patch.
2) New flag for memory-backend-file. We already have "readonly" and
"share=".
On 8/11/23 03:02, Song Gao wrote:
The default check parmeter is ALL, remove TRANS_64 marco.
Suggested-by: Richard Henderson
Signed-off-by: Song Gao
If you're going to remove TRANS_64, you should simply drop the patch that added it, and be
careful about the final patch ordering such that the
On 8/11/23 01:12, gaosong wrote:
+TRANS_64(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
TRANS_64(rotr_w, ...)
...
TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
TRANS_64(rotri_w, ...)
I see the manual
We currently have a pattern for cleaning up a migration QEMUFile:
qemu_mutex_lock(&s->qemu_file_lock);
file = s->file_name;
s->file_name = NULL;
qemu_mutex_unlock(&s->qemu_file_lock);
migration_ioc_unregister_yank_from_file(file);
qemu_file_shutdown(file);
qemu_fclose(file);
There
When doing cleanup, we currently close() some of the shared migration
files and shutdown() + close() others. Be consistent by always calling
shutdown() before close().
Do this only for the source files for now because the source runs
multiple threads which could cause races between the two calls.
This file is owned by the return path thread which is already doing
cleanup.
Signed-off-by: Fabiano Rosas
---
migration/migration.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/migration/migration.c b/migration/migration.c
index 5e6a766235..195726eb4a 100644
--- a/migration/migration
Now that the return path thread is allowed to finish during a paused
migration, we can move the cleanup of the QEMUFiles to the main
migration thread.
Signed-off-by: Fabiano Rosas
---
migration/migration.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/migration/
Checking ms->to_dst_file for errors when cleaning up the return path
could race with migrate_fd_cleanup() which clears the pointer.
Since migrate_fd_cleanup() is reachable via qmp_migrate(), which is
issued by the user, it is safer if we take the lock when reading
ms->to_dst_file.
Signed-off-by:
We cannot call qemu_file_shutdown() on the return path file without
taking the file lock. The return path thread could be running it's
cleanup code and have just cleared the pointer.
This was caught by inspection, it should be rare, but the next patches
will start calling this code from other plac
It's not safe to call qemu_file_shutdown() on the to_dst_file without
first checking for the file's presence under the lock. The cleanup of
this file happens at postcopy_pause() and migrate_fd_cleanup() which
are not necessarily running in the same thread as migrate_fd_cancel().
Signed-off-by: Fab
I decided to fix the issues with the shutdown instead of complaining
about them. First 5 patches address all of the possible races I
found. The only problem left to figure out is the -EIO on shutdown
which will need more thought.
Patches 6 & 7 fix the original segfault.
Patches 8-10 make the clea
We don't need to set the rp_state.error right after a shutdown because
qemu_file_shutdown() always sets the QEMUFile error, so the return
path thread would have seen it and set the rp error itself.
Setting the error outside of the thread is also racy because the
thread could clear it after we set
Replace the return path retry logic with finishing and restarting the
thread. This fixes a race when resuming the migration that leads to a
segfault.
Currently when doing postcopy we consider that an IO error on the
return path file could be due to a network intermittency. We then keep
the thread
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