Recommend to tweak the subject to
MAINTAINERS: Add section "TITLE"
where TITLE is whatever you use in MAINTAINERS, provided it's short
enough to fit.
~hyman writes:
> From: Hyman Huang(黄勇)
>
> I've built interests in dirty-limit and dirty page rate
Recommend to drop the dash.
> features
On 7/28/23 19:35, Richard Henderson wrote:
The change to use translator_use_goto_tb went too far, as the
CF_SINGLE_STEP flag managed by the translator only handles
gdb single stepping and not the architectural single stepping
modeled in DisasContext.singlestep_enabled.
Fixes: 6e9cc373ec5 ("targe
At 2023-07-28 18:45:20, "David Hildenbrand" wrote:
>>> Quick untested attempt to move retry handling to the caller:
>>>
>>> diff --git a/softmmu/physmem.c b/softmmu/physmem.c
>>> index 3df73542e1..c826bb78fc 100644
>>> --- a/softmmu/physmem.c
>>> +++ b/softmmu/physmem.c
>>> @@ -1289,8 +1289,7 @@ s
Commit bef6f008b98(accel/tcg: Return bool from page_check_range) converts
integer return value to bool type. However, it wrongly converted the use
of the API in riscv fault-only-first, where page_check_range < = 0, should
be converted to !page_check_range.
Signed-off-by: LIU Zhiwei
---
target/ri
On Fri, Jul 28, 2023 at 09:15:16AM -0300, Fabiano Rosas wrote:
> Replace the return path retry logic with finishing and restarting the
> thread. This fixes a race when resuming the migration that leads to a
> segfault.
>
> Currently when doing postcopy we consider that an IO error on the
> return
On Fri, Jul 28, 2023 at 09:15:15AM -0300, Fabiano Rosas wrote:
> We're about to reuse this function so move the 'rp_thread_created'
> check into it and remove the redundant tracing and comment.
>
> Add a new tracepoint akin to what is already done at
> migration_completion().
>
> Signed-off-by: F
On Fri, Jul 28, 2023 at 09:15:14AM -0300, Fabiano Rosas wrote:
> When waiting for the return path (RP) thread to finish, there is
> really nothing wrong in the RP if the destination end of the migration
> stops responding, leaving it stuck.
>
> Stop returning an error at that point and leave it to
On Fri, Jul 28, 2023 at 09:42:28PM +0700, Bui Quang Minh wrote:
> As userspace APIC now supports x2APIC, intel interrupt remapping
> hardware can be set to EIM mode when userspace local APIC is used.
>
> Suggested-by: Joao Martins
> Signed-off-by: Bui Quang Minh
Acked-by: Peter Xu
--
Peter X
Hi
On Thu, Jul 13, 2023 at 11:11 AM Dongli Zhang wrote:
>
> The kdump-zlib data pages are not dumped from aarch64 host when the
> 'pvtime' is involved, that is, when the block->target_end is not aligned to
> page_size. In the below example, it is expected to dump two blocks.
>
> (qemu) info mtree
On 7/28/23 22:57, Richard Henderson wrote:
On 7/28/23 13:51, Richard Henderson wrote:
On 7/28/23 12:23, Helge Deller wrote:
+ /* endianess-swap if emulating armeb */
+ oldval = tswap64(oldval);
+ newval = tswap64(newval);
Oh btw, it's not about arm vs armeb, but guest vs host.
This a
On 7/28/23 12:23, Helge Deller wrote:
Commit 7f4f0d9ea870 ("linux-user/arm: Implement __kernel_cmpxchg with host
atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
content, but missed to endianess-swap the oldval and newval values when
emulating an armeb CPU, which expects
On 7/28/23 13:51, Richard Henderson wrote:
On 7/28/23 12:23, Helge Deller wrote:
+ /* endianess-swap if emulating armeb */
+ oldval = tswap64(oldval);
+ newval = tswap64(newval);
Oh btw, it's not about arm vs armeb, but guest vs host.
This also fixes armel on big-endian hosts.
Anywa
Cc qemu-stable.
On 7/28/23 10:35, Richard Henderson wrote:
The change to use translator_use_goto_tb went too far, as the
CF_SINGLE_STEP flag managed by the translator only handles
gdb single stepping and not the architectural single stepping
modeled in DisasContext.singlestep_enabled.
Fixes: 6e
On 7/28/23 12:23, Helge Deller wrote:
+/* endianess-swap if emulating armeb */
+oldval = tswap64(oldval);
+newval = tswap64(newval);
Oh btw, it's not about arm vs armeb, but guest vs host.
This also fixes armel on big-endian hosts.
r~
This solves a problem in which the store to LowCore during tlb_fill
triggers a clean-page TB invalidation for page0 during translation,
which results in an assertion failure for locked pages.
By delaying the store until after the exception has been raised,
we will have unwound the pages locked for
tcet->mig_table is memcpy'ed from tcet->table, which in turn is created
via spapr_tce_alloc_table().
Use g_free() instead of free() to deallocate it.
Signed-off-by: Daniel Henrique Barboza
---
hw/ppc/spapr_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr_
On 7/26/23 15:22, Nicholas Piggin wrote:
Sorry for the delay following up on the fixes, I got sucked down
the decrementer rabbit hole that took longer than expected.
Question about what is suitable for merge at this time and what
should be stable. The first 3 have caused crashes or hangs runn
On 7/28/23 12:55, Richard Henderson wrote:
This solves a problem in which the store to LowCore during tlb_fill
triggers a clean-page TB invalidation for page0 during translation,
which results in an assertion failure for locked pages.
By delaying the store until after the exception has been rais
Use g_free(table[i]) instead of free(table[i]) to comply with QEMU low
level memory management guidelines.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e
Hello,
Here's some trivial changes following Peter's call to arms against
free() and friends in gitlab issue #1798 in an attempt to enforce
our memory management guidelines [1].
We only have 2 "free()" occurences that needs fixing in the ppc tree.
The hard part is to be dilligent to to not introd
On 7/28/23 17:35, Richard Henderson wrote:
On 7/27/23 21:54, Helge Deller wrote:
@@ -174,6 +175,10 @@ static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
return;
}
+ /* endianess-swap if emulating armeb */
+ oldval = tswap32(oldval);
+ newval = tswap32(newval);
Yong,
On Thu, Jun 08, 2023 at 12:46:45AM +0800, ~hyman wrote:
> From: Hyman Huang(黄勇)
>
> Add migration dirty-limit capability test if kernel support
> dirty ring.
>
> Migration dirty-limit capability introduce dirty limit
> capability, two parameters: x-vcpu-dirty-limit-period and
> vcpu-dirty
On 7/28/23 07:55, Eric Blake wrote:
The following changes since commit ccdd31267678db9d80578b5f80bbe94141609ef4:
Merge tag 'pull-qapi-2023-07-26-v2' of https://repo.or.cz/qemu/armbru into
staging (2023-07-26 07:16:19 -0700)
are available in the Git repository at:
https://repo.or.cz/qemu
Commit 7f4f0d9ea870 ("linux-user/arm: Implement __kernel_cmpxchg with host
atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
content, but missed to endianess-swap the oldval and newval values when
emulating an armeb CPU, which expects words to be stored in big endian in
the
On Thu, Jul 27, 2023 at 02:10:09AM +0800, ~hyman wrote:
> From: Hyman Huang(黄勇)
>
> I've built interests in dirty-limit and dirty page rate
> features and also have been working on projects related
> to this subsystem.
>
> Self-recommand myself as a maintainer for this subsystem
> so that I can
Hi Marc-André,
May I get any feedback on this bugfix?
Feel free to let me know if I can help by collecting any data from the aarch64
server.
Since the pvtime is supported by default by QEMU/linux, this indicates currently
the dump does not work for aarch64 with new version of QEMU/linux.
Thank
Previous to this commit, it was assumed that data can only be shadowed
with x-cvq, or if a migration was in place. So CVQ did not need to
check for migration.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/net/vhost-vdp
Now that we have add migration blockers if the device does not support
all the needed features, remove the general blocker applied to all net
devices with CVQ.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 12
1 file changed, 12 deletions(-)
diff --git a/net/vhost-vdpa.c b/ne
At this moment the migration of net features that depends on CVQ is not
possible, as there is no reliable way to restore the device state like mac
address, number of enabled queues, etc to the destination. This is mainly
caused because the device must only read CVQ, and process all the commands
be
Show the memory location of the heap in the /proc/pid/maps file inside
the guest. Store the heap address in ts->heap_base, which requires to
make that variable accessible for all guest architectures, not just
architectures for semihosted binaries (arm, m68k, riscv).
Note that /proc/pid/maps in the
To restore the device at the destination of a live migration we send
the commands through control virtqueue. For a device to read CVQ it
must have received the DRIVER_OK status bit.
However this opens a window where the device could start receiving
packets in rx queue 0 before it receives the RSS
Fix the elf loader to calculate a valid TASK_UNMAPPED_BASE address for all
32-bit architectures, based on the GUEST_ADDR_MAX constant.
Additionally modify the elf loader to load dynamic pie executables at
around:
~ 0x55 for 64-bit guest binaries on 64-bit host,
- 0x0030for 32-bit
To restore the device at the destination of a live migration we send the
commands through control virtqueue. For a device to read CVQ it must
have received the DRIVER_OK status bit.
However this opens a window where the device could start receiving
packets in rx queue 0 before it receives the RSS
Reorganize the guest memory layout to get as much memory as possible for
heap for the guest application.
This patch optimizes the memory layout by loading pie executables
into lower memory and shared libs into higher memory (at
TASK_UNMAPPED_BASE). This leaves a bigger memory area usable for heap
The change to use translator_use_goto_tb went too far, as the
CF_SINGLE_STEP flag managed by the translator only handles
gdb single stepping and not the architectural single stepping
modeled in DisasContext.singlestep_enabled.
Fixes: 6e9cc373ec5 ("target/ppc: Use translator_use_goto_tb")
Resolves:
While trying to fix a bug which prevents running a static
armhf binary with linux-user, I noticed a whole bunch of
memory layout issues on various platforms. Most noteably
the free heap space was very limited in the current setup.
A large heap is important for example, if you want to
use qemu-user
From: Hyman Huang(黄勇)
Dirty ring size configuration is not supported by guestperf tool.
Introduce dirty-ring-size (ranges in [1024, 65536]) option so
developers can play with dirty-ring and dirty-limit feature easier.
To set dirty ring size with 4096 during migration test:
$ ./tests/migration/g
To restore the device at the destination of a live migration we send the
commands through control virtqueue. For a device to read CVQ it must
have received the DRIVER_OK status bit.
However this opens a window where the device could start receiving
packets in rx queue 0 before it receives the RSS
This allow to skip some rings that qemu does not want to enable.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index bebcc9fe7c..1281502a71 100644
--- a/hw/virtio/vhost-vdpa.c
+++ b
From: Hyman Huang(黄勇)
Add migration dirty-limit capability test if kernel support
dirty ring.
Migration dirty-limit capability introduce dirty limit
capability, two parameters: x-vcpu-dirty-limit-period and
vcpu-dirty-limit are introduced to implement the live
migration with dirty limit.
The te
Dirty-limit feature was introduced in 8.1, and the test
case could be enriched to make sure the behavior and
the performance of dirty-limit is exactly what we want.
This series add 2 test cases, the first commit aims for
the functional test and the others aim for the
performance test.
Please revi
The vhost-vdpa net backend needs to enable vrings in a different order
than default, so export it.
No functional change intended except for tracing, that now includes the
(virtio) index being enabled and the return value of the ioctl.
Still ignoring return value of this function if called from
vh
From: Hyman Huang(黄勇)
Currently, guestperf does not cover the dirty-limit
migration, support this feature.
Note that dirty-limit requires 'dirty-ring-size' set.
To enable dirty-limit, setting x-vcpu-dirty-limit-period
as 500ms and x-vcpu-dirty-limit as 10MB/s:
$ ./tests/migration/guestperf.py \
On 7/28/23 07:37, Daniel P. Berrangé wrote:
On Fri, Jul 28, 2023 at 04:27:46PM +0200, Thomas Huth wrote:
We might want to compile QEMU with Clang on Windows - but it
does not support the __attribute__((gcc_struct)) yet. So we
have to make sure that the structs will stay the same when
the compile
Named interception of in-GPIOs is not supported yet.
Signed-off-by: Chris Laplante
Reviewed-by: Peter Maydell
---
softmmu/qtest.c | 8
1 file changed, 8 insertions(+)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 0f1d478bda..66757ba261 100644
--- a/softmmu/qtest.c
+++ b/softmmu
Adds qtest_irq_intercept_out_named method, which utilizes a new optional
name parameter to the irq_intercept_out qtest command.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c| 18 ++
tests/qtest/libqtest.c | 6 ++
tests/qtest/libqtest.h | 11 +++
3 files c
On 7/28/23 09:05, Richard Henderson wrote:
It's the page containing both code and a page table entry that concerns me. It seems like
a kernel bug, though obviously we shouldn't crash. I'm not sure what to do about it.
Bah. Of course it's not a kernel bug, since the store is to LowCore.
And o
On 7/28/23 09:29, Warner Losh wrote:
We're hitting an assert when we pass in alignment == 0 since that's not
a power of two. so pass in the ideal page size.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
On Fri, 28 Jul 2023 at 02:17, Richard Henderson
wrote:
>
> On 7/27/23 14:36, Ard Biesheuvel wrote:
> > On Thu, 27 Jul 2023 at 19:56, Richard Henderson
> > wrote:
> >>
> >> On 7/26/23 08:01, Richard Henderson wrote:
> >>> On 7/26/23 01:17, Ard Biesheuvel wrote:
> Hints welcome on where the ar
On Fri, Jul 28, 2023 at 7:41 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 7/28/23 06:34, Richard Henderson wrote:
> > On 7/27/23 20:54, Warner Losh wrote:
> >> We're hitting an assert when we pass in alignment == 0 since that's not
> >> a power of two. so pass in the ideal page
We're hitting an assert when we pass in alignment == 0 since that's not
a power of two. so pass in the ideal page size.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/bsd-user/mmap.c b/bsd-user/mmap.c
index 74ed00b9fe3..b62a69
This is much better than just silently failing with OK.
Signed-off-by: Chris Laplante
---
softmmu/qtest.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index 66757ba261..35b643a274 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qt
From: Hyman Huang(黄勇)
Reformat the dirty-limit migration doc comments to conform
to current conventions as commit a937b6aa739 (qapi: Reformat
doc comments to conform to current conventions).
Signed-off-by: Markus Armbruster
Signed-off-by: Hyman Huang(黄勇)
---
qapi/migration.json | 69 +
Hi, Markus, Juan.
Please review the version 2, thanks.
v2:
- split the first commit in v1 into 2
- add commit message of commit:
MAINTAINERS: Add Hyman Huang as maintainer
Yong
Hyman Huang(黄勇) (3):
qapi: Reformat the dirty-limit migration doc comments
qapi: Craft the dirty-limit capabilit
From: Hyman Huang(黄勇)
I've built interests in dirty-limit and dirty page rate
features and also have been working on projects related
to this subsystem.
Self-recommand myself as a maintainer for this subsystem
so that I can help to improve the dirty-limit algorithm
and review the patches about d
From: Hyman Huang(黄勇)
Signed-off-by: Markus Armbruster
Signed-off-by: Hyman Huang(黄勇)
---
qapi/migration.json | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index a74ade4d72..62ab151da2 100644
--- a/qapi/migration.jso
On 7/28/23 06:29, Claudio Fontana wrote:
On 7/27/23 19:41, Richard Henderson wrote:
On 7/21/23 02:08, Claudio Fontana wrote:
Thread 3 "qemu-system-s39" received signal SIGABRT, Aborted.
[Switching to Thread 0x753516c0 (LWP 215975)]
(gdb) bt
#0 0x7730dabc in __pthread_kill_implement
Signed-off-by: Chris Laplante
Reviewed-by: Peter Maydell
---
softmmu/qtest.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/softmmu/qtest.c b/softmmu/qtest.c
index f8d764b719..1b86489162 100644
--- a/softmmu/qtest.c
+++ b/softmmu/qtest.c
@@ -365,6 +365,15 @
This patch series implements the nRF51 DETECT signal
in the GPIO peripheral. A qtest is added exercising the signal.
To implement the test, named out-GPIO IRQ interception had to be added
to the qtest framework. I also took the opportunity to improve IRQ
interception a bit by adding 'FAIL' respons
Exercise the DETECT mechanism of the GPIO peripheral.
Signed-off-by: Chris Laplante
Reviewed-by: Peter Maydell
---
tests/qtest/microbit-test.c | 42 +
1 file changed, 42 insertions(+)
diff --git a/tests/qtest/microbit-test.c b/tests/qtest/microbit-test.c
ind
Implement nRF51 DETECT signal in the GPIO peripheral.
The reference manual makes mention of a per-pin DETECT signal, but these
are not exposed to the user. See
https://devzone.nordicsemi.com/f/nordic-q-a/39858/gpio-per-pin-detect-signal-available
for more information. Currently, I don't see a rea
[ ... ]
--- a/hw/vfio/pci.h
+++ b/hw/vfio/pci.h
@@ -113,6 +113,7 @@ typedef struct VFIOMSIXInfo {
uint32_t table_offset;
uint32_t pba_offset;
unsigned long *pending;
+uint32_t irq_info_flags;
Why not simply pull out a "noresize" bool? Thanks,
Will change to a bool
On Fri, 28 Jul 2023 10:27:17 +0200
Cédric Le Goater wrote:
> On 7/28/23 10:09, Liu, Jing2 wrote:
> > Hi Alex,
> >
> > Thanks very much for reviewing the patches.
> >
> >> On July 28, 2023 1:25 AM, Alex Williamson
> >> wrote:
> >>
> >> On Thu, 27 Jul 2023 03:24:08 -0400
> >> Jing Liu wrote:
On 7/27/23 21:54, Helge Deller wrote:
@@ -174,6 +175,10 @@ static void arm_kernel_cmpxchg64_helper(CPUARMState *env)
return;
}
+/* endianess-swap if emulating armeb */
+oldval = tswap32(oldval);
+newval = tswap32(newval);
Must be tswap64.
r~
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
series, we can now boot Linux kernel into x2APIC mode with TCG accel
On Fri, 28 Jul 2023 at 15:28, Thomas Huth wrote:
>
> Clang on Windows does not seem to know the "gcc_struct" attribute
> and emits a warning when we try to use it. Add an additional check
> here with __has_attribute() to avoid this problem.
>
> Signed-off-by: Thomas Huth
> ---
> include/qemu/com
On 7/28/23 16:28, Richard Henderson wrote:
> On 7/28/23 07:23, Claudio Fontana wrote:
>>> It is a test environment for building packages, so the guest at the time of
>>> the error is running ./configure for the package swig-v4.1.1.tar.gz
>>>
>>> checking build system type... s390x-ibm-linux-gnu^M
This commit extends the APIC ID to 32-bit long and remove the 255 max APIC
ID limit in userspace APIC. The array that manages local APICs is now
dynamically allocated based on the max APIC ID of created x86 machine.
Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC
mode reg
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to support 32-bit destination id.
Additionally, this commit exports IVHD type 0x11 besides the old IVHD type
0x10
The following changes since commit ccdd31267678db9d80578b5f80bbe94141609ef4:
Merge tag 'pull-qapi-2023-07-26-v2' of https://repo.or.cz/qemu/armbru into
staging (2023-07-26 07:16:19 -0700)
are available in the Git repository at:
https://repo.or.cz/qemu/ericb.git tags/pull-nbd-2023-07-28
for
From: "Denis V. Lunev"
Unfortunately
commit 03b67621445d601c9cdc7dfe25812e9f19b81488
Author: Denis V. Lunev
Date: Mon Jul 17 16:55:40 2023 +0200
qemu-nbd: pass structure into nbd_client_thread instead of plain char*
has introduced a regression. struct NbdClientOpts resides on s
Clang complains:
../util/oslib-win32.c:483:56: error: omitting the parameter name in a
function definition is a C2x extension [-Werror,-Wc2x-extensions]
win32_close_exception_handler(struct _EXCEPTION_RECORD*,
^
Fix it by adding parameter na
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Suggested-by: Joao Martins
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/hw/i386
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc/api
On Fri, Jul 28, 2023 at 04:27:46PM +0200, Thomas Huth wrote:
> We might want to compile QEMU with Clang on Windows - but it
> does not support the __attribute__((gcc_struct)) yet. So we
> have to make sure that the structs will stay the same when
> the compiler uses the "ms_struct" layout. The VTD_
On 7/28/23 16:40, Claudio Fontana wrote:
> On 7/28/23 16:28, Richard Henderson wrote:
>> On 7/28/23 07:23, Claudio Fontana wrote:
It is a test environment for building packages, so the guest at the time
of the error is running ./configure for the package swig-v4.1.1.tar.gz
chec
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4 +-
includ
Clang on Windows does not seem to know the "gcc_struct" attribute
and emits a warning when we try to use it. Add an additional check
here with __has_attribute() to avoid this problem.
Signed-off-by: Thomas Huth
---
include/qemu/compiler.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
di
The 64-bit MSYS2 job often times out in our CI, though we already have
limited it to a very minimum by using --without-default-devices etc.
GCC is incredibly slow here. By using Clang instead of GCC, the job
is ca. 15 minutes faster - that's enough buffer to avoid the timeouts
here.
The caveat is
On 7/28/23 07:23, Claudio Fontana wrote:
It is a test environment for building packages, so the guest at the time of the
error is running ./configure for the package swig-v4.1.1.tar.gz
checking build system type... s390x-ibm-linux-gnu^M
checking host system type... s390x-ibm-linux-gnu^M
checkin
We might want to compile QEMU with Clang on Windows - but it
does not support the __attribute__((gcc_struct)) yet. So we
have to make sure that the structs will stay the same when
the compiler uses the "ms_struct" layout. The VTD_IR_TableEntry
struct is affected - rewrite it a little bit so that it
We are struggeling with timeouts in the 64-bit MSYS2 job. Clang seems
to be a little bit faster, so let's use this compiler now instead.
There is a problem with compiling the spice headers with Clang, though,
so we can only test this in the 32-bit builds with GCC now. And we have
to disable dbus-d
Nitpick: the bug was introduced between 6.2.0 and 7.0.0, so "qemu >= v7.0.0"
~Markus
On 2023-07-28 06:54, Helge Deller wrote:
> Commit 7f4f0d9ea870 ("linux-user/arm: Implement __kernel_cmpxchg with host
> atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
> content, but mi
From: Daniel P. Berrangé
Although they share a common parent, the two msys jobs still have
massive duplication in their script definitions that can easily be
collapsed.
Signed-off-by: Daniel P. Berrangé
Message-Id: <20230726161942.229093-1-berra...@redhat.com>
Signed-off-by: Thomas Huth
---
.
The fix in arm_kernel_cmpxchg64_helper probably should use tswap64() instead
of tswap32().
~Markus
On 2023-07-28 06:54, Helge Deller wrote:
> Commit 7f4f0d9ea870 ("linux-user/arm: Implement __kernel_cmpxchg with host
> atomics") switched to use qatomic_cmpxchg() to swap a word with the memory
> c
From: Marc-André Lureau
../ui/dbus-listener.c:236:9: error: expected expression
Error *err = NULL;
See:
https://gitlab.com/qemu-project/qemu/-/issues/1782#note_1488517427
Reviewed-by: Thomas Huth
Signed-off-by: Marc-André Lureau
---
ui/dbus-listener.c | 3 ++-
1 file changed, 2 inser
On 7/28/23 15:45, Claudio Fontana wrote:
> On 7/28/23 15:33, Richard Henderson wrote:
>> On 7/28/23 06:29, Claudio Fontana wrote:
>>> On 7/27/23 19:41, Richard Henderson wrote:
On 7/21/23 02:08, Claudio Fontana wrote:
> Thread 3 "qemu-system-s39" received signal SIGABRT, Aborted.
> [Sw
On Thu, 20 Jul 2023 15:15:13 +0800
xianglai li wrote:
> Turn on CPU hot-(un)plug custom for loongarch in the configuration file
>
> Cc: Xiaojuan Yang
> Cc: Song Gao
> Cc: "Michael S. Tsirkin"
> Cc: Igor Mammedov
> Cc: Ani Sinha
> Cc: Paolo Bonzini
> Cc: Richard Henderson
> Cc: Eduardo Hab
On 7/28/23 06:17, Peter Maydell wrote:
On Thu, 27 Jul 2023 at 17:33, Richard Henderson
wrote:
STGP writes to tag memory, it does not check it.
This happened to work because we wrote tag memory first
so that the check always succeeded.
So this is code cleanup to be more sensible, rather
than
On 7/28/23 06:29, Claudio Fontana wrote:
On 7/27/23 19:41, Richard Henderson wrote:
On 7/21/23 02:08, Claudio Fontana wrote:
Thread 3 "qemu-system-s39" received signal SIGABRT, Aborted.
[Switching to Thread 0x753516c0 (LWP 215975)]
(gdb) bt
#0 0x7730dabc in __pthread_kill_implement
If we want to make better decisions when auto-enabling extensions during
realize() we need a way to tell if an user set an extension manually.
The RISC-V KVM driver has its own solution via a KVMCPUConfig struct
that has an 'user_set' flag that is set during the Property set()
callback. The set() c
The bdrv_create_dirty_bitmap() function (which is also called by
bdrv_dirty_bitmap_create_successor()) uses bdrv_getlength(bs). This is
a wrapper around a coroutine, and when not called in coroutine context
would use bdrv_poll_co(). Such a call would trigger an assert() if the
correct AioContext ha
Add a new cpu_cfg_ext_is_user_set() helper to check if an extension was
set by the user in the command line. Use it inside
cpu_cfg_ext_auto_update() to verify if the user set a certain extension
and, if that's the case, do not change its value.
This will make us honor user choice instead of overwr
On 7/27/23 19:41, Richard Henderson wrote:
> On 7/21/23 02:08, Claudio Fontana wrote:
>> Thread 3 "qemu-system-s39" received signal SIGABRT, Aborted.
>> [Switching to Thread 0x753516c0 (LWP 215975)]
>> (gdb) bt
>> #0 0x7730dabc in __pthread_kill_implementation () at
>> /lib64/libc.so.
Hi,
This series, based on the work done in "[PATCH for-8.2 v6 00/11] riscv:
add 'max' CPU, deprecate 'any'", aims to solve two problem we have in
TCG properties handling:
- we are not checking for priv_ver when auto-enabling extensions during
realize();
- we are not able to honor user choice d
We'll have future usage for a function where, given an offset of the
struct RISCVCPUConfig, the flag is updated to a certain val.
Change all existing callers to use edata->ext_enable_offset instead of
'edata'.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 18 +-
On 7/28/23 06:34, Richard Henderson wrote:
On 7/27/23 20:54, Warner Losh wrote:
We're hitting an assert when we pass in alignment == 0 since that's not
a power of two. so pass in the ideal page size.
Signed-off-by: Warner Losh
---
bsd-user/mmap.c | 2 +-
1 file changed, 1 insertion(+), 1 de
Before adding support to detect if an extension was user set we need to
handle how we're enabling extensions in riscv_init_max_cpu_extensions().
object_property_set_bool() calls the set() callback for the property,
and we're going to use this callback to set the 'multi_ext_user_opts'
hash.
This me
On 7/28/23 15:33, Richard Henderson wrote:
> On 7/28/23 06:29, Claudio Fontana wrote:
>> On 7/27/23 19:41, Richard Henderson wrote:
>>> On 7/21/23 02:08, Claudio Fontana wrote:
Thread 3 "qemu-system-s39" received signal SIGABRT, Aborted.
[Switching to Thread 0x753516c0 (LWP 215975)]
>
On Thu, 20 Jul 2023 15:15:12 +0800
xianglai li wrote:
> 1.Create a new GED device type for Loongarch,
> mount cpu_madt function to update the ACPI table
madt changes should be its own patch
> 2.Update the APIC table for loongarch based on
> CPU information to support CPU hot-(un)plug
>
> Cc: X
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