Applied to the trivial tree, thank you!
/mjt
Applied to the trivial tree, thank you!
/mjt
在 2023/6/18 0:29, Guenter Roeck 写道:
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
From: qianfan Zhao
Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
for In-Car Entertainment us
Hi Marcelo,
On 16/6/23 19:44, Marcelo Tosatti wrote:
A regression has been detected in latency testing of KVM guests.
More specifically, it was observed that the cyclictest
numbers inside of an isolated vcpu (running on isolated pcpu) are:
# Max Lat
On 17/6/23 07:36, Bin Meng wrote:
sysconf(_SC_OPEN_MAX) returns the maximum number of files that
a process can have open at any time, which means the fd should
not be larger than or equal to the return value.
Signed-off-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- new patch: "test
On 17/6/23 07:36, Bin Meng wrote:
The code style does not conform with QEMU's. Correct it so that the
upcoming commit does not trigger checkpatch warnings.
Signed-off-by: Bin Meng
---
(no changes since v2)
Changes in v2:
- new patch: "tests/tcg/cris: Fix the coding style"
tests/tcg/cris/l
On 16/6/23 16:38, Kinsey Moore wrote:
The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
platforms have two priority queues with separate interrupt sources for
each. If the interrupt source for the second priority queue is not
connected, they work in polling mode only. This chang
Hi,
On Tue, May 23, 2023 at 06:04:58PM +0800, qianfangui...@163.com wrote:
> From: qianfan Zhao
>
> Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU,
> and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3
> for In-Car Entertainment usage, A40i and A40pro are varian
As said in the comment, instructions doing device I/Os must be at the end
of the TB in deterministic execution mode, icount mode or replay mode in
other words.
But cpu_io_recompile is still got called when I disable icount opt. The
corresponding MemoryRegion is apic-msi with the access address fee
A regression has been detected in latency testing of KVM guests.
More specifically, it was observed that the cyclictest
numbers inside of an isolated vcpu (running on isolated pcpu) are:
# Max Latencies: 00090 00096 00141
Where a maximum of
Hi
On Fri, Jun 16, 2023 at 7:41 AM Zhang Huasen
wrote:
> From: Huasen Zhang
>
> Hello,
>
> On Thu, 15 Jun 2023 12:57:55 +0200 Marc-André Lureau <
> marcandre.lur...@redhat.com>
> wrote:
> > Hi
> >
> > On Thu, Jun 15, 2023 at 12:36 PM Zhang Huasen
> > wrote:
> >
> > > If the monitor or the seri
On 6/16/23 01:52, Stefano Stabellini wrote:
Hi Peter, Richard,
Vikram fixed the gitlab test problem yet again. I appended a tiny qtest
fix at the end of the series.
Cheers,
Stefano
The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
Merge tag 'pull-riscv-to-apply
On 6/16/23 12:01, Song Gao wrote:
The following changes since commit 7efd65423ab22e6f5890ca08ae40c84d6660242f:
Merge tag 'pull-riscv-to-apply-20230614'
ofhttps://github.com/alistair23/qemu into staging (2023-06-14 05:28:51 +0200)
are available in the Git repository at:
https://gitlab.c
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