On 6/2/23 08:52, Peter Maydell wrote:
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document
On 6/2/23 08:52, Peter Maydell wrote:
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
all essentially the same instruction (system register access).
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 8
target/arm/tcg/translate-a64.c | 32 +---
On 6/2/23 08:52, Peter Maydell wrote:
Convert the MSR (immediate) insn to decodetree. Our implementation
has basically no commonality between the different destinations,
so we decode the destination register in a64.decode.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 13 +
On 6/2/23 08:52, Peter Maydell wrote:
Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
The old decoder handles these in handle_msr_i(), but
the architecture defines them as separate instructions
from MSR (immediate).
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode |
On 6/2/23 08:52, Peter Maydell wrote:
+# Barriers
+
+CLREX 1101 0101 0011 0011 imm:4 010 1
...
+ISB 1101 0101 0011 0011 imm:4 110 1
The two imm:4 fields are ignored; use instead?
Otherwise,
Reviewed-by: Richard Henderson
r~
On 6/2/23 08:52, Peter Maydell wrote:
Convert the various instructions in the hint instruction space
to decodetree.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 31
target/arm/tcg/translate-a64.c | 277 ++---
2 files changed, 185 inserti
On 6/2/23 08:52, Peter Maydell wrote:
The atomic memory operations are supposed to return the old memory
data value in the destination register. This value is not
sign-extended, even if the operation is the signed minimum or
maximum. (In the pseudocode for the instructions the returned data
val
On 6/2/23 14:43, Zhuojia Shen wrote:
Accessing EL0-accessible Debug Communication Channel (DCC) registers in
user mode emulation is currently enabled. However, it does not match
Linux behavior as Linux sets MDSCR_EL1.TDCC on startup to disable EL0
access to DCC (see __cpu_setup() in arch/arm64/m
On 6/2/23 14:25, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:02, Richard Henderson wrote:
133 files changed, 3022 insertions(+), 2728 deletions(-)
create mode 100644 include/exec/helper-gen-common.h
create mode 100644 include/exec/helper-proto-common.h
create mode 100644 include/e
On 6/2/23 02:54, Philippe Mathieu-Daudé wrote:
Now that gen_icount_io_start() is a simple wrapper to
translator_io_start(), inline it.
Signed-off-by: Philippe Mathieu-Daudé
---
target/ppc/translate.c | 63 --
target/ppc/power8-pmu-regs.c.inc | 10
On 6/2/23 03:02, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:03, Richard Henderson wrote:
This is a step toward making TranslationBlock agnostic
to the address size of the guest.
My understanding is tb_page_addr_t is QEMU internal, not exposed
to the guest, thus abi_ulong isn't required. It wa
On 6/2/23 14:14, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:03, Richard Henderson wrote:
Create helper-proto-common.h without the target specific portion.
Use that in tcg-op-common.h. Include helper-proto.h in target/arm
and target/hexagon before helper-info.c.inc; all other targets are
alread
On 6/2/23 14:17, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:03, Richard Henderson wrote:
Create helper-gen-common.h without the target specific portion.
Use that in tcg-op-common.h. Reorg headers in target/arm to
ensure that helper-gen.h is included before helper-info.c.inc.
All other targets
On 6/2/23 14:29, Philippe Mathieu-Daudé wrote:
On 31/5/23 06:02, Richard Henderson wrote:
Create tcg/tcg-op-common.h, moving everything that does not concern
TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header
instead of tcg-op.h, in preparation for compiling tcg/ only once.
Signed-
On 6/2/23 15:58, Philippe Mathieu-Daudé wrote:
CONFIG_USER_ONLY is the opposite of CONFIG_SOFTMMU.
Replace !CONFIG_SOFTMMU negation by the positive form
which is clearer when reviewing code.
CONFIG_SOFTMMU should be reserved for the actual softmmu tlb, which we *should* be able to
enable for u
On 6/2/23 15:46, Philippe Mathieu-Daudé wrote:
Not very interesting code shuffle, but this was in
the way of another big cleanup. So sending apart.
BTW this file isn't covered in MAINTAINERS:
$ ./scripts/get_maintainer.pl -f target/i386/helper.c
get_maintainer.pl: No maintainers found
Ph
On 6/2/23 15:30, Philippe Mathieu-Daudé wrote:
int_helper.c only contains system emulation code:
remove the #ifdef'ry and move the file to the meson
softmmu source set.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/int_helper.c | 3 ---
target/hppa/meson.build | 2 +-
2 files change
On 6/2/23 10:18, Thomas Huth wrote:
For the average user, it is likely quite difficult which library is
responsible for different features that QEMU supports. Let's make
it a little bit easier for them and put some libraries into separate
groups in the summary output of meson.
Thomas Huth (3):
On 6/2/23 07:22, Peter Maydell wrote:
The atomic memory operations are supposed to return the old memory
data value in the destination register. This value is not
sign-extended, even if the operation is the signed minimum or
maximum. (In the pseudocode for the instructions the returned data
val
On 6/1/23 14:53, Zhuojia Shen wrote:
Zhuojia Shen (2):
target/arm: allow DC CVA[D]P in user mode emulation
tests/tcg/aarch64: add DC CVA[D]P tests
target/arm/helper.c | 6 +--
tests/tcg/aarch64/Makefile.target | 11 ++
tests/tcg/aarch64/dcpodp.c| 63 +
On 6/2/23 09:34, Thomas Huth wrote:
There is no need to disable this useful compiler warning for
all versions of the SDL. Unfortunately, various versions are
buggy (beside SDL 2.0.8, the version 2.26.0 and 2.26.1 are
broken, too, seehttps://github.com/libsdl-org/SDL/issues/6619 ),
but we can use
In order to support large number of vcpus, a newer 64-bit SMBIOS
entry point type is needed. Therefore, upgrade the default SMBIOS version
for PC machines to SMBIOS 3.0 for newer systems. Then increase the maximum
number of vCPUs for Q35 models to 1024, which is the limit for KVM.
Changes from V2:
On 6/2/23 05:16, Rob Bradford wrote:
+#if TARGET_LONG_BITS == 32
+static bool trans_amocas_w(DisasContext *ctx, arg_amocas_w *a)
You need to eliminate all of the ifdefs, because we can switch a 64-bit cpu into 32-bit
mode -- get_xl(ctx) shows which mode we are in.
r~
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
In case KVM could not support the specified number of vcpus, QEMU would
return the following error message:
qemu-system-x86_64: kvm_init_vcpu: kvm_get_vcp
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
models. This is necessary to avoid the following message when launching
a VM wit
On 6/2/23 08:07, Andrew Jones wrote:
On Fri, Jun 02, 2023 at 04:39:20PM +0200, Robbin Ehn wrote:
On Fri, 2023-06-02 at 16:02 +0200, Andrew Jones wrote:
On Fri, Jun 02, 2023 at 11:41:11AM +0200, Robbin Ehn wrote:
...
+#if defined(TARGET_RISCV)
+case TARGET_NR_riscv_hwprobe:
+{
Th
On 6/2/23 07:02, Andrew Jones wrote:
+struct riscv_hwprobe {
+int64_t key;
+uint64_t value;
+};
The above is all uapi so Linux's arch/riscv/include/uapi/asm/hwprobe.h
should be picked up on Linux header update. You'll need to modify the
script, scripts/update-linux-headers.sh, to do th
On 6/2/23 02:41, Robbin Ehn wrote:
+struct riscv_hwprobe {
+int64_t key;
+uint64_t value;
+};
This needs to use abi_llong and abi_ullong, as the guest may not have the same alignment
requirements as the host.
+case RISCV_HWPROBE_KEY_MVENDORID:
+pair->value = cf
This implements the AES64DSM instruction. This was the last use
of aes64_operation and its support macros, so remove them all.
Signed-off-by: Richard Henderson
---
target/riscv/crypto_helper.c | 101 ---
1 file changed, 10 insertions(+), 91 deletions(-)
diff --g
This array is no longer used.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 7 --
crypto/aes.c | 264 ---
2 files changed, 271 deletions(-)
diff --git a/include/crypto/aes.h b/include/crypto/aes.h
index aa8b54065d..99209f51b9 10064
Add a primitive for InvMixColumns.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 3 ++
include/crypto/aes-round.h| 18 +
crypto/aes.c | 57 +++
3 files changed, 78 insertions(+)
diff --git a/hos
This implements the AES64ES instruction.
Signed-off-by: Richard Henderson
---
target/riscv/crypto_helper.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 2ef30281b1..82d7f3a060 100644
--- a/target/riscv
Add a primitive for InvSubBytes + InvShiftRows.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 3 ++
include/crypto/aes-round.h| 18 +++
crypto/aes.c | 46 +++
3 files changed, 67 insertions(+)
d
This implements the VCIPHER instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 444beb1779..c7f8b39e9a 100644
--- a/target/ppc/int_hel
Detect AES in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/aes-round.h | 204 ++
host/include/aarch64/host/cpuinfo.h | 1 +
util/cpuinfo-aarch64.c| 2 +
3 files changed, 207 insertions(+)
create
These arrays are no longer used outside of aes.c.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 25 -
crypto/aes.c | 33 +
2 files changed, 21 insertions(+), 37 deletions(-)
diff --git a/include/crypto/aes.h b/include
This implements the VNCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b49e17685b..444beb1779 100644
--- a/target/ppc/int_h
These arrays are no longer used, replaced by AES_SH_*, AES_ISH_*.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 4
crypto/aes.c | 14 --
2 files changed, 18 deletions(-)
diff --git a/include/crypto/aes.h b/include/crypto/aes.h
index 24b073d569..aa8b54065d
This implements the AES64ESM instruction.
Signed-off-by: Richard Henderson
---
target/riscv/crypto_helper.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 64004b2329..71694b787c 100644
--- a/target
This implements the AESDEC instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index c7a2c586f4..e666bd5068 100644
--- a/target/i386/ops_sse.h
+++
This implements the AES64IM instruction.
Signed-off-by: Richard Henderson
---
target/riscv/crypto_helper.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 08191b4b2a..64004b2329 100644
--- a/ta
Add a primitive for InvSubBytes + InvShiftRows +
AddRoundKey + InvMixColumns.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 4
include/crypto/aes-round.h| 21 +
crypto/aes.c | 20
3
This implements the AES64DS instruction.
Signed-off-by: Richard Henderson
---
target/riscv/crypto_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 82d7f3a060..08191b4b2a 100644
--- a/target/riscv/
Add a primitive for InvSubBytes + InvShiftRows +
InvMixColumns + AddRoundKey.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 4 ++
include/crypto/aes-round.h| 21 ++
crypto/aes.c | 56 +++
3 files
Add a primitive for SubBytes + ShiftRows + MixColumns + AddRoundKey.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 4 ++
include/crypto/aes-round.h| 21 ++
crypto/aes.c | 56 +++
3 files changed,
This implements the AESD instruction.
Signed-off-by: Richard Henderson
---
target/arm/tcg/crypto_helper.c | 37 +++---
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index 5cebc88f5f..d7b
This implements the VNCIPHER instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index c7f8b39e9a..8ae10ad748 100644
--- a/target/ppc/i
This implements the AESENC instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 0187651140..c7a2c586f4 100644
--- a/target/i386/ops_sse.h
+++
This method uses one uint32_t * 256 table instead of 4,
which means its data cache overhead is less.
Signed-off-by: Richard Henderson
---
crypto/aes.c | 41 -
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/crypto/aes.c b/crypto/aes.c
index
Add a primitive for MixColumns.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 3 ++
include/crypto/aes-round.h| 18 +
crypto/aes.c | 58 +++
3 files changed, 79 insertions(+)
diff --git a/host/i
This implements the AESENCLAST instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index fb63af7afa..31e1f6edc7 100644
--- a/target/i386/ops_sse.h
+
Use a shared driver and backends for i386, aarch64, ppc64, riscv64.
Signed-off-by: Richard Henderson
---
tests/tcg/aarch64/test-aes.c| 58
tests/tcg/i386/test-aes.c | 68 +
tests/tcg/ppc64/test-aes.c | 116 +++
tests/tcg/riscv
https://gitlab.com/juan.quintela/qemu.git
tags/migration-20230602-pull-request
for you to fetch changes up to b861383c2690501ff2687f9ef9268b128b0fb3b3:
qtest/migration: Document live=true cases (2023-06-02 11:46:20 +0200)
This implements the AESE instruction.
Signed-off-by: Richard Henderson
---
target/arm/tcg/crypto_helper.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index 75882d9ea3..5cebc88f5f 100644
---
Start adding infrastructure for accelerating guest AES.
Begin with a SubBytes + ShiftRows primitive.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 15 +
include/crypto/aes-round.h| 41 +++
crypto/aes.c
This implements the AESIMC instruction. We have converted everything
to crypto/aes-round.h; crypto/aes.h is no longer needed.
Signed-off-by: Richard Henderson
---
target/arm/tcg/crypto_helper.c | 33 ++---
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git
Detect AES in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
host/include/i386/host/aes-round.h | 148 +++
host/include/i386/host/cpuinfo.h | 1 +
host/include/x86_64/host/aes-round.h | 1 +
util/cpuinfo-i386.c | 3 +
This implements the AESMC instruction.
Signed-off-by: Richard Henderson
---
target/arm/tcg/crypto_helper.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c
index d7b644851f..a0fec08771 100644
--- a
This implements the AESDECLAST instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 31e1f6edc7..036eabdf95 100644
--- a/target/i386/ops_sse.h
++
We do not currently have a table in crypto/ for
just MixColumns. Move both tables for consistency.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 6 ++
crypto/aes.c | 142
target/arm/tcg/crypto_helper.c | 143 ++
This implements the VCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d97a7f1f28..b49e17685b 100644
--- a/target/ppc/int_h
This implements the AESIMC instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h
index 036eabdf95..0187651140 100644
--- a/target/i386/ops_sse.h
+++ b/t
Split these helpers so that we are not passing 'decrypt'
within the simd descriptor.
Signed-off-by: Richard Henderson
---
target/arm/helper.h | 2 ++
target/arm/tcg/sve.decode | 4 ++--
target/arm/tcg/crypto_helper.c | 37 +++--
target/arm/tcg/tra
These symbols will avoid the indirection through memory
when fully unrolling some new primitives.
Signed-off-by: Richard Henderson
---
crypto/aes.c | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/crypto/aes.c b/crypto/aes.c
Inspired by Ard Biesheuvel's RFC patches for accelerating AES
under emulation, provide a set of primitives that maps between
the guest and host fragments.
There is a small guest correctness test case.
I think the end result is quite a bit cleaner, since the logic
is now centralized, rather than s
On 6/2/23 10:33, Eric Blake wrote:
The following changes since commit a86d7b9ec0adb2f1efce8ab30d9ed2b72db0236e:
Merge tag 'migration-20230601-pull-request'
ofhttps://gitlab.com/juan.quintela/qemu into staging (2023-06-01 20:59:28
-0700)
are available in the Git repository at:
https://
On 31/5/23 06:03, Richard Henderson wrote:
If CONFIG_USER_ONLY is ok generically, so is CONFIG_SOFTMMU,
because they are exactly opposite.
Signed-off-by: Richard Henderson
---
include/exec/poison.h | 1 -
scripts/make-config-poison.sh | 5 +++--
2 files changed, 3 insertions(+), 3 d
On 3/6/23 00:58, Philippe Mathieu-Daudé wrote:
CONFIG_SOFTMMU is the opposite of CONFIG_USER_ONLY.
Now that CONFIG_SOFTMMU isn't poisoined anymore,
replace !CONFIG_USER_ONLY negation by the positive
form which is clearer when reviewing code.
Change mostly done mechanically using:
$ sed -i -e
On 3/6/23 00:58, Philippe Mathieu-Daudé wrote:
CONFIG_SOFTMMU is the opposite of CONFIG_USER_ONLY.
Now that CONFIG_SOFTMMU isn't poisoined anymore,
replace !CONFIG_USER_ONLY negation by the positive
form which is clearer when reviewing code.
Change mostly done mechanically using:
$ sed -i -e
Since CONFIG_SOFTMMU is poisoned, we are using its opposite
form via "!CONFIG_USER_ONLY" (because CONFIG_USER_ONLY is
not poisoned).
Since patch [2] unpoison CONFIG_SOFTMMU, we can remove the
kludge, resulting is a more logical code to review.
Personally I like the resulting code, but I can unders
CONFIG_USER_ONLY is the opposite of CONFIG_SOFTMMU.
Replace !CONFIG_SOFTMMU negation by the positive form
which is clearer when reviewing code.
Change mostly done mechanically using:
$ sed -i -e 's/!defined(CONFIG_SOFTMMU)/defined(CONFIG_USER_ONLY)/' \
-e 's/ifndef CONFIG_SOFTMMU/ifd
Since commit 604664726f ("target/i386: Restrict cpu_exec_interrupt()
handler to sysemu"), do_cpu_sipi() isn't called anymore on user
emulation. Remove the now pointless stub.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/cpu.h| 3 ++-
target/i386/helper.c | 3 ---
2 files changed, 2
Move the #ifdef'ry inside do_cpu_init() instead of
declaring an empty stub for user emulation.
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/helper.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 792c8eb
Not very interesting code shuffle, but this was in
the way of another big cleanup. So sending apart.
BTW this file isn't covered in MAINTAINERS:
$ ./scripts/get_maintainer.pl -f target/i386/helper.c
get_maintainer.pl: No maintainers found
Philippe Mathieu-Daudé (2):
target/i386/helper: Rem
int_helper.c only contains system emulation code:
remove the #ifdef'ry and move the file to the meson
softmmu source set.
Signed-off-by: Philippe Mathieu-Daudé
---
target/hppa/int_helper.c | 3 ---
target/hppa/meson.build | 2 +-
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/tar
Accessing EL0-accessible Debug Communication Channel (DCC) registers in
user mode emulation is currently enabled. However, it does not match
Linux behavior as Linux sets MDSCR_EL1.TDCC on startup to disable EL0
access to DCC (see __cpu_setup() in arch/arm64/mm/proc.S).
This patch fixes access_tdc
On 31/5/23 06:02, Richard Henderson wrote:
Create tcg/tcg-op-common.h, moving everything that does not concern
TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header
instead of tcg-op.h, in preparation for compiling tcg/ only once.
Signed-off-by: Richard Henderson
---
include/tcg/tcg
On 31/5/23 06:02, Richard Henderson wrote:
133 files changed, 3022 insertions(+), 2728 deletions(-)
create mode 100644 include/exec/helper-gen-common.h
create mode 100644 include/exec/helper-proto-common.h
create mode 100644 include/exec/helper-gen.h.inc
create mode 100644 includ
On 31/5/23 06:03, Richard Henderson wrote:
Make tcg_gen_callN a static function. Create tcg_gen_call[0-7]
functions for use by helper-gen.h.inc.
Removes a multiplicty of calls to __stack_chk_fail, saving up
to 143kiB of .text space as measured on an x86_64 host.
Old New Less%Chang
On 31/5/23 06:03, Richard Henderson wrote:
Create helper-gen-common.h without the target specific portion.
Use that in tcg-op-common.h. Reorg headers in target/arm to
ensure that helper-gen.h is included before helper-info.c.inc.
All other targets are already correct in this regard.
Signed-off-
On 31/5/23 06:03, Richard Henderson wrote:
Create helper-proto-common.h without the target specific portion.
Use that in tcg-op-common.h. Include helper-proto.h in target/arm
and target/hexagon before helper-info.c.inc; all other targets are
already correct in this regard.
Signed-off-by: Richar
On 31/5/23 06:03, Richard Henderson wrote:
This had been pulled in via exec/exec-all.h, via exec/translator.h,
but the include of exec-all.h will be removed.
Signed-off-by: Richard Henderson
---
target/hexagon/translate.c | 1 +
target/loongarch/translate.c | 3 +--
target/mips/tcg/transl
On 31/5/23 06:03, Richard Henderson wrote:
This had been pulled in via exec/translator.h,
but the include of exec-all.h will be removed.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate.h | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
On 6/1/23 18:31, Weiwei Li wrote:
Even though MPRV normally can be set to 1 in M mode, it seems possible to set it to 1 in
other mode by gdbstub.
That would seem to be a gdbstub bug, since it is cleared on exit from M-mode, and cannot
be set again until we re-enter M-mode.
r~
On 31/5/23 06:03, Richard Henderson wrote:
Two headers are not required for the rest of the
contents of plugin-gen.h.
Signed-off-by: Richard Henderson
---
include/exec/plugin-gen.h | 2 --
1 file changed, 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 31/5/23 06:03, Richard Henderson wrote:
This function is only used in translator.c, and uses a
target-specific typedef, abi_ptr.
Signed-off-by: Richard Henderson
---
include/exec/plugin-gen.h | 22 --
accel/tcg/translator.c| 21 +
2 files chang
On 31/5/23 06:03, Richard Henderson wrote:
The bug was hidden because they happen to have the same values.
Signed-off-by: Richard Henderson
---
tcg/region.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 31/5/23 06:03, Richard Henderson wrote:
Reduce the header to only bswap.h and cpu_ldst.h.
Move exec/translate-all.h to translator.c.
Reduce tcg.h and tcg-op.h to tcg-op-common.h.
Remove otherwise unused headers.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 6 +-
ac
On 2/6/23 17:52, Peter Maydell wrote:
Convert the instructions in the load/store register (pointer
authentication) group ot decodetree: LDRAA, LDRAB.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 7 +++
target/arm/tcg/translate-a64.c | 83 +++-
Hi Peter,
On 2/6/23 17:52, Peter Maydell wrote:
Convert the LDR and STR instructions which use a 12-bit immediate
offset to decodetree. We can reuse the existing LDR and STR
trans functions for these.
Signed-off-by: Peter Maydell
---
target/arm/tcg/a64.decode | 25
target/arm
On 2/6/23 19:48, Peter Maydell wrote:
Coverity doesn't like the way we might end up calling getgroups()
with a NULL grouplist pointer. This is fine for the special case
of gidsetsize == 0, but we will also do it if the guest passes
us a negative gidsetsize. (CID 1512465)
Explicitly fail the nega
On 2/6/23 19:18, Thomas Huth wrote:
Let's make it easier for the users to spot audio-related entries
in the summary of the meson output.
Signed-off-by: Thomas Huth
---
meson.build | 32 ++--
1 file changed, 18 insertions(+), 14 deletions(-)
Reviewed-by: Philippe
On 2/6/23 19:18, Thomas Huth wrote:
Let's make it easier for the users to spot network-related entries
in the summary of the meson output.
Signed-off-by: Thomas Huth
---
meson.build | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/meson.build b/meson.build
in
On 2/6/23 19:18, Thomas Huth wrote:
Let's make it easier for the users to spot UI-related entries in
the summary of the meson output.
Signed-off-by: Thomas Huth
---
meson.build | 35 +--
1 file changed, 21 insertions(+), 14 deletions(-)
diff --git a/meson.bui
On 2/6/23 18:27, Laurent Vivier wrote:
in vhost_dev_enable_notifiers(), if virtio_bus_set_host_notifier(true)
fails, we call vhost_dev_disable_notifiers() that executes
virtio_bus_set_host_notifier(false) on all queues, even on queues that
have failed to be initialized.
This triggers a core dump
On 2/6/23 16:22, Peter Maydell wrote:
The atomic memory operations are supposed to return the old memory
data value in the destination register. This value is not
sign-extended, even if the operation is the signed minimum or
maximum. (In the pseudocode for the instructions the returned data
val
idef-parser emits safety checks around shifts and extensions to deal
with shift amounts larger than the TCGv size and extensions of 0-bit
regions. These safety checks sometimes result in dead branches, which
coverity detects and warns about.
This commits silences these dead code warnings in emitt
Matthew Rosato 于2023年6月3日周六 02:41写道：
>
> On 6/2/23 2:18 PM, Sam Li wrote:
> > Matthew Rosato 于2023年6月1日周四 02:21写道：
> >>
> >> On 5/15/23 12:04 PM, Stefan Hajnoczi wrote:
> >>> From: Sam Li
> >>>
> >>> Use get_sysfs_str_val() to get the string value of device
> >>> zoned model. Then get_sysfs_zone
On 6/2/23 2:18 PM, Sam Li wrote:
> Matthew Rosato 于2023年6月1日周四 02:21写道：
>>
>> On 5/15/23 12:04 PM, Stefan Hajnoczi wrote:
>>> From: Sam Li
>>>
>>> Use get_sysfs_str_val() to get the string value of device
>>> zoned model. Then get_sysfs_zoned_model() can convert it to
>>> BlockZoneModel type of Q
Matthew Rosato 于2023年6月1日周四 02:21写道：
>
> On 5/15/23 12:04 PM, Stefan Hajnoczi wrote:
> > From: Sam Li
> >
> > Use get_sysfs_str_val() to get the string value of device
> > zoned model. Then get_sysfs_zoned_model() can convert it to
> > BlockZoneModel type of QEMU.
> >
> > Use get_sysfs_long_val()
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