On Mon, 2023-05-15 at 21:57 +0200, Juan Quintela wrote:
> Just create a variable for it, the same way that multifd does. This
> way it is safe to use for other thread, etc, etc.
>
> Signed-off-by: Juan Quintela
> ---
> migration/migration-stats.h | 4
> migration/migration-stats.c | 5 ++
On Mon, 2023-05-15 at 21:57 +0200, Juan Quintela wrote:
> Since previous commit, we calculate how much data we have send with
> migration_transferred_bytes() so no need to maintain this counter and
> remember to always update it.
>
> Signed-off-by: Juan Quintela
> Reviewed-by: Cédric Le Goater
>
On Mon, 2023-05-15 at 21:57 +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> Reviewed-by: Cédric Le Goater
> ---
> migration/migration-stats.h | 8 +++-
> migration/migration-stats.c | 7 +--
> migration/migration.c | 2 +-
> 3 files changed, 13 insertions(+), 4 deletio
It's possible to compile QEMU without the USB devices (e.g. when using
"--without-default-devices" as option for the "configure" script).
To be still able to run the loongson3-virt machine in default mode with
such a QEMU binary, we have to check here for the availability of the
devices first befor
[ ... ]
However, regarding Cédric's log above, a reboot is expected on the first
boot of a fresh image when there's valid VPD available. For the first
boot of a fresh image we configure the kernel with a minimal devicetree
that allows us to read the VPD data. This determines the system we're
act
On 5/23/23 15:52, Cédric Le Goater wrote:
On 5/22/23 18:02, Narayana Murty N wrote:
Currently on PPC64 qemu always dumps the guest memory in
Big Endian (BE) format even though the guest running in Little Endian
The patch is surely correct. I have problems understanding the config
you are te
On Wed, May 24, 2023 at 01:09:30PM -0700, Richard Henderson wrote:
> Hi Eldon,
>
> New this morning are some odd failures in the container build stage, e.g
>
> https://gitlab.com/qemu-project/qemu/-/jobs/4345796216#L235
>
> cgroups: cgroup mountpoint does not exist: unknown
>
> There are severa
On 2023-05-24 22:33:36, Peter Zijlstra wrote:
> On Wed, May 24, 2023 at 01:16:03PM -0700, Sean Christopherson wrote:
>
> > Atomics aren't memory barriers on all architectures, e.g. see the various
> > definitions of smp_mb__after_atomic().
> >
> > Even if atomic operations did provide barriers, u
On Mon, 2023-05-15 at 21:57 +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> Reviewed-by: Cédric Le Goater
> ---
> migration/migration-stats.c | 8 ++--
> migration/trace-events | 3 +++
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/migration/migration
On Mon, 2023-05-15 at 21:56 +0200, Juan Quintela wrote:
> Once there rename it to migration_transferred_bytes() and pass a
> QEMUFile instead of a migration object.
>
> Signed-off-by: Juan Quintela
> Reviewed-by: Cédric Le Goater
> ---
> migration/migration-stats.h | 11 +++
> migration
On Mon, 2023-05-15 at 21:56 +0200, Juan Quintela wrote:
> These way we can make them atomic and use this functions from any
> place. I also moved all functions that use rate_limit to
> migration-stats.
>
> Functions got renamed, they are not qemu_file anymore.
>
> qemu_file_rate_limit -> migrati
On Tue, May 23, 2023 at 6:50 PM Tommy Wu wrote:
>
> Create the AON device when we realize the sifive_e machine.
> This patch only implemented the functionality of the watchdog timer,
> not all the functionality of the AON device.
>
> Signed-off-by: Tommy Wu
> Reviewed-by: Frank Chang
Reviewed-b
On Tue, May 23, 2023 at 9:46 PM Tommy Wu wrote:
>
> When we change the cpu extension state after the cpu is
> realized, we cannot print the value of some CSRs in the remote
> gdb debugger. The root cause is that the dynamic CSR xml is
> generated when the cpu is realized.
>
> This patch add a func
On Fri, May 19, 2023 at 12:38 PM Yin Wang wrote:
>
> Command "qemu-system-riscv64 -machine virt
> -m 2G -smp 1 -numa node,mem=1G -numa node,mem=1G"
> would trigger this problem.Backtrace with:
> #0 0x55b5b1a4 in riscv_numa_get_default_cpu_node_id at
> ../hw/riscv/numa.c:211
> #1 0x00
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
wrote:
>
> Hi,
>
> This series fix a QOM issue with the OpenTitanState
> structure, noticed while auditing QOM relations globally.
>
> All patches are trivial to review.
>
> Regards,
>
> Phil.
>
> Philippe Mathieu-Daudé (5):
> hw/riscv/opent
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
wrote:
>
> OpenTitanState is the 'machine' (or 'board') state: it isn't
> a SysBus device, but inherits from the MachineState type.
> Correct the instance size.
> Doing so we avoid leaking an OpenTitanState pointer in
> opentitan_machine_init
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
wrote:
>
> Expand the DEFINE_MACHINE() macro, converting the class_init()
> handler.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/riscv/opentitan.h | 3 ++-
> hw/riscv/opentitan.c
On Sat, May 20, 2023 at 3:46 PM Philippe Mathieu-Daudé
wrote:
>
> QOM type names are usually defined as TYPE_FOO.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Alistair
> ---
> include/hw/riscv/opentitan.h | 2 ++
> hw/riscv/opentitan.c | 2 +-
> 2 files cha
On Sat, May 20, 2023 at 3:46 PM Philippe Mathieu-Daudé
wrote:
>
> When multiple QOM types are registered in the same file,
> it is simpler to use the the DEFINE_TYPES() macro. Replace
> the type_init() / type_register_static() combination. This
> is in preparation of adding the OpenTitan machine t
On Sat, May 20, 2023 at 3:47 PM Philippe Mathieu-Daudé
wrote:
>
> Follow QOM style which declares FOO_init() as instance
> initializer and FOO_class_init() as class initializer:
> rename the OpenTitan machine class/instance init()
> accordingly.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed
On Mon, 2023-05-15 at 21:56 +0200, Juan Quintela wrote:
> That is the moment we know we have transferred something.
>
> Signed-off-by: Juan Quintela
> Reviewed-by: Cédric Le Goater
> ---
> migration/qemu-file.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/mig
Hello Cedric,
On 5/24/23 1:36 AM, Cédric Le Goater wrote:
On 5/23/23 23:45, Ninad Palsule wrote:
The current modeling of Rainier machine creates zero filled
VPDs(EEPROMs).
This makes some services and applications unhappy and causing them to
fail.
Hence this drop adds some fabricated data for
On Mon, 2023-05-15 at 21:56 +0200, Juan Quintela wrote:
> It is a time that needs to be cleaned each time cancel migration.
> Once there create migration_time_since() to calculate how time since a
> time in the past.
>
> Signed-off-by: Juan Quintela
>
> ---
>
> Rename to migration_time_since (c
On Fri, 2023-05-05 at 17:20 +0200, Mickaël Salaün wrote:
> # How does it work?
>
> This implementation mainly leverages KVM capabilities to control the
> Second
> Layer Address Translation (or the Two Dimensional Paging e.g.,
> Intel's EPT or
> AMD's RVI/NPT) and Mode Based Execution Control (Inte
https://github.com/legoater/qemu/ tags/pull-vfio-20230524
for you to fetch changes up to dbdea0dbfe2cef9ef6c752e9077e4fc98724194c:
util/vfio-helpers: Use g_file_read_link() (2023-05-24 09:21:22 +0200)
vfio queue:
* Fix for a memory
On 5/25/2023 1:02 AM, Richard Henderson wrote:
> On 5/24/23 06:35, Wu, Fei wrote:
>> On 5/23/2023 8:45 AM, Richard Henderson wrote:
>>> On 5/18/23 06:57, Fei Wu wrote:
+void HELPER(inc_exec_freq)(void *ptr)
+{
+ TBStatistics *stats = (TBStatistics *) ptr;
+ tcg_debug_asser
On 5/24/2023 3:20 PM, Edgecombe, Rick P wrote:
On Fri, 2023-05-05 at 17:20 +0200, Mickaël Salaün wrote:
# How does it work?
This implementation mainly leverages KVM capabilities to control the
Second
Layer Address Translation (or the Two Dimensional Paging e.g.,
Intel's EPT or
AMD's RVI/NPT) an
On Wed, 24 May 2023, at 17:14, Joel Stanley wrote:
> On Wed, 24 May 2023 at 06:38, Cédric Le Goater wrote:
>>
>> But, I also got this :
>>
>>root@p10bmc:~# [ 91.656331] watchdog: watchdog0: watchdog did not stop!
>>[ 91.734858] systemd-shutdown[1]: Using hardware watchdog 'aspeed_wd
On Wed, May 24, 2023, Peter Zijlstra wrote:
> On Wed, May 24, 2023 at 01:16:03PM -0700, Sean Christopherson wrote:
> > Of course, the only accesses outside of mmu_lock are reads, so on x86 that
> > "atomic" access is just a READ_ONCE() load, but that's not the case for all
> > architectures.
>
> T
Based on the kernel commit "b0563468ee x86/CPU/AMD: Disable XSAVES on
AMD family 0x17", host system with EPYC-Rome can clear XSAVES capability
bit. In another words, EPYC-Rome host without XSAVES can occur. Thus, we
need an EPYC-Rome cpu model (without this feature) that matches the
solution of fix
On 5/22/23 10:41, Camilla Conte wrote:
Here's a second version (v2) of patches to support the Kubernetes runner for
Gitlab CI.
You can find the v1 thread here:
https://lore.kernel.org/qemu-devel/20230407145252.32955-1-cco...@redhat.com/.
Applied to master. With the k8s tag on the azure runne
NetBSD switches directly to IDLE state without switching the shift register to
input mode. Duplicate the existing ADB_STATE_IDLE logic in input mode from when
the shift register is in output mode which allows the ADB autopoll handler to
handle the response.
Signed-off-by: Mark Cave-Ayland
---
hw
The Quadra 800 has the enhanced ASC (EASC) audio chip which supports both the
legacy IRQ routing through VIA2 and also "A/UX" mode routing direct to the
CPU.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 30 --
1 file changed, 2
The swim chip provides an implementation of both Apple's IWM and ISM floppy disk
controllers. Split the existing implementation into separate register banks for
each controller, whilst also switching the IWM registers from 16-bit to 8-bit
as implemented in real hardware.
Signed-off-by: Mark Cave-A
It is needed because it defines the BIOSConfig area.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS| 2 +
hw/m68k/Kconfig| 1 +
hw/m68k/q800.c | 10 +++
hw/misc/Kconfig| 3 +
hw/misc/iosb.c | 156 +++
MacOS (un)helpfully leaves the FIFO engine running even when all the samples
have
been written to the hardware, and expects the FIFO status flags and IRQ to be
updated continuously.
Since not all audio backends guarantee an all-zero output when no data is
provided, explicitly generate an all-zero
Signed-off-by: Mark Cave-Ayland
---
hw/block/swim.c | 14 ++
hw/block/trace-events | 7 +++
2 files changed, 21 insertions(+)
diff --git a/hw/block/swim.c b/hw/block/swim.c
index 333da08ce0..7df36ea139 100644
--- a/hw/block/swim.c
+++ b/hw/block/swim.c
@@ -19,6 +19,7 @@
#
Update the IWM/ISM register block decoding to match the description given in the
"SWIM Chip Users Reference". This allows us to validate the device response to
the guest OS which currently only does just enough to indicate that the floppy
drive is unavailable.
Signed-off-by: Mark Cave-Ayland
---
This determines whether the Apple Sound Chip (ASC) is set to enhanced mode
(default) or to original mode. The real Q800 hardware used an EASC chip however
a lot of older software only works with the older ASC chip.
Adding this as a machine parameter allows QEMU to be used as an developer aid
for t
The MacOS toolbox ROM calculates the number of branches that can be executed
per millisecond as part of its timer calibration. Since modern hosts are
considerably quicker than original hardware, the negative counter reaches zero
before the calibration completes leading to division by zero later in
The djMEMC controller is used to store information related to the physical
memory
configuration.
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS | 2 +
hw/m68k/Kconfig | 1 +
hw/m68k/q800.c | 9 +++
hw/misc/Kconfig
According to the Apple Quadra 800 Developer Note document, the Quadra 800 ROM
consists of 2 ROM code sections based at offsets 0x0 and 0x80. A/UX attempts
to access the toolbox ROM at the lower offset during startup, so provide a
memory alias to allow the access to succeed.
Signed-off-by: Mark
The current use of aliased memory regions causes us 2 problems: firstly the
output of "info qom-tree" is absolutely huge and difficult to read, and
secondly we have already reached the internal limit for memory regions as
adding any new memory region into the mac-io region causes QEMU to assert
wit
A comparison between the rtc command table included in the comment and the code
itself shows that the decoding for PRAM addresses 0x0 to 0xf is being done on
the raw command, and not the shifted version held in value.
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 2 +-
1 file changed,
NetBSD assumes it can send its first ADB command after sending the ADB_BUSRESET
command in ADB_STATE_NEW without changing the state back to ADB_STATE_IDLE
first as detailed in the ADB protocol.
Add a workaround to detect this condition at the start of ADB enumeration
and send the next command writ
Analysis of the MacOS toolbox ROM code shows that on startup it attempts 2
separate reads of the seconds registers with commands 0x9d...0x91 followed by
0x8d..0x81 without resetting the command to its initial value. The PRAM seconds
value is only accepted when the values of the 2 separate reads mat
During the kernel timer calibration routine A/UX performs an unaligned access
across the T1CL and T1CH registers to read the entire 16-bit value in a
single memory access.
This triggers a bug in the QEMU softtlb implementation whereby the 2 separate
accesses are combined incorrectly losing the hig
This will enable us later to distinguish between QOM initialisation and machine
initialisation.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index bdccd93c7f..976da06231 100644
--- a/hw
The A/UX timer calibration loop runs continuously until 2 consecutive iterations
differ by at least 0x492 timer ticks. Modern hosts execute the timer calibration
loop so fast that this situation never occurs causing a hang on boot.
Use a similar method to Shoebill which is to randomly add 0x500 to
Tests on real Q800 hardware show that the ESCC is addressable at multiple
locations
within the ESCC memory region - at least 0xc000, 0xc020 (as expected by the
MacOS
toolbox ROM) and 0xc040.
All released NetBSD kernels before 10 use the 0xc000 address which causes a
fatal
error when running the
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 20 ++--
include/hw/m68k/q800.h | 1 +
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 6a000ceb75..c22a98d616 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -3
MacOS attempts a series of writes and reads over the entire RAM area in order
to determine the amount of RAM within the machine. Allow accesses to the
entire RAM area ignoring writes and always reading zero for areas where there
is no physical RAM installed to allow MacOS to detect the memory size
When the NetBSD kernel initialises it can leave the ADB interrupt asserted
depending upon where in the ADB poll cycle the MacOS ADB interrupt handler
is when the NetBSD kernel disables interrupts.
The NetBSD ADB driver uses the ADB interrupt state to determine if the ADB
is busy and refuses to sen
The Apple Sound Chip was primarily used by the Macintosh II to generate sound
in hardware which was previously handled by the toolbox ROM with software
interrupts.
Implement both the standard ASC and also the enhanced ASC (EASC) functionality
which is used in the Quadra 800.
Note that whilst real
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 13 +
include/hw/m68k/q800.h | 1 +
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index ee6175ceb4..6a000ceb75 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -371,7 +371
Ensure there is a space before the final closing brace for all global
properties.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index b35ecafbc7..1aead224e2 100644
--- a/hw/m68k/q8
Move all devices from the IO region to within the container in preparation
for updating the IO aliasing mechanism.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 6 ++
include/hw/m68k/q800.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
i
Co-developed-by: Laurent Vivier
Signed-off-by: Mark Cave-Ayland
---
hw/misc/mac_via.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 076d18e5fd..f90a22a067 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -1
MacOS reads this address to identify the hardware.
This is a basic implementation returning the ID of Quadra 800.
Details:
http://mess.redump.net/mess/driver_info/mac_technical_notes
"There are 3 ID schemes [...]
The third and most scalable is a machine ID register at 0x5ffc.
The top wo
This provides an overall container and owner for Machine-related objects such
as MemoryRegions.
Signed-off-by: Mark Cave-Ayland
---
MAINTAINERS| 1 +
hw/m68k/q800.c | 2 ++
include/hw/m68k/q800.h | 37 +
3 files changed, 40 insertions(+)
This series contains the remaining patches needed to allow QEMU's q800
machine to boot MacOS Classic when used in conjunction with a real
Quadra 800 ROM image. In fact with this series applied it is possible
to boot all of the following OSs:
- MacOS 7.1 - 8.1, with or without virtual memory enab
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 10 +-
include/hw/m68k/q800.h | 4 +++-
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c
index 976da06231..ee6175ceb4 100644
--- a/hw/m68k/q800.c
+++ b/hw/m68k/q800.c
@@ -363,7 +363
On 5/5/2023 8:20 AM, Mickaël Salaün wrote:
Hi,
This patch series is a proof-of-concept that implements new KVM features
(extended page tracking, MBEC support, CR pinning) and defines a new API to
protect guest VMs. No VMM (e.g., Qemu) modification is required.
The main idea being that kernel se
On 5/5/23 12:31, Sean Christopherson wrote:
> On Fri, May 05, 2023, Micka�l Sala�n wrote:
>>
>> On 05/05/2023 18:28, Sean Christopherson wrote:
>>> I have no doubt that we'll need to solve performance and scaling issues
>>> with the
>>> memory attributes implementation, e.g. to utilize xarr
On Wed, May 24, 2023 at 01:16:03PM -0700, Sean Christopherson wrote:
> Atomics aren't memory barriers on all architectures, e.g. see the various
> definitions of smp_mb__after_atomic().
>
> Even if atomic operations did provide barriers, using an atomic would be
> overkill
> and a net negative.
On Wed, May 24, 2023 at 11:42:15AM +0530, Kautuk Consul wrote:
> My comment was based on the assumption that "all atomic operations are
> implicit memory barriers". If that assumption is true then we won't need
It is not -- also see Documentation/atomic_t.txt.
Specifically atomic_read() doesn't
On Wed, May 24, 2023, Kautuk Consul wrote:
> On 2023-05-23 07:19:43, Sean Christopherson wrote:
> > On Tue, May 23, 2023, Kautuk Consul wrote:
> > > On 2022-07-06 16:20:10, Chao Peng wrote:
> > > > diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
> > > > index e9153b54e2a4..c262ebb1
Hi Eldon,
New this morning are some odd failures in the container build stage, e.g
https://gitlab.com/qemu-project/qemu/-/jobs/4345796216#L235
cgroups: cgroup mountpoint does not exist: unknown
There are several such failures in that pipeline. I've not seen this before, nor was it
happening y
The first move was incorrectly using TCG_TYPE_I32 while the second
move was correctly using TCG_TYPE_REG. This prevents a 64-bit host
from moving all 128-bits of the return value.
Fixes: ebebea53ef8 ("tcg: Support TCG_TYPE_I128 in
tcg_out_{ld,st}_helper_{args,ret}")
Signed-off-by: Richard Hender
On Sun, May 21, 2023 at 06:18:03PM +0300, Avihai Horon wrote:
> Implement switchover ack logic. This prevents the source from stopping
> the VM and completing the migration until an ACK is received from the
> destination that it's OK to do so.
>
> To achieve this, a new SaveVMHandlers handler swit
On Sun, May 21, 2023 at 06:18:02PM +0300, Avihai Horon wrote:
> Migration downtime estimation is calculated based on bandwidth and
> remaining migration data. This assumes that loading of migration data in
> the destination takes a negligible amount of time and that downtime
> depends only on netwo
Hello!
Sorry for a quite a big patch, but most of the changes are the same type.
Most of the patch is about a definition of new constants/structs and replacing
magic numbers with those constants.
Signed-off-by: Sergey Kambalin
---
hw/misc/bcm2835_property.c| 314
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
-int is_mpcore = 0;
+bool is_mpcore = rmc->mpcore_periphbase != 0;
bool is_pb = rmc->is_pb;
uint32_t proc_id = 0;
uint32_t sys_id;
ram_addr_t low_ram_size;
ram_addr_t ram_size = machine->ram_size;
-hwaddr pe
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
The realview_board_type enum is now unused. Remove it and have
all instances use the common realview_common_machine_init()
method.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 46 ++
1
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
Instead of having each machine instance resolve its loader
start address, set it once in their class_init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
Reviewed-
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
Mark the default NIC via the new MachineClass->default_nic setting
so that the machine-defaults code in vl.c can decide whether the
default NIC is usable or not (for example when compiling with the
"--without-default-devices" configure switch).
Ins
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
Instead of having each machine instance set whether EP/PB,
set it once in their class_init() handler.
Arguably this could be extracted from the board_id field.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 7 ---
1 file chan
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
Instead of having each machine instance resolve its board ID,
set it once in their class_init() handler.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
R
On 5/24/23 07:59, Philippe Mathieu-Daudé wrote:
Introduce realview_common_class_init() where we'll set
fields common to all Realview classes.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Richard H
On 5/24/23 07:58, Philippe Mathieu-Daudé wrote:
Introduce the abstract QOM TYPE_REALVIEW_MACHINE to
handle fields common to all Realview machines.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
Review
On 5/24/23 07:58, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file,
it is simpler to use the the DEFINE_TYPES() macro. Replace
the type_init() / type_register_static() combination.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 50 +++
On 5/24/23 07:58, Philippe Mathieu-Daudé wrote:
The 'break' statement terminates the execution of the nearest
enclosing 'for' statement in which it appears.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/arm/realview.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/h
Older versions of clang have missing runtime functions for arithmetic
with -fsanitize=undefined (see 464e3671f9d5c), so we cannot use
__int128_t for implementing Int128. But __int128_t is present,
data movement works, and can be use for atomic128.
Probe for both CONFIG_INT128_TYPE and CONFIG_INT1
With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic
load/store without cmpxchg16b.
Signed-off-by: Richard Henderson
---
host/include/x86_64/host/atomic128-ldst.h | 68 +++
1 file changed, 68 insertions(+)
create mode 100644 host/include/x86_64/host/atomic128-ldst.h
di
Changes for v3:
* Most of the v2 patch set merged, except x86_64 atomic128-ldst.h,
which failed testing with clang-11 with debian 11.
* New patch to change __int128_t detection.
* This in turn enabled CONFIG_ATOMIC128, which was not ideal.
This clang bug/mis-feature of using a cmpxc
On 24/5/23 19:31, Nicolas Saenz Julienne wrote:
We want to only enable '-Wno-unused-function' if glib's version is
smaller than '2.57.2' and has a G_DEFINE_AUTOPTR_CLEANUP_FUNC()
implementation that doesn't take into account unused functions. But the
compilation test isn't working as intended as
We currently print FAIL for the failure of a succ_* test, but don't
return a failure exit code. Instead, convert the script to emit
Test Anything Protocol, which gives visibility into each subtest
as well as not relying on exit codes.
Suggested-by: Paolo Bonzini
Signed-off-by: Richard Henderson
On Wed, May 17, 2023 at 7:49 AM Jason Wang wrote:
>
> On Wed, May 17, 2023 at 1:46 PM Eugenio Perez Martin
> wrote:
> >
> > On Wed, May 17, 2023 at 5:14 AM Jason Wang wrote:
> > >
> > > On Tue, May 9, 2023 at 11:44 PM Eugenio Pérez wrote:
> > > >
> > > > This allows to reset a vhost-vdpa device
Hi Andrea,
On Wed, May 24, 2023 at 03:50:34PM +, Andrea Bolognani wrote:
> On Tue, May 23, 2023 at 03:58:05PM +0530, Sunil V L wrote:
> > Currently, virt machine supports two pflash instances each with
> > 32MB size. However, the first pflash is always assumed to
> > contain M-mode firmware an
We want to only enable '-Wno-unused-function' if glib's version is
smaller than '2.57.2' and has a G_DEFINE_AUTOPTR_CLEANUP_FUNC()
implementation that doesn't take into account unused functions. But the
compilation test isn't working as intended as '-Wunused-function' isn't
enabled while running it
Taylor Simpson writes:
> Change Hexagon maintainer from Taylor Simpson to Brian Cain
> Put Taylor's gmail address in .mailmap
>
> Signed-off-by: Taylor Simpson
Thanks for all your efforts getting in Hexagon up-streamed and
supporting it over the years.
Reviewed-by: Alex Bennée
--
Alex Be
On 5/24/23 07:54, Philippe Mathieu-Daudé wrote:
When multiple QOM types are registered in the same file, it
is clearer and simpler to use the the DEFINE_TYPES() macro.
Add a rule to checkpatch.pl to suggest using DEFINE_TYPES()
instead of type_init() / type_register_static().
Suggested-by: Dani
On 5/24/23 06:35, Wu, Fei wrote:
On 5/23/2023 8:45 AM, Richard Henderson wrote:
On 5/18/23 06:57, Fei Wu wrote:
+void HELPER(inc_exec_freq)(void *ptr)
+{
+ TBStatistics *stats = (TBStatistics *) ptr;
+ tcg_debug_assert(stats);
+ ++stats->executions.normal;
+}
...
+static inline void
Hi, Zhenzhong,
On Tue, May 23, 2023 at 04:07:02PM +0800, Zhenzhong Duan wrote:
> Commit 63b88968f1 ("intel-iommu: rework the page walk logic") adds logic
> to record mapped IOVA ranges so we only need to send MAP or UNMAP when
> necessary. But there are still a few corner cases of unnecessary UNMA
Change Hexagon maintainer from Taylor Simpson to Brian Cain
Put Taylor's gmail address in .mailmap
Signed-off-by: Taylor Simpson
---
MAINTAINERS | 2 +-
.mailmap| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1b6466496d..426d33f4cb 100644
I will be retiring from Qualcomm at the end of May, so I am placing
the maintainership in the very capable hands of Brian Cain.
Taylor Simpson (1):
Hexagon (target/hexagon) Change Hexagon maintainer
MAINTAINERS | 2 +-
.mailmap| 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--
2.2
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Wednesday, May 24, 2023 9:42 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; Marco Liebel (QUIC)
> Subject: [PATCH v2 2/2] Hexagon: fix outdated `hex_new_*` comments
>
> Some code comments refer to he
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Wednesday, May 24, 2023 9:42 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Brian Cain
> ; Marco Liebel (QUIC) ;
> Alessandro Di Federico ; Anton Johansson
> Subject: [PATCH v2 1/2] target/hexagon/*.py: clean up use
On 5/24/23 11:24, Lin Ma wrote:
> The query-named-block-nodes is only availabe for qmp, not support hmp yet.
>
> Lin
Ok, makes sense.
On 5/23/23 23:39, Fabiano Rosas wrote:
> From: João Silva
>
> The fstat call can take a long time to finish when running over
> NFS. Add a version of it that runs in the thread pool.
>
> Adapt one of its users, raw_co_get_allocated_file size to use the new
> version. That function is called via
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