On Fri, May 19, 2023 at 08:44:18PM +0530, Ani Sinha wrote:
>
>
> > On 17-May-2023, at 12:23 PM, Ani Sinha wrote:
> >
> > Biosbits avocado tests on gitlab has thus far been disabled because some
> > packages needed by this test was missing in the container images used by
> > gitlab
> > CI. Thes
The low level extract and deposit funtions provided by bitops.h are
used in performance critical places. It crept into target/ppc via
FIELD_EX64 and also used by softfloat so PPC code using a lot of FPU
where hardfloat is also disabled is doubly affected.
Normally asserts should be compiled out fr
If sphinx is present but the theme is not, mkvenv will print an
inaccurate diagnostic:
ERROR: Could not find a version that satisfies the requirement
sphinx-rtd-theme>=0.5.0 (from versions: none)
ERROR: No matching distribution found for sphinx-rtd-theme>=0.5.0
'sphinx>=1.6.0' not found:
• Pyth
Some scripts are invoked via the first "python3" binary in the PATH,
because they are executable and their shebang line is "#! /usr/bin/env
python3". To enforce usage of $(PYTHON), make them nonexecutable.
Scripts invoked via meson need nothing else, and meson-buildoptions.py
is already using $(PY
importlib.metadata is just as good as distlib.database and a bit more
battle-proven for "egg" based distributions, and in fact that is exactly
why mkvenv.py is not using distlib.database to find entry points: it
simply does not work for eggs.
The only disadvantage of importlib.metadata is that it
Do not use the rule in build.ninja, because the path to meson is hardcoded
in build.ninja and this breaks if meson moves (for example if the distro
meson suddenly becomes too old after an update).
Reported-by: Peter Maydell
Tested-by: Peter Maydell
Signed-off-by: Paolo Bonzini
---
Makefile | 6
Reintroduce the cmd_line.txt mangling to remove the sphinx_build option
when rerunning meson. The mechanism was removed in commit 75cc28648574
("configure: remove backwards-compatibility code", 2023-01-11) because
the fixups were obsolete at the time; however, the Meson deprecation
mechanism doesn
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest-template.yml | 4
scripts/archive-source.sh | 2 +-
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/.gitlab-ci.d/buildtest-template.yml
b/.gitlab-ci.d/buildtest-template.yml
index 7edb50b76035..c9f2e737c09a 1006
The following changes since commit f0b95ab6b8192d84338496a0b6fd8f2c08a4a3a8:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-05-18 07:52:12 -0700)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream-urgent
for you to
Since custom runners are not generally available, make it possible to
debug the differences between a successful and a failing build by
comparing the logs and the build.ninja rules.
Acked-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/custom-runners.yml | 4 +++-
1 file cha
On 20/5/23 17:15, Richard Henderson wrote:
On 5/20/23 06:15, BALATON Zoltan wrote:
On Sat, 20 May 2023, Peter Maydell wrote:
On Fri, 19 May 2023 at 15:19, Jonathan Cameron via
wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little end
Remove the locally defined load_atomic16 and store_atomic16,
along with HAVE_al16 and HAVE_al16_fast in favor of the
routines defined in atomic128.h.
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 2 +-
accel/tcg/ldst_atomicity.c.inc | 118 +++
No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.
Signed-off-by: Richard Henderson
---
Cc: qemu-s3...@nongnu.org
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
---
target/s390x/cpu.h | 3 --
target/s390x/helper.h
With FEAT_LSE2, load and store of int128 is directly supported.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-ldst.h | 53 --
1 file changed, 40 insertions(+), 13 deletions(-)
diff --git a/host/include/aarch64/host/atomic128-ldst.h
b/host/include/
Separates the aarch64-specific portion into its own file.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 2 +-
host/include/aarch64/host/atomic128-ldst.h | 49 ++
host/include/generic/host/atomic128-ldst.h | 57 +
include/qemu/atomi
Add cpuinfo.h for i386 and x86_64, and the initialization
for that in util/. Populate that with a slightly altered
copy of the tcg host probing code. Other uses of cpuid.h
will be adjusted one patch at a time.
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henderson
---
host/include/i386/h
Eliminate the CONFIG_USER_ONLY specialization.
Signed-off-by: Richard Henderson
---
Cc: qemu-s3...@nongnu.org
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
---
target/s390x/tcg/mem_helper.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/s390x/tcg/mem_helper.c b/
Use cpu_ld16_mmu and cpu_st16_mmu to eliminate the special case,
and change all of the *_data_ra functions to match.
Signed-off-by: Richard Henderson
---
Cc: qemu-s3...@nongnu.org
Cc: David Hildenbrand
Cc: Ilya Leoshkevich
---
target/s390x/tcg/mem_helper.c | 65 ++--
Silly typo: sizeof(16) != 16.
Fixes: e61f1efeb730 ("meson: Detect atomic128 support with optimization")
Signed-off-by: Richard Henderson
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 4ffc0d3e59..5e7fc6345f 100644
--- a/meson.b
Not only the routines in ldst_atomicity.c.inc need markup,
but also the ones in the headers.
Signed-off-by: Richard Henderson
---
host/include/generic/host/atomic128-cas.h | 12
host/include/generic/host/atomic128-ldst.h | 18 --
include/qemu/atomic128.h
Use cpuinfo_init() during init_accel(), and the variable cpuinfo
during test_buffer_is_zero_next_accel(). Adjust the logic that
cycles through the set of accelerators for testing.
Signed-off-by: Richard Henderson
---
util/bufferiszero.c | 126
1 file
Move the code from tcg/. The only use of these bits so far
is with respect to the atomicity of tcg operations.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/cpuinfo.h | 22 ++
tcg/aarch64/tcg-target.h| 6 ++-
util/cpuinfo-aarch64
Use __sync_bool_compare_and_swap_16 to control the loop,
rather than a separate comparison.
Signed-off-by: Richard Henderson
---
host/include/generic/host/atomic128-ldst.h | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/host/include/generic/host/atomic128-ldst.h
Use the CPUINFO_* bits instead of the individual boolean
variables that we had been using. Remove all of the init
code that was moved over to cpuinfo-i386.c.
Note that have_avx512* check both AVX512{F,VL}, as we had
previously done during tcg_target_init.
Reviewed-by: Peter Maydell
Signed-off-b
These symbols will shortly become dynamic runtime tests and
therefore not appropriate for the preprocessor. Use the
matching CONFIG_* symbols for that purpose.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 2 ++
host/include/generic/host/atomic128-ldst.h | 2
With CPUINFO_ATOMIC_VMOVDQA, we can perform proper atomic
load/store without cmpxchg16b.
Signed-off-by: Richard Henderson
---
host/include/x86_64/host/atomic128-ldst.h | 54 +++
1 file changed, 54 insertions(+)
create mode 100644 host/include/x86_64/host/atomic128-ldst.h
di
Perform the function selection once, and only if CONFIG_AVX512_OPT
is enabled. Centralize the selection to xbzrle.c, instead of
spreading the init across 3 files.
Remove xbzrle-bench.c. The benefit of being able to benchmark
the different implementations is less important than not peeking
into t
With the current structure of cputlb.c, there is no difference
between the little-endian and big-endian entry points, aside
from the assert. Unify the pairs of functions.
The only use of the functions with explicit endianness was in
target/sparc64, and that was only to satisfy the assert.
Signed
No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.
Signed-off-by: Richard Henderson
---
Cc: qemu-...@nongnu.org
Cc: Daniel Henrique Barboza
Cc: "Cédric Le Goater"
Cc: David Gibson
Cc: Greg Kurz
---
target/ppc/cpu.h
Signed-off-by: Richard Henderson
---
include/tcg/debug-assert.h | 17 +
include/tcg/tcg.h | 9 +
2 files changed, 18 insertions(+), 8 deletions(-)
create mode 100644 include/tcg/debug-assert.h
diff --git a/include/tcg/debug-assert.h b/include/tcg/debug-assert.h
Peter raised a good point about it not being ideal to mix inline assembly
into the middle of accel/tcg/ldst_atomicity.c. We now have a host-specific
structure in which to put those.
Additionally, Peter noticed that clang will incorrectly use a read-write
sequence for __atomic_load_16 on AArch64,
Place the CONFIG_AVX512BW_OPT block at the top,
which will aid function selection in the next patch.
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henderson
---
migration/xbzrle.c | 244 ++---
1 file changed, 122 insertions(+), 122 deletions(-)
diff
Create both atomic16_read_ro and atomic16_read_rw.
Previously we pretended that we had atomic16_read in system mode,
because we "know" that all ram is always writable to the host.
Now, expose read-only and read-write versions all of the time.
For aarch64, do not fall back to __atomic_read_16 even
Now that load/store are gone, we're always passing
PAGE_READ | PAGE_WRITE for RMW atomic operations.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 32 ++
accel/tcg/cputlb.c | 85 ++---
accel/tcg/user-exec.c | 8 +---
Atomic load/store of 128-byte quantities is now handled
by cpu_{ld,st}16_mmu.
Signed-off-by: Richard Henderson
---
accel/tcg/atomic_template.h | 61 +++
include/exec/cpu_ldst.h | 9 --
accel/tcg/atomic_common.c.inc | 14
3 files changed, 4 in
Separates the aarch64-specific portion into its own file.
Signed-off-by: Richard Henderson
---
host/include/aarch64/host/atomic128-cas.h | 43 ++
host/include/generic/host/atomic128-cas.h | 43 ++
include/qemu/atomic128.h | 55 +---
The entire contents of the header is host-specific, but the
existence of such a header is not, which could prevent some
host specific ifdefs at the top of the file for the include.
Add host/include/{arch,generic} to the project arguments.
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henders
Add a bit to indicate when VMOVDQU is also atomic if aligned.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
host/include/i386/host/cpuinfo.h | 1 +
util/cpuinfo-i386.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/host/include/i386/host/c
The items in migration_files are built for libmigration and included
info softmmu_ss from there; no need to also include them directly.
Reviewed-by: Juan Quintela
Signed-off-by: Richard Henderson
---
migration/meson.build | 1 -
1 file changed, 1 deletion(-)
diff --git a/migration/meson.build
On 5/20/23 06:15, BALATON Zoltan wrote:
On Sat, 20 May 2023, Peter Maydell wrote:
On Fri, 19 May 2023 at 15:19, Jonathan Cameron via
wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting
> On 20-May-2023, at 3:06 PM, Paolo Bonzini wrote:
>
>
>
> Il sab 20 mag 2023, 09:25 Ani Sinha ha scritto:
> 40c909f534e3f3cd2 from what I can see. It requires a full QEMU build in order
> to turn on CONFIG_IASL in bios-tables-test. At some point in the past, we
> could just install iasl
On 5/19/23 08:02, Philippe Mathieu-Daudé wrote:
Could it be clearer to add a 'icr_ie_mask' field in CPUTriCoreState,
initialized once in tricore_cpu_realizefn() and avoid this if/else/ in
translation here, simply using the initialized mask?
If its for use in the translator, put it in DisasConte
On Sat, 20 May 2023, Peter Maydell wrote:
On Fri, 19 May 2023 at 15:19, Jonathan Cameron via
wrote:
From: Ira Weiny
CXL has 24 bit unaligned fields which need to be stored to. CXL is
specified as little endian.
Define st24_le_p() and the supporting functions to store such a field
from a 32
On Fri, 19 May 2023 at 15:19, Jonathan Cameron via
wrote:
>
> From: Ira Weiny
>
> CXL has 24 bit unaligned fields which need to be stored to. CXL is
> specified as little endian.
>
> Define st24_le_p() and the supporting functions to store such a field
> from a 32 bit host native value.
>
> The
Test if the audio subsystem can handle extreme up- and down-
sampling ratios like 44100/1 and 1/44100. For some time these
used to trigger QEMU aborts. The test was taken from
https://gitlab.com/qemu-project/qemu/-/issues/71 where it was
used to demonstrate a very different issue.
Suggested-by: Ma
Reviewed-by: Frank Chang
On Fri, May 19, 2023 at 2:23 PM Tommy Wu wrote:
> When we receive a packet from the xilinx_axienet and then try to s2mem
> through the xilinx_axidma, if the descriptor ring buffer is full in the
> xilinx axidma driver, we’ll assert the DMASR.HALTED in the
> function : s
Il sab 20 mag 2023, 09:25 Ani Sinha ha scritto:
> 40c909f534e3f3cd2 from what I can see. It requires a full QEMU build in
> order to turn on CONFIG_IASL in bios-tables-test. At some point in the
> past, we could just install iasl and rerun the test and it would discover
> iasl in the path if CONF
> On 19-May-2023, at 10:43 PM, Paolo Bonzini wrote:
>
> On Thu, May 18, 2023 at 1:02 PM Ani Sinha wrote:
>>> Can we split this variable out to config-test.h maybe?
>>> Then you can reconfigure with a different iasl and QEMU
>>> will not be rebuilt, just the tests.
>>
>> TBH, it looks more an
Hi
On Thu, May 18, 2023 at 4:03 PM Albert Esteve wrote:
> Add hash and an equal function to uuid module.
>
> Add a couple simple unit tests for new functions,
> checking collisions for similar UUIDs in the case
> of the hash function, and comparing generated UUIDs
> for the equal function.
>
> S
Currently the meson based QEMU build process locates the iasl binary from the
current PATH and other locations [1] and uses that to set CONFIG_IASL which is
then used by the test.
This has two disadvantages:
- If iasl was not previously installed in the PATH, one has to install iasl
and rebuil
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